JPS6085494A - Control system of memory device - Google Patents

Abstract

PURPOSE:To prevent destruction of the content of memory by synchronizing initial setting signals for column address strobe signals and row address strobe signals supplied to a metal oxide film semiconductor random access memory by a fresh request signal. CONSTITUTION:A POW-READY signal is shifted, and when there is RFST signal of refresh signal in minimum 16 mus (refresh interval), output of FF-4 and FF-5 becomes on, and an AND gate circuit 6 can take logic. The AND gate circuit 6 is shifted by FF-7 to avoid competition of refresh action of P-RST signal by RFST signal. A CLK signal of FF-7 is a clock signal from the system side, and when competition occurs with refresh action in case of shifting by an FF-7, the output can be shifted by a flip-flop circuit. Accordingly, signals such as outside noise etc. are synchronized in fresh cycle. As the pulse width is confirmed, small width is neglected, and does not come in by mistake during refresh action. Thus, the content of memory of the metal oxide film random access memory is secured and destruction can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a control method for a storage device that guarantees and protects the storage contents of a metal oxide semiconductor random access memory of the storage device.

(Yama) Technology Background In recent years, with the need for expanded online database functions in the information processing industry, information processing equipment has become increasingly larger, more sophisticated, and faster. The development of semiconductor memories used in storage devices, which are the heart of information processing equipment, has been remarkable, and dynamic metal oxide semiconductor random access memories with high density and high speed access are contributing to the development of the information processing industry. . Dynamic type metal oxide film semiconductor random access memory has a higher degree of integration than normal static type metal oxide semiconductor random access memory, and consumes less power, so it is suitable for writing various control programs and data for information processing equipment. /Used as read memory. Furthermore, this write/read operation is performed using a row address strobe signal (hereinafter abbreviated as RAS) and a column address strobe signal (hereinafter abbreviated as CAS).

With the advent of memory chips that operate in nibble mode, write/read operations have become increasingly faster.

No matter how fast this write/read operation is.

For RAS/CAS, etc., if the time regulations are not satisfied, the information in the dynamic metal oxide semiconductor random access memory (hereinafter referred to as MO3RAM) will not be reproduced, and the contents of MO3RAM will not be guaranteed. There are two problems.

(C) Prior Art and Problems A conventional circuit for creating a RAS signal in this type of MO5RAM will be described. FIG. 1 shows a block diagram of a RAS signal generation circuit. 1 is a logical sum circuit.

2 is a flip-flop circuit (hereinafter abbreviated as FF-2)
, 3 is an OR circuit, and the RDST signal, WTST signal, and IIFST signal are read/write/refresh operation start signals, respectively, and are input to the OR circuit 1.

The RFST signal is normally transmitted at an interval of once every 16 us. The output signal of OR circuit 1 is input to FF-2. The Toff signal is a timing signal that determines the trailing edge of the RAS signal, and the P-R3T signal is an initial setting signal for FF-2.
A pulse signal for initial setting is issued when a specified voltage is reached after a certain period of time after the device is powered on. The Toff signal and the P-R5T signal are input to the OR circuit 3. The output signal of the OR circuit 3 is input to PF-2. If the output signal of OR circuit 1 or OR circuit 3 is input to FF-2.

Send RAS signal from FF-2 to MO5RAM (not shown).

Or stop.

FIG. 2 shows a time chart of the RAS signal generation circuit, and throughout the diagrams, the same signal contents are indicated by the same symbols as in FIG. 1.

The operation of the RAS signal generation circuit will be explained using the timings shown in FIG. 1 and FIG. 2. RDST signal at timing RDST (
Or the WTST signal and RFST signal are the same, but if the RDST signal is received by the OR circuit 1, the OR circuit 1 turns on and sends the output signal to the FF-2. Then, FF~2 turns on and sends the RAS signal at timing RAS to MO3RAM.

The operation of FF-2 continues until the reset signal of the Toff signal is input, and the timing ToffT:Toff signal is input to the OR circuit 3 and +fi! The output signal from the logic and dowa circuit 3 is sent to FF-2, and the timing RAS'
7: Reset the RAS signal. This timing RAS
The A section of is the specified time width of RAS.

In the conventional RAS signal generation circuit, if the P-R5T signal is received by mistake after receiving this RDST signal and FF-2 is reset, the RAS will not be able to satisfy the specified time width A and readout of the memory contents will not be guaranteed. . Also.

This erroneous P-R3T signal can also occur due to noise signals caused by external factors, so after the power supply to the storage device has been confirmed and the memory contents have been determined, the P4tST signal may be generated asynchronously due to a malfunction due to external noise, etc. In some cases, the memory contents may be destroyed. Therefore.

Conventional RAS signal generation circuits have had drawbacks such as the memory contents cannot be guaranteed or the memory contents may be destroyed.

(di) Object of the Invention The present invention aims to solve the drawback that the conventional storage contents cannot be guaranteed.

(el) Structure of the Invention The above object is to provide a memory device using a metal oxide film semiconductor random access memory that requires a refresh operation at regular intervals in order to retain memory contents, in which a row address is supplied to the metal oxide film semiconductor random access memory. Initial setting signals for strobe signal and column address strobe signal.

This is achieved by the present invention, which is configured to synchronize with the refresh request signal.

That is, focusing on the fact that the refresh operation signal is normally sent out at an interval of once every 16 us, the initial setting signal for the 3-row address strobe signal is synchronized with the refresh operation request signal, and signals such as external noise are also transmitted in this manner. By configuring the structure to be synchronized with a refresh operation request signal, signals such as external noise are suppressed, the storage contents of the metal oxide film random access memory are guaranteed, and storage device control prevents destruction of the storage contents. It provides a method.

(fl Embodiment of the Invention An embodiment of the present invention will be described below. FIG. 3 shows a circuit configuration block diagram of a P-R3T signal generation circuit according to the present invention. 4 is a flip-flop circuit (hereinafter abbreviated as FF-4). RF
The ST signal is a start signal for refresh operation and is normally 1.
FF-4 and FF- are sent out at intervals of once every 6us.
It is input to the clock terminal of No. 5.

The CLK signal is a clock signal on the system side. P-1 of the P-R5T signal generation circuit according to the present invention? The sT signal is.

The signal is input from the output terminal of FF-7 to the OR circuit 3 of the RAS signal generation circuit shown in FIG.

In the circuit configuration shown in Fig. 3, if the POW-READY signal is shifted and the refresh signal RFST signal is present for a minimum of 16 us (refresh interval), F
The outputs of both F-4 and FF-5 are turned on, and the AND gate circuit 6 becomes logical. Tend gate circuit 6 is P-R5
The T signal is shifted by FF-7 so that there is no refresh operation conflict with the RFST signal. FF-7's C
The LK signal is a clock signal from the system side, and if a conflict with a fresh operation occurs in shift l- by one FF-7, its output can be further shifted by a flip-flop circuit.

Therefore, signals such as external noise are also synchronized in the refresh cycle, and their pulse widths are also checked, and as a result, signals with small widths are ignored. Furthermore.

No more accidental entry during refresh operation.

P-1? A control method for a storage device that provides a P-R5T signal generation circuit that suppresses erroneous signals in ST signals from external factors such as noise, and prevents sending erroneous P-R3T signals to a RAS signal generation circuit. It is.

Above, we have explained the RDST signal input to the OR circuit 1 as a typical example, but the WTST signal, RFST
Needless to say, the stored contents are similarly guaranteed even when a signal is input.

(Kouzu: As described in detail of the invention, the initial setting signal for the two-row address strobe signal is synchronized with the refresh operation request signal, and the configuration is such that signals such as external noise are also synchronized with this refresh operation request signal. By adopting the circuit configuration of the present invention.

This has the effect of suppressing signals such as external noise, ensuring the memory contents of the metal oxide film random access memory, and preventing destruction of the memory contents.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration block diagram of a conventional row address strobe signal generation circuit, FIG. 2 is a time chart diagram of a conventional row address strobe signal generation circuit, and FIG. 3 is a circuit configuration of an initial setting signal generation circuit according to the present invention. A block diagram is shown. In the drawing, 1 and 3 are OR circuits, 2, 4゜5.7 are flip-flop circuits, 6 is an AND gate circuit, RD
The ST signal is a read operation start signal, the WTST signal is a write operation start signal, the RFST signal is a refresh operation start signal, the Toff signal is a timing signal that determines the trailing edge of the row address strobe signal, and the P-R5T signal is an initial setting signal. , POW-R1! The ADY signal indicates a power supply confirmation signal, and the CLK signal indicates a system clock signal. Rod 1 Mouth^ro) Bi 2 Daily collection 32

Claims (1)

[Claims] In a storage device using a metal oxide film semiconductor random access memory that requires refresh operations at regular intervals to retain memory contents, initialization of the row address strobe signal and column address strobe signal supplied to the metal oxide film semiconductor random access memory is 1. A control method for a storage device, characterized in that a setting signal is synchronized with the refresh request signal.