JPS6077512A - Aft circuit of pll synthesizer system television receiver - Google Patents

Aft circuit of pll synthesizer system television receiver

Info

Publication number
JPS6077512A
JPS6077512A JP58186246A JP18624683A JPS6077512A JP S6077512 A JPS6077512 A JP S6077512A JP 58186246 A JP58186246 A JP 58186246A JP 18624683 A JP18624683 A JP 18624683A JP S6077512 A JPS6077512 A JP S6077512A
Authority
JP
Japan
Prior art keywords
circuit
counter
aft
range
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58186246A
Other languages
Japanese (ja)
Inventor
Tsuneo Aihara
相原　常男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp, Pioneer Electronic Corp filed Critical Pioneer Corp
Priority to JP58186246A priority Critical patent/JPS6077512A/en
Publication of JPS6077512A publication Critical patent/JPS6077512A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/02—Automatic frequency control
    • H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
    • H03J7/06—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers
    • H03J7/065—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers the counter or frequency divider being used in a phase locked loop

Landscapes

  • Television Receiver Circuits (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To receive surely a broadcast signal by setting a maximum value of a programmable counter to a narrower range from a center frequency in a capture range of an AFT circuit so as to bring the shift of an AFT voltage into the inside of the AFT capture range. CONSTITUTION:The PLL synthesizer system is adopted to an electronic tuner section of a TV receiver, and the system consists of a reference frequency oscillator 11, a phase comparator 10, an LPF9, a VCO8, a prescaler 7 and a programmable counter 6. A specific data is inputted to the counter 6 from a CPU5 via a channel data setting device 4 so as to set a 1/N value of the counter 6. An S curve voltage from an AFT circuit 1 of a video intermediate frequency section is fed to the counter 6 via an A/D converting circuit 2 and a discriminating circuit 3 at the AFT operation of the receiver. Then the maximum value of the counter 6 is set to the narrower range from the center frequency in the capture range of the circuit 1 so as to receive surely the broadcast signal.

Description

【発明の詳細な説明】 本発明は１〕シしシンセサイｆｌＪ式テレビ受像機のΔ
「゛１−回路に関するちのであり、八Ｆ「電１Ｆが７７
’れ（も、放送４３号を確実に受信できるようにし／Ｓ
ものぐある。DETAILED DESCRIPTION OF THE INVENTION The present invention provides (1) Δ
``゛1-It is related to the circuit, and the 1st floor of the 8th floor is 77
'Re(Also, make sure to receive Broadcast No. 43/S
There are things.

第゛１図は本発明の実施例を示し、Δ１：］゛回路の制
御信号によりプログラマブルカウンタが標準放送チャン
ネル周波数に対して所定の範囲の」−下にΔＦＴ動作が
可能なＰＬＬシンヒリ゛イザのＡ　Ｆ　Ｔ部及びＰＬＬ
郡である。FIG. 1 shows an embodiment of the present invention, in which the control signal of the circuit causes the programmable counter to operate within a predetermined range with respect to the standard broadcast channel frequency. AFT section and PLL
It is a county.

放送を受信する動作はＣＰ　ＬＪ　５からチャンネルデ
ータ設定器４に特定の放送チャンネルのデータが入力し
、プログラマブルカウンタ６の１／Ｎｉｌを設定する。In the operation of receiving a broadcast, data of a specific broadcast channel is input from the CP LJ 5 to the channel data setter 4, and 1/Nil is set in the programmable counter 6.

プログラマブルカウンタ６は電ｆチューブ内の局部発信
器である電圧制御ｌ１発振器（ＶＣＯ）８の発信周波数
をプリスケーラ７で１／Ｍされたものをさらに１／Ｎに
分周し、位相比較器１０に送る。位相比較器１０は前記
プログラマブルカウンタ６の出力信号と１３　Ｑｌ−周
波数梵振器１１の出力どを位相比較し、出力ｊ’ｆｆｔ
　；Ｃ雷Ｊ［は［Ｉ−パスフィルタ９を通って電１１制
御Ｉ光振器８を制御づる。A programmable counter 6 divides the oscillation frequency of a voltage-controlled l1 oscillator (VCO) 8, which is a local oscillator in the electric f-tube, by 1/M by a prescaler 7, and then divides the frequency by 1/N, and sends the frequency to a phase comparator 10. send. A phase comparator 10 compares the phases of the output signal of the programmable counter 6 and the output of the Ql-frequency oscillator 11, and outputs j'fft.
;C lightning J[ passes through I-pass filter 9 to control electricity 11 and I-optical oscillator 8.

△に−Ｉ！ＩＪＪ作は映像中間周波数（＋）　Ｉ　Ｅ　
）のＡ［二Ｔ回路１からのＳカーブ電圧をΔ／［）変換
回路２及び判定回路３によりブ１コグラマ１ルカウンタ
６を放送周波数の標準値に対して上下に動かりこと（゛
周波数を可変できる。△ni-I! IJJ works have video intermediate frequency (+) I E
) of the S curve voltage from the two-T circuit 1 by Δ/[) conversion circuit 2 and judgment circuit 3 to move the block diagram counter 6 up and down with respect to the standard value of the broadcasting frequency. Can be changed.

フレビ受像機のＰＩＦ部ＡＦ王回路１で得られるＳカー
）電圧は第２図に示づように、映像キャリｊ′と音声キ
ャリアの２波のため、中間周波数の１−側の範囲が狭く
、下側の範囲が広い。その周波数は＋側８００　Ｋ　ｌ
−１ｚ　、下側２　Ｍ　ＨＺぐらいである。As shown in Figure 2, the S voltage obtained in the AF circuit 1 of the PIF section of the Frevi receiver is two waves, the video carrier j' and the audio carrier, so the range on the 1- side of the intermediate frequency is narrow. , the lower range is wide. Its frequency is + side 800K l
-1z, the lower side is about 2 MHz.

本発明の要旨はＡ　Ｆ　’ｌ−動作を含むヂューナシス
ｊムのうｌう、ｌ］ｌＬシンセ１ノ゛イザ方式での、Ａ
Ｆ［電ＪＦの１１？ブヂＩ７−レンジ（第２図のＡ　Ｆ
　Ｔ’　１３心周波数に対して斜線の範囲）内に、プロ
グラマゾルカウンタの分周比の可変範囲の最大値を設定
りることである。本来ＰＬＬシンレ１少イザ方式は電子
チー１−ノの局部発信周波数のドリフ１〜がない１、：
め、Δ１：１−機能は必要ないが、Ｖ　１−　Ｒやブレ
ビゲーム等の［＜［：出力が、標準デーＩンネル周波数
に２４　Ｌ、　（す“れＣいる場合には、テレビ受像機
のＡ　Ｆｌ−により追従しＣやる必要があるためｆ］加
Ｊる必要がある。そこで、かかる設定を行なうことによ
り、プログラマ１ルカウンタ６のＡＦ　ｌ’動作範囲を
ＡＦＴキ１７プヂヤーレンジ内にすることにより大幅に
改善できる。つまり、無信号（無放送）　Ｉｋ’７や伯
の放送のスプリアス等によりＡＦＴ電圧がずれて受信周
波数がｆれでしまっても、そのずれがＡＦＴギャブヂ１
７−レンジ内にあるため、放送信号をつかまえることが
できるものである。The gist of the present invention is that the A F'l-operation is included in the syntax, and the A
F [Electric JF's 11? Buji I7-Range (A F in Fig. 2)
The maximum value of the variable range of the frequency division ratio of the programmer sol counter is set within the shaded range relative to T'13 heart frequency. Originally, the PLL synchronization system eliminates the drift of the local oscillation frequency of the electronic chip.
Therefore, the Δ1:1-function is not necessary, but if the output is 24L, Since it is necessary to follow up with A Fl- of A and perform C, it is necessary to add f]. Therefore, by making such settings, the AF l' operating range of programmer 1 counter 6 can be brought within the AFT key 17 pressure range. In other words, even if the AFT voltage deviates due to no signal (non-broadcasting) Ik'7 or spurious broadcasting, etc. and the receiving frequency becomes f, the deviation will be
Since it is within the 7-range, it can catch broadcast signals.

以上のように本発明によれば、放送局の送信が始まる前
にヂレンネルを設定しＣ放送の始まるのを待つ持受り受
信の時、スプリアス等が存在し、ＡＦＴ電圧がずれ−Ｃ
しまって受信周波数がずれいても確実に放送信号をキュ
ッヂすることができる。As described above, according to the present invention, when a broadcast station sets the de-channel before the broadcast station starts transmitting and waits for the start of the C broadcast, spurious etc. exist and the AFT voltage deviates -C.
Even if the reception frequency is shifted due to storage, the broadcast signal can be reliably received.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に係る実施例を示づ図、第２図は第１図
Δ］−１回路の電ＨＥ特性を示す図である。 １・・・・・・ΔＦ］−回路 ２・・・・・・Δ／１）変換回路 ３・・・・・・判定回路 １・・・・・・チャンネルデータ設定器５・・・・・・
ＣＰ　Ｕ ６・・・・・・ブＵグラマプルカウンタ７・・・・・・
プリスケーラ ８・・・・・・電１（制御発振器 ［）・・・・・・ローパスフィルタ １０・・・・・・位相比較器 １１・・・・・・基準周波数発振器 特許出願人 バイＡニア株式会FIG. 1 is a diagram showing an embodiment according to the present invention, and FIG. 2 is a diagram showing the electric HE characteristics of the Δ]-1 circuit shown in FIG. 1...ΔF]-circuit 2...Δ/1) Conversion circuit 3...Judgment circuit 1...Channel data setter 5...・
CPU 6...Bugram pull counter 7...
Prescaler 8...Electric 1 (controlled oscillator [)...Low pass filter 10...Phase comparator 11...Reference frequency oscillator Patent applicant Buy A Near Stock Association

Claims (1)

【特許請求の範囲】[Claims] １）１」−シンＬ７ナイザ方式テレビ受！＆機において
、所定の放送ヂＶンネルを受信するだめの局部発振周波
数を１ｉノると共に、前記放送チャンネルの標準周波数
に対してＡＩ＝Ｔ回路からの制御信号にＪ：り受信周波
数を土トに可変可能なプログラマブルカウンタを有し、
ＡＦＴ回路のキャプチＶ−レンジ内にａハノる中心周波
数より狭い側の範囲に前記ブ■グラマブルノＪウンタの
可変範囲の最大値を設定しｌこことを特徴とりるＰ　Ｌ
　Ｌシンレリイ’ｆ　７’５式テレビ受像機のＡ　Ｐ　
Ｉ−回路。1) 1” - Shin L7 Nizer system TV reception! In the & machine, the local oscillation frequency for receiving a predetermined broadcasting channel is multiplied by 1i, and the receiving frequency is set to It has a programmable counter that can be changed to
The maximum value of the variable range of the programmable counter is set to a range narrower than the center frequency within the capture V range of the AFT circuit.
L Shinrely'f 7' Type 5 TV receiver A P
I-Circuit.
JP58186246A 1983-10-05 1983-10-05 Aft circuit of pll synthesizer system television receiver Pending JPS6077512A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58186246A JPS6077512A (en) 1983-10-05 1983-10-05 Aft circuit of pll synthesizer system television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58186246A JPS6077512A (en) 1983-10-05 1983-10-05 Aft circuit of pll synthesizer system television receiver

Publications (1)

Publication Number Publication Date
JPS6077512A true JPS6077512A (en) 1985-05-02

Family

ID=16184903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58186246A Pending JPS6077512A (en) 1983-10-05 1983-10-05 Aft circuit of pll synthesizer system television receiver

Country Status (1)

Country Link
JP (1) JPS6077512A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257552A2 (en) * 1986-08-20 1988-03-02 Mitsubishi Denki Kabushiki Kaisha Television signal selection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257552A2 (en) * 1986-08-20 1988-03-02 Mitsubishi Denki Kabushiki Kaisha Television signal selection device

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