JPS6074847A - General polling system - Google Patents

Abstract

PURPOSE:To shorten the polling time by generating just one polling instruction of a host controller, to perform the transfer of data among all stations just with the polling of one time. CONSTITUTION:An instruction circuit 7 has polling instructions to all stations under the control of a processing controller 1 and applies them to an S/P converting circuit 6. This instruction is sent one bit by one bit to a serial data generating circuit 9 from the circuit 6, then to all stations via a driver 11 and a connection terminal 12. A buffer memory 2 is connected to the controller 1, and a serial data detecting circuit 8 connected to a receiver 10 is connected to the memory 2 via an S/P converting circuit 5. The output of the circuit 8 is connected to the controller 1 via a tail word detecting circuit 4. Then the data transfer is performed among all stations just with the polling of one time. In such a way, the polling time is shortened.

Description

Detailed Description of the Invention (1) Technical Field of the Invention In the present invention, a plurality of stations are connected to a host controller in a serial manner, and after polling, data is transferred over a serial interface connecting the host controller and the stations. This paper is about an efficient polling method in various systems.

(2) Prior art and problems Conventionally, in the system described above, when data is transferred using the polling method, there is a host system that prevents responses from each station from colliding on the serial interface. The controller polls only one of the multiple stations, and after receiving a response from that station, polls the next station. Polling was performed separately.

In this type of system, the host controller must issue polling commands for the number of stations connected to the host controller, and since time is required for the response, all stations The drawback is that it takes a long time to complete one round of polling. Furthermore, this has the disadvantage that the frequency of polling each station is restricted and the efficiency of data transfer is not good.

(3) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a system in which a host controller issues a polling command t-1 times to enable responses from all stations owned by the host controller. The purpose of this invention is to provide a method that reduces the time required for polling and improves the efficiency of data transfer.

(4) Structure of the Invention According to the present invention, the object is to provide a system in which a plurality of stations are connected to a host controller in an interlocking manner and data is transferred by polling. The host controller is provided with a backup memory having an area corresponding to each station, and each station is provided with a buffer memory capable of storing transmission data of other stations connected via the station. This is achieved by a simultaneous polling method, which is characterized in that polling is performed simultaneously, and a station address is assigned to each series of data to transfer the data.

(5) Embodiment of the invention FIG. 1 is a block diagram of a host controller according to an embodiment of the invention, in which 1 is a processor, 2 is a backup memory, 3 is a counter, 4 is a tail word detection circuit, and 5.6 10 represents an S/P conversion circuit, 7 a command circuit, 8 a serial data detection circuit, 9 a serial data generation circuit, 10 a receiver, 11 a driver, and 12 a connection terminal to the station.

FIG. 2 is a block diagram of a station according to an embodiment of the present invention, in which 13 is a control circuit, 14.15 is an S
/P conversion circuit, 16 is a serial data generation circuit, 17 is a serial data detection circuit, 18 is a driver, 19 is a receiver, 20 is a switch, 21 is a connection terminal to a host controller or a previous station, 22 is to a subsequent station 23 is a buffer memory, 24 is a buffer memory read counter, 25 is a buffer memory own write counter, 26 is a tail word detection circuit, 27 is a transfer path BUSY detection circuit, and 28 to 30 are selectors. There is.

At the time of polling, in the host controller, under the control of the processor l shown in FIG.
send to

The P/S conversion circuit 6 sends this command bit by bit to the serial data generation circuit 9, and the data is sent out as data shaped for transfer to the station via the driver 11, the connection terminal 12f.

On the station side, the data is sent to the subsequent station by closing the switch 20 in FIG.
The serial data detection circuit 17 receives “1#, @I
6 Determine # and send it to the S/P conversion circuit 15.

The S/P conversion circuit 15 accumulates the data sent one bit at a time, and when it becomes one word, sends it to the control circuit 1s. When control 00 path 13 identifies that it is a polling command, it sends a transfer path BUSY detection circuit 27 to check whether another station is using the transfer path, and if it is free, P/S conversion is performed. The response data is sent to the circuit 14, and the selector 28 is switched to the P/S conversion circuit 14 side. The P/S conversion circuit 14 sends response data bit by bit to the serial data generation circuit 16, and the data is sent to the host controller via the driver 18 and connection terminal 21 as data shaped for transfer. Ru. At this time, the control circuit 13 opens the switch 20, switches the seventh receiver 30 to the buffer memory write counter 25 side, and switches the selector 29 to the serial data detection circuit 17 side, and transmits data from the subsequent station. The received data is stored in the buffer memory 23 bit by bit.

When the control circuit 13 has finished transmitting all the response data, it checks the backup memory write counter 25, and if it is not "O", it assumes that data has been transmitted from the subsequent station, and sets the selector 30 to the buffer memory. Selectors 28 and 29 are placed on the memory read counter 24 side.
The switch is switched to the Q serial data generation circuit 16 side, and the contents of the backup memory 23 are sequentially transmitted to the host controller starting from address 1. If there is transmission data from a subsequent station during the transmission, the selector 29 and the ao
The transmission data is stored in the buffer memory 23 in duplicate. When sending out the contents of the buffer memory 23, the buffer memory e-read counter 24 and the buffer memory
If the values of the write counter 25 become the same and the transfer path is not in use, the control circuit 13
0 is closed and the data sent from the subsequent station is sent directly to the host controller (in this case, the data is not stored in the buffer memory 23).

When the control circuit 13 attempts to return response data, if another station is transmitting data to the host controller, the transfer path BUSY detection circuit detects that the transfer path is in use. In times like this,
The tail word indicating the end of transmission is detected by the tail word detection circuit 2.
Data transmission is suspended until detected by 6.

On the other hand, on the host controller side, after sending out a polling command, the counter is cleared to make it ready to accept data from the station. When data is sent from one of the stations, the receiver 10 receives it, the serial data detection circuit 8 determines '1' and 0#, and the ts/P conversion circuit 5 assembles it into one word of parallel data. .

The parallel data is written into the buffer memory 2 using the station address field and the value of the counter 3 as an address (the counter 3 has a counter corresponding to each station). Further, the data from the station is counted up by the counter 3 and written into the buffer memory 2 one after another. When a tail word is sent from the station, it is detected by the tail word detection circuit 4 and notified to the processor 1. As a result, the processor 1 reads out a series of data from the station from the buffer memory 2 and processes the data.

Since each data has a station address section, the host controller manages each station's data in the buffer memory, so there is no need to issue a polling command for each station.

(6) Effects of the Invention As explained in detail above, in a system according to the present invention, in which a plurality of stations are connected to a lever, a host controller, and a serial interface in a serial interface, and data is transferred by a polling method. Since data can be transferred to and from all stations by one polling, the time required for polling is shortened and the transfer path can be used efficiently, which is very effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a host controller according to one embodiment of the present invention, and FIG. 2 is a block diagram of a station according to one embodiment of the present invention.

Claims (1)

[Claims] In a system in which a plurality of stations are connected to a host controller in a chain and data is transferred by polling, the host controller is provided with a backup memory having an area corresponding to each station, and the station is connected to the station via the station. A buffer memory capable of storing transmission data from other stations connected to the station is provided, and each station is polled simultaneously, and each data set is assigned a station address and data is transferred. Features simultaneous polling method.