JPS6074738A - Satellite broadcast receiver - Google Patents

Abstract

PURPOSE:To attain error correction even with the presence of a 1-bit error in a range bit or voice data or the like by providing a BCH single error correction double error detection code decoding circuit before a de-inteleave device of the voice signal. CONSTITUTION:The BCH (7, 3) SEC.DED code decoding circuit 10 correcting only 1-bit error in the range bit or the like in the received voice data and applying the result to a storage circuit 1 is connected to a satellite broadcast receiver having the storage circuit 1 de-interleaving the received voice data, the 1st BCH (63, 56) single error correction SEC double error detection DED code decoding circuit 2 correcting the error of the de-interleaved reception voice data and the 2nd BCH (7, 3) SEC.DED code decoding circuit 3 correcting the error of the range bit or the like extracted from the output of the circuit 2. The circuit 10 corrects the error at syndrome F(1)not equal to 0, F(alpha)not equal to 0 of the range bit or the like of the input voice data and corrects the error at the 2nd time only at syndrome F(1)=0, F(alpha)=0 and outputs the result.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a satellite broadcasting receiver for receiving PCM audio data of television satellite broadcasting.

(Prior art) Received audio data of 12 GHz band television satellite broadcasting includes audio data, independent data, and range bits, and is BCH (Boss-Chaudhuri-Hoc).
quenhem) (63,56) Single Error Correction (SEC
)・Double error detection (DED) is encoded), and the range bit is BCI (7, 3) 5EC- in addition to the above.
DED encoded.

In a conventional satellite broadcasting receiver, received audio data is decoded by a storage circuit τ after being supplied with acoustic data and deinterleaved, as shown in FIG.
- BCH (63, 56) SEC to decode DED code -
The data is supplied to the DED code decoding circuit 2 for error correction, and then audio data, independent data, and test data thereof (sound data, independent data, and test data thereof are referred to as audio data, etc. in this specification) are extracted. Output range bit and its inspection data (range bit and its inspection data are referred to as range bit etc. in this specification)
BCH (7, 3) BWC-DID code decoding circuit 3
The data is supplied to the computer, and the data is output after error correction.

However, 5c) I (63# s 6 ) 5Ec-Di
The D code is subjected to single error correction in the decoding circuit 2, but 2-bit errors cannot be corrected. Further, when an odd number of bits are erroneous (three or more), the probability of erroneous correction is extremely high as a result of computer simulation.

Therefore, for example, as shown in FIG.
If there is an error between the range bit, etc. and 1 bit in the audio data, etc., as shown by the X mark, in a 3-bit 1 block, that is, at the same line stop on the incremental matrix, the error cannot be corrected. was there.

(Object of the invention) In view of the above, the present invention is based on 63 pits.
In the block, range bit etc. and 1 in audio data etc.
An object of the present invention is to provide a satellite broadcasting receiver capable of correcting errors even when there are errors in bits.

(Structure of the Invention) The present invention includes a dinkeep prefix for deinterleaping received audio data, a first BCHSED/DED code/decoding circuit for error correction of the deinterleaved received audio data, and a first BCHID - a second BCHSEC-DED code decoding circuit for correcting errors such as range bits extracted from the output of the DED code decoding circuit; The present invention is characterized by comprising a third BCH8EC-DED code decoding circuit which corrects only one-pit error in range bits, etc., and supplies the output to a deinterleague device.

Hereinafter, the present invention will be explained by examples.

FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 3, the same components as those shown in FIG. 1 are designated by the same reference numerals.

One embodiment of the present invention corrects only 1-piF errors in range bits, etc. in received audio data supplied to the input terminal IN between the input terminal IN and the memory circuit 1 serving as a deinterference device. and supplies the output to the storage device 1 B
Cf((7,3) SgC-DED code decoding circuit 10
is connected.

BCH (7, 3) 5EC-DID encoding circuit 1O converts syndrome A such as range bits of input audio data.
Calculate F (1) and F ([1) and calculate F (1) ”
−ZoKatsu F($(0) Calculate the syndromes F(1) and F@ of range bits etc. that were incorrectly corrected when it is 0, and this second syndrome is F(1) =
0 Outputs error-corrected range bits, etc., audio data, etc. only when F (b) = 0, and when the second syndrome is other than F (1) = 0 and F) = 0. It is configured to output the supplied received audio data as is.

FIG. 4 is a block diagram showing the configuration of the ncIt (7#a) SEC-Dgo code decoding circuit 10.

BC3I (7, 3) 5EC-DID code decoding circuit 10 receives the received audio data before dink creep supplied to the input terminal IN to the calculation circuit 11. It is supplied to the calculation circuit 12 and the delay circuit 14 for the period of 8 bits.

Generating polynomial for range bits in received audio data〇(,)
is G 6ri = X'+X3+X2+1 = (x+1)
It is given by (:'+x+1).

The calculation circuit 11 calculates received audio data (R(X) in polynomial expression)
) divided by (X+1), net, syndrome F(1
) and generates a binary output corresponding to the syndrome F(1).The calculation circuit 12 divides the received audio data by the primitive polynomial (x3+x+1) and calculates V7do0.
-4F) [α is the root of the primitive polynomial (x'+x-1-1)].

The output of the calculation circuit 12 is the detection output of whether the output of the calculation circuit 12 (from the output of the calculation circuit 12 to the syndrome F) is 0'', and the output of the syndrome F.
D) When #o, the signal is supplied to the detection circuit 13 which generates an error correction output for the bit corresponding to the syndrome F←).

The output of the calculation circuit 11 and the detection output of the detection circuit 13 are supplied to an exclusive OR circuit 15. Exclusive OR circuit 15
The output of is supplied to the latch circuit 16 and latched by the latch circuit 16. The latch circuit 16 outputs a latch output EP obtained by latching the output of the exclusive OR circuit 15, and its inverted output EP.

The inverted output EP of the latch circuit 16 and the correction output of the detection circuit 13 are supplied to an AND gate circuit 18, and the output of the AND/DART circuit 18 and the output of the delay circuit 14 are supplied to an exclusive OR circuit 19 as a power correction means. The exclusive OR circuit 19 inverts and corrects the error bits of the received data using the output of the AND/DART circuit 18.

The output of the exclusive OR circuit 19 is supplied to a delay circuit 20, a calculation circuit 21, and a calculation circuit 22 for an 8-bit period. The calculation circuit 21 converts the output of the exclusive OR circuit 19 into (x+1
), the calculation circuit calculates the syndrome F(1) and generates a binary output corresponding to the syndrome F(1), and has the same configuration as the calculation circuit 11. ! The i calculation circuit 21 converts the output of the exclusive OR circuit 19 into a primitive polynomial (x'
This calculation circuit calculates the syndrome F@ by dividing by +x+1), and is configured similarly to the calculation circuit 12.

F■ calculated by the calculation circuit 22, that is, the calculation circuit 21
The output of F is supplied to a detection circuit 23 which generates a detection output as to whether F is IO'' or not.

On the other hand, the latch output EP of the latch circuit 16 is supplied to a delay circuit 17 for an 8-bit period, and the output of the delay circuit 17, the output of the calculation circuit 21, and the detection output of the detection circuit 23 are supplied to the OR gate circuit 24. Ashi, or gate circuit 2
The output of 4 is supplied as one input of the or-dart circuit 25. The OR gate circuit 25 is supplied with a signal C which is at a high potential when the received audio data is not in the range bit or the like as the other input.

On the other hand, the output of the delay circuit 14 is supplied to a delay circuit 26 for an 8-bit period. The outputs of the delay circuits 20 and 26 are supplied to a selector 27, and the output of the OR gate circuit 25 is used as a selection signal to select the output of the delay circuit 20 or the delay circuit 2.
One of the outputs of 7 is selected according to the output of the or-dart circuit 25 and is supplied to the memory circuit 1. Here, the selector 27 is set to select and output the output of the delay circuit 20 when the output of the OR/DART circuit 25 is at a low potential.

Note that the delay circuits 14, 17, 20, and 26 are provided for synchronizing the timing (effects of the invention). 7, 3) The 5EC-DIDD code decoding circuit 10 will be explained first.

The calculation circuits 11 and 21 calculate the subtracted syndrome F(1
) outputs a low potential when F (1) = 0, F (1
) Generates high potential output when arrow O. The detection circuits 13 and 23 calculate the sindo o − calculated by the calculation circuit 12.22.
Syndrome F←), syndrome F(b), place χ)
When FtX=0, a low potential detection output is generated, and when FtX)=00, a high potential detection output is generated. In addition, the detection circuit 13 detects that the syndrome A F Hayashi) calculated by the calculation circuit 12 is F(Ill
) Generates a high potential correction output when NO. Note that, as described above, the detection circuit 23 generates only a detection output and does not generate a correction output.

Therefore, the incremented received audio data is supplied to the input terminal IN. However, in television satellite broadcasting, range bits, etc. exist in the incremented received audio data without being incremented.
Audio data etc. exist in an incremental state.

Input interleaved received audio data [polynomial R(X
) ] is calculation circuit 11 and 12 Nyo syndrome F (
1), F(ψkami l calculation, syndrome F(1),
The value of F←) is as shown in Table 1.

Therefore, in one embodiment of the present invention, the correction operations and outputs for the erroneous patterns shown in Table 1 are as follows.

First, in case A, the output of the exclusive OR circuit 15 becomes a low potential, and the inverted output EP of the latch circuit 16 becomes a high potential. Therefore, the dart of the ANDr-) circuit 18 is controlled to be in the open state. On the other hand, since the syndrome F(to) calculated by the calculation circuit 12 is F@20, the detection circuit 13 does not generate a correction output and no correction operation is performed. That is, in case A, it is determined that there is no error and no correction operation is performed.Therefore, the output of the exclusive OR circuit 19 is that the received audio data via the delay circuit 14 is output as is, and the delay circuit 201 calculation circuit 21. 22.

In calculation circuits 21 and 22, the syndrome F(1
), F) are calculated, but since the uncorrected voice data etc. are supplied as they are to the calculation circuit 21.22, F2(1) r is applied to the result of the syndrome calculation by the calculation circuit 21.22. If it is shown as F2←), the syndrome F2(1)=0 or F2@)=o.

Therefore, the output of the calculation circuit 21 and the detection output of the detection circuit 23 are at low potential. On the other hand, the latch output EP of the latch circuit 16 is at a low potential and is supplied to the OR-DART circuit 24 via the delay circuit 17. As a result, the output of the OR gate circuit 24 becomes a low potential, and the selector 27
On the other hand, when the range bit etc. pass, that is, during the period when audio data etc. pass, the signal C is at a high potential, and during this period the output of the or dirt 25 is at a high potential.The selector 27 is a delay circuit. Choose how 26 comes out.

That is, the storage circuit 1 is supplied with the range bits etc. being output from the exclusive OR circuit 19 and the audio data etc. being output from the delay circuit 14.

However, in case A, since no correction has been made, the range bits etc. output via the exclusive OR circuit 19 and the range bits etc. being output from the delay circuit 14 are the same, and the range bits etc. output from the long sword terminal IN are the same. It will be added.

Next, in case B, the output of the exclusive OR circuit 15 becomes a high potential, and the inverted output EP of the latch circuit 16 becomes a low level. Therefore, the AND dart circuit 18 is controlled so that its dart is closed. On the other hand, since the syndrome F(Q) calculated by the calculation circuit 12 is FD)=O, the detection circuit 1
No correction output is generated from 3 onwards. However, since the dart of the AND dart circuit 18 is controlled to be in the closed state, no correction operation is performed regardless of the presence or absence of the correction output from the detection circuit 13.

As a result, the syndrome F2(t)#o, F2)=0. On the other hand, the output EP of the latch circuit 16 is high'
The potential is high regardless of the value of the output F2 (b). Also, the output of the OR/DART circuit 25 is at a high potential regardless of the signal supplied to the terminal C, and the selector 27 selects the output from the delay circuit 2.
6 is selected and supplied to the storage circuit 1, so that the storage circuit 1 is supplied with the received audio data applied to the input terminal IN.

Next, in case C, as in case B, the output of the exclusive OR circuit 15 is at a high potential, and the inverted output EP of the latch circuit 16 is at a low potential. On the other hand, since the syndrome F←) calculated by the calculation circuit 12 is F=1, the detection circuit 13 generates a corrected output. But and dirt 18
Since the dart is controlled to be closed, no corrective action is performed.

As a result, syndrome F2(1)-〇, F2 cap U occurs. On the other hand, since the output EP of the latch circuit 16 is at a high potential, the OR-DART circuit 24 has the syndrome F2(1),
The OR gate circuit 25 has a high potential regardless of the result of F2 (<. Also, the OR gate circuit 25 has a high potential regardless of the signal supplied to the terminal C, and as in case B, the selector 27
selects the output of the delay circuit 26. Therefore, the storage circuit 1 is supplied with the received audio data applied to the input terminal IN.

Next, case D will be explained. In this case, the output of the exclusive OR circuit 15 is at a low potential, and the inverted output EP of the latch circuit 16 is at a high potential.

Therefore, the dart of the AND gate circuit 18 is controlled to be open. On the other hand, since the syndrome F@ calculated by the calculation circuit 12 is F(b)=1, the detection circuit 13 generates a correction output, and the error bits such as the range bit supplied from the delay circuit 14 are sent to the exclusive OR circuit 19. ′f
A correction is made.Also, there are bits that are corrected in the audio data etc. being output from the delay circuit 14, but as will be described later, they are not selected by the selector 27, so there is no problem.

The output of the exclusive OR circuit 19 is subjected to syndrome calculation again in calculation circuits 21 and 22.

The result of this word calculation is syndrome F2(1)lF2(b)
p1 case DO (F2(1)=0 and F7<1
=0), Case D 1 (F2(1)+ o and F2@=
0), case D2 (F2(1) = 0 and F2(b) lol 0), case I) s (F(1) 'q O and F2
(NO) will occur.

In case Do, as a result of the syndrome calculation by calculation circuits 11 and 12, there is no odd number of bit errors and F←
)=1 due to correction in the exclusive OR circuit 19, F2(1)=0 and F2(b)=0
This is because an odd number of range bits, etc. were determined to be incorrect, but the error was due to one bit being incorrect. Therefore, by performing the syndrome calculation twice, it is determined whether there is an odd number of bit errors or one bit error. This is because in BCH (7, 3) sgc-DgD, 1-bit error 9 can be correctly corrected.

In case Do, the output EP of the latch circuit 16 is at a low potential, and F2 (1) = 0, and F2) =
Since it is 0, the output of the OR gate circuit 24 becomes a low potential, and the OR? -) The output of the circuit 25 is at a low potential, and the selector 27 selects the output of the delay circuit 2o. Therefore, the storage circuit 1 is supplied with error-corrected range bits and the like.

Then, when the subsequent audio data etc. are being supplied, the signal C is not at a high potential, and the output of the or-dirt circuit 25 is at a high level, and the output of the delay circuit 26 is selected by the selector 27, and the memory circuit is will be supplied to

Therefore, the storage circuit 1 is supplied with range bits, etc., which have a 1-bit error and are free of errors as a result of correction of that erroneous bit, and audio data, etc., in which the subsequent erroneous bits have not been corrected. 1, BCH (63°56) SEC-DED
The signal is supplied to the code/decoder circuit 2.

Therefore, if there are two error bits as shown by the X marks in Figure 2, the error bits such as the range bit are BC) I I
The 1-bit error in the audio data etc. that remains after being corrected by the c-DED code decoding circuit 1o is processed by the BCHSEC-DE.
The D code decoding circuit 2 will correct the error correctly. Therefore, the erroneous bits marked with an X in FIG. 2 are correctly corrected, and the conventional drawbacks are eliminated.

Next, in the case of Gu 10 Ri, the output of the calculation circuit 21 is a high potential, the detection output of the detection circuit 23 is a low potential,
The output EP of the latch circuit 16 via the delay circuit 17 is at a low potential, but the output of the OR gate circuit 24 is at a high potential regardless of the output of the latch circuit 16 via the delay circuit 17 and the output of the detection circuit 23. .

Case D again! In this case, the detection output of the detection circuit 23 is at a high level E, and the output of the circuit 21 is at a low potential υ, and the output EP of the latch circuit 16 via the delay circuit 17 is
is at a low potential, but the latch circuit 1 via the delay circuit 17
6 and the calculation circuit 21, the output of the or-dart circuit 24 is at a high potential.

In case D, the output of the calculation circuit 21 and the detection output of the detection circuit 23 are both at high potential, and the delay circuit 1
Although the output EP of the latch circuit 16 via 7t is at a low potential, the output of the OR/DART circuit 24 is at a high potential.

Therefore, in each case DI#D鵞#DB, the output of the OR-DART circuit 25 becomes a high potential and the selector 27 selects the output of the delay circuit 26, regardless of the signal C. Therefore, the corrected output from the exclusive OR circuit 19 in case D is not selected, and the received audio data supplied to the input terminal IN is supplied to the memory circuit 1 as is, and the BCH ( 7,
3) The SgC-DED code decoding circuit 10 is now substantially equivalent to being bypassed and is replaced by the circuit shown in FIG.
NQ correction will be made.

(Effects of the Invention) As explained above, according to the present invention, it is detected that the range bit, etc. in the inked received audio data has a 1-bit error, and by this detection, the erroneous p bit of the range bit, etc. Since the corrected received audio data is deinterleaved, if there is an error in the range bit, etc. in one block (63 bits), and if there is a 1-bit error in the audio data, etc., it is possible to perform tiJ compression correctly.

Furthermore, since the erroneous p bits such as the range bit are corrected before deinterleaving only when there is a one-bit error in the range bit, etc., there is no possibility of erroneous correction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional satellite broadcast reception whisper decoding circuit. FIG. 2 is an explanatory diagram showing the state of an erroneous bit. FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 4 is a block diagram showing an example of the configuration of the BCH (7, 3) 5EC-DB;D code decoding circuit 10. l...Memory circuit, 2...BCH (63, j6)
8EC/DED code decoding circuit, 3...BCH (7,
3) SgC/DED code decoding circuit, lO...BC
f((7,3) SKC/DED code decoding circuit, 11
and 21... calculation circuit, 12 and 22... calculation circuit, 13... detection circuit, 14°17.20 and 2
6...Delay circuit, 15...Exclusive OR circuit, 18.
...And dart circuit, 19...Exclusive OR circuit, 2
4 and 25...or-dart circuit, 27...selector. Patent Applicant Trio Co., Ltd. Patent Attorney Nobuo Dosako

Claims (2)

[Claims] (1) A deinterleaving device that deinterleases received audio data, and a first BCH single error 9 that is supplied with the deinterleaved received data and corrects errors in the received data.
a correction/double error detection code decoding circuit; and a second BCH for correcting errors such as range bits extracted from the output of the first BCH single error correction/double error detection code decoding circuit.
In a satellite broadcasting receiver having a single-error correction/double error detection code decoding circuit, corrects only one-bit error in range bits, etc. in interleaved received audio data, and supplies the output to the deinterleaver. A satellite broadcast receiver comprising a third BCH single-error correction/double error detection code decoding circuit. (2) The third BCH single error correction/double error detection code decoding circuit is the first calculation circuit that calculates syndrome F(1) when the generating polynomial for range bits etc. is FC, ), and the syndrome F6 ) [α is the root of the primitive polynomial] and F(1)'=0 and F)
A correction means for correcting the error bit when the answer is NO, and the output F 2 (X) of the correction means is supplied to correct the syndrome F2.
Third calculation circuit that calculates (1) and syndrome F
20) and a fourth calculation circuit that calculates F,i,1)=0
And when F2(d)=00, output the range bit etc. output from the correction means and the intact sound/voice data etc. in the incremented received audio data, and F2(1)=0.
2. The satellite broadcasting receiver according to claim 1, further comprising a selection means for outputting interleaved received audio data when F2light)=0.