JPS607307B2 - Bus control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control method for controlling a bus that transfers information between a processing device, an input/output device, etc.

In a DMA (serial memory access) control method in a processing system in which a processing unit (hereinafter referred to as CPU), a main memory register group, an input/output device (hereinafter referred to as 1/0), etc. are connected by a common bus, the 1/0 side Generally, a system is adopted in which bus access requests from the processor (using the main memory) are given priority over bus access requests from the processing device.

In the conventional system, one of the bus access requests from the processing device is access to a register group, and the register group includes a CPU control register and a 1/0 control register.
It is necessary to determine which register the bus access request relates to. This determination requires, for example, 8 seconds (nanoseconds), but in this example, it takes at least 8 nanoseconds to accept the bus request from the processing device and grant permission to use the bus.
This means that it will take more than s (time required for determination). In this conventional method, even if there is a bus request from the 1/0 side immediately after accepting a bus request from the processing device, it is put on standby, and the bus access request from the 1/0 side is made to wait. Even if priority was given, there was a drawback that it was not taken advantage of. The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a bus control system that further increases the priority of bus access requests from the 1/0 side. The present invention provides a bus control method for a processing system in which a processing unit (CPU), a main memory, a bus control unit, and a register group (CPU control register and 1/0 control register) are connected by a common bus. , after the bus control unit receives a first bus access request for the register issued from the CPU and grants access to the common bus in response to the first bus access request, it determines which input/output device the access request is directed to. When a second bus access request issued from the 1/0 control register side is detected while determining whether it is an access request, the permission to use the common bus for the first bus access request is canceled, and the second bus access request is canceled. This bus control system is characterized by comprising means for granting permission to use the common bus in response to a bus access request.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram explaining one embodiment of the present invention, and FIG.
The figure is a time chart explaining one embodiment of the present invention, in which 1 is a processing unit (CPU), 2 is a main storage device, and 3 is a CPU.
U control register, 4, 9 register, 5 discriminator circuit, 6
is a control circuit, 7, 10, 12 is a detection circuit, 8 is a delay circuit, 11 is a 1/0 control register, 13 is a pulse circuit, A,
B is a common bus, CL is a clock pulse, D is a detection signal,
E is a control signal, a, c, c,, c2 are access request signals, f, h are permission signals, g is an output signal, t,, t2, t3
, t5, k' is the time. The discrimination circuit 5 in FIG. 1 requires more than 8 seconds to complete its discrimination operation,
Therefore, the delay time of the delay circuit 8 is set to 8 seconds. Note that common bus A (hereinafter referred to as A bus) is common bus B (hereinafter referred to as A bus).
This bus is faster than the B bus (hereinafter referred to as the B bus). In FIG. 1, there are two types of bus access request signals c issued from the CPUI. is an access request c2 (to the 1/0 control register) to the B bus. Therefore, the access request c is the above-mentioned access request lc, or
It is necessary to determine which one is c2, and in order to determine this, the determination circuit 5 requires eight plates or more. As shown in FIG. 2, when the address request signal c is set in the register 4 at time t, the detection circuit 7 detects this and issues the permission signal f at a time of 2, triggering the delay circuit 8. do. On the other hand, an access request a is issued from the 1/0 side (1/0 control register 11) at the time, and this is sent to the register 9.
is set to The detection circuit 12 detects this access request a
Even if this is detected, the transmission of the permission signal h is suspended (because the permission signal f for the A bus has already been transmitted). At time t4, when 8 seconds have elapsed since the time ratio 2, an output signal g is issued to the delay circuit 8, and this is input to the detection circuit 10. At this time t4, the detection circuit 10 outputs the permission signal f (already transmitted).
When detecting the access request signal a of the register 9, a detection signal D is generated. The detection signal D controls the detection circuit 7 to stop the permission signal f (time t5), and also causes the control circuit 6 to stop generating the control signal E. On the other hand, the detection signal D reaches the detection circuit 12 and transmits the permission signal h at time k.
'The 1/0 side is allowed to use the A bus. As described above, in the present invention, when bus access requests from the CPU side and the 1/0 side compete and an access request from the 1/0 side arrives with a slight time delay, the delay is within a predetermined time. If there is, priority is given to the access request on the 1/0 side, which has the advantage of improving the processing efficiency of the processing system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining one embodiment of the present invention, and FIG.
The figure is a time chart explaining one embodiment of the present invention, and the symbols used in the figure are as follows. 1 is the processing unit (CPU), 2 is the main memory, 3 is the CPU
Control register, 4 and 9 are registers, 5 is a discrimination circuit, 6 is a control circuit, 7, 10 and 12 are detection circuits, 8 is a delay circuit,
11 is a 1/0 control register, 13 is a pulse circuit, A, B
is a common bus, CL is a clock pulse, D is a detection signal, E
is a control signal, a'C'CI'C2 is an access request signal,
f, h are permission signals, g is output signals, t2, upper 3, t
4, H, and t6 indicate time. Figure 2

Claims (1)

[Claims] 1. In a bus control method of a processing system in which a processing unit (CPU), a main storage device, a plurality of input/output devices, and a bus control unit are connected by a common bus, the bus control unit accepting the first bus access request;
After granting permission to use the common bus in response to the first bus access request, a second bus issued from the input/output device while the bus control unit is determining which input/output device the bus access request is directed to; A bus comprising means for canceling use of the common bus for the first bus access request and granting permission for use of the common bus for the second bus access request when an access request is received. control method.