JPS6069993A - Recording system of video format - Google Patents

Abstract

PURPOSE:To generate a reading clock having a timing corresponding accurately with an input data by generating a bit clock at all times. CONSTITUTION:In recording a video format signal while a digital data of prescribed information is inserted, when the digital data and picture information exist in mixture in the same field, a clock signal in synchronizing with the clock timing of the digital data is recorded while it is inserted not only to the horizontal scanning period where the digital data is inserted but also to the horizontal scanning period where picture information is inserted. Thus, the bit clock having the timing coincident accurately with the input data is generated to avoid the state that the bit clock is unlocked at dropout.

Description

[Detailed description of the invention]

The present invention relates to a recording method for a video format signal, and more particularly to a method for recording image information and audio information on a recording medium as a video format signal. When audio information corresponding to image information is recorded on a recording medium together with image information, the audio information is compressed in time and inserted in the first part of the issue, and the image information is inserted in the song part. There is a way. In this case, the audio information is digitized and recorded, but in order to read this digital data, it is necessary to read the digitized data by clicking the digits ``)'' in synchronization with the digits composing the digital data. When inserting this pin 1 in advance at the beginning of the digital data insertion period.
It is possible to insert a clock signal synchronized with the taro clock for several V cycles to several cycles, but if the digital data and image signal f4 are mixed in one field, the horizontal The scan line section is exactly 1
The playback side is not inserted and the playback signal is not inserted.
It is difficult to generate and see the clock signal.1 [Stop yelling.1.
Therefore, the present invention always generates a signal so that accurate 4-fold extraction can generate a signal to the bin i[1 block]. The purpose is to provide a recording method. The recording formula for a video format signal according to the present invention is:
When inserting digitized digital data of predetermined information into a signal and recording it, if the digital data and image information are mixed in the same field, the digital data It is characterized in that a clock signal synchronized with clock timing is inserted and recorded not only in the horizontal scanning section in which the digital data is inserted, but also in the horizontal scanning section in which the image information is inserted. The present invention will be described in detail below with reference to the drawings. FIG. 1 is a detailed explanation diagram of the principle of the present invention, in which the number of horizontal scanning lines (corresponding to an effective screen) of a signal corresponding to one field of the signal to the video format 1 at the time of recording is a. Divide b, O, and Q into multiple blocks. In particular, a, b, and c are made up of an integer number of horizontal scanning lines, and furthermore, the number of horizontal scanning lines of C is a predetermined integer x. It is made divisible and has the relationship m=c/x (m is an integer).Therefore, C is composed of m units and C1 to C
It is divided into up to X subblocks. Note that Q is not necessarily an integer. Figure 2 shows part of the same digital I-7 signal shown in Figure 1. Figure (A) shows an image on block C1Q, and Figure (I3) shows a picture on block C. This is an example waveform of digital data recorded. FIG. 3 is a diagram showing specific numerical values of an example of division of a, b, c, and Q in the N'1-8C signal. .5 water, and a.1) The block is set so that it is outside the visible range on the TV screen. In this example C, a = 1. b=4. c=234.
, X −9,m =26.0=2.5. Here, when digital data is inserted into b and c, interleaving is applied so that even if errors are concentrated in Trop-out 1 to etc., only consecutive errors occur, and J, which is capable of error detection and correction, is used. Although the positive code is added, in this example, the interleaving and error correction blocks are completed independently of b. Similarly, J in C
Even if there are 5, interleaving and error correction 1 can be completed independently from C1 to CX. Figure 4 shows an example when digital data is inserted on one horizontal scanning line, and the data transfer rate is 408 f + (f
+-+ is the horizontal scanning frequency), and a clock run-in signal, which is a signal for the clock signal 111J, is inserted before the digital data. Further, following this signal, several bits of a data synchronization signal are inserted for data synchronization. A data word and an error detection and correction code are inserted following this data synchronization signal. Figure 5 shows various recording modes. In (A), only images are inserted into blocks C and Q, and blocks a and b are outside the visible range, so they are similar to ordinary television images. will be displayed. (B) shows all digital data inserted into block C, and (C) shows digital data inserted into sub-blocks C, C2, C8, and 09 of block C divided into nine parts, and images inserted into blocks 03 to C7. are inserted respectively. (D) is an example in which digital data is inserted into →knob blocks c, , c2 and images are inserted into C3 to C9, and (E) is an example in which images are inserted into V block c, , C7.
8 and C9, respectively. In FIG. 6, frames (fields) in which digital data is inserted into block G are continuous for a period of 1.11). This ranges from several clays to several tens of arenes, and varies depending on the required data. In period B following ma/= , the C block corresponds to all data (an image is inserted. Here, normally, J31 in period △) It may be an 11-screen image, a frame-by-frame image, or a moving image. It should be noted that the same image may be recorded for several frames in the still Jj image C as well, in order to prevent image overlap 1-1 streak between adjacent frames. Figure 7 shows the riff of C block 1-1 Ivy I)/[1 Tsuk C
1. Insert digital data into C9 and images into C2- and C8, respectively, and continue for a period Δ of several rooms, and a period 13 (・ is an example of inserting only an image in block C (Yes, there is. In the case of a mouth, part of the screen becomes a thud during the period, and the image is not interrupted. -pine 1~
This is a block diagram of a recording system for converting a signal into a digital signal, and the analog A-D signal is digitized in a Δ/D converter 80. This digital signal is written to a buffer memory 81 for time-base compression at a sampling frequency B(R). Time axis compression is achieved by reading data from the memory 81 at a higher frequency f2<W: f+(R)J. The control signal, which is control information, is
In addition to the clock run-in signal and data synchronization signal described above, it includes the content and capacity of information in each block, and various processing information in J3 when reproducing the information. A video signal, a digital data signal including audio data compressed in time by a buffer memory 81, and control information are input to a switching circuit 82, respectively. The selection operation of this switching circuit 82 is controlled by a timing signal generator 83.
The timing signal generator 83 also controls the writing and reading of the memory 81. The timing signal generator 83 inputs an input signal, and the internal oscillator synchronizes with the lh1 light signal of the M signal.
Various timing signals are generated according to the signals.
4 because the matte signal is obtained. Figure 9 is a schematic block diagram of a general jij production device for still image signals with audio information. and j-internal data are separated, and among the digital data, audio data and ]-1 to 1-1-1-1 data are separately separated. J to synchronization signal, retiming (ij @ generation (1 device 2 generates timing signals such as output pulse f2 (W), read pulse [1 (R), etc.)] Control data error detection and correction i [Error iiJ +l- is made in the unit 4, and the error is decoded and sent to the control generator 7. The digital data is inputted into the memory 5 via the error Ml' it unit 3 into the pulse f2 (W), read out with the pulse fl (R), and subjected to UK axis expansion. Error = Jit may be configured to be performed after time axis expansion processing. This time axis expanded digital data is processed by a digital analyzer.

The -C signal is converted into an analog signal by the converter 9 and the reproduced audio signal A is generated. According to each control command decoded by the control decoder 6, roll signals to various controllers 1 are generated from the system control generator 7, and playback video signals are transmitted through the screen processor 8, which operates according to predetermined control signals. 1J”
be done. However, for the digital data insertion block, for example, the image is processed as a black level and output.
It is something that In addition, a control signal is derived from the playback controller 10 to control the playback operation of the VDP (video subdisk player ~7), and control signals such as stopping Vt), PLAY, etc. ” - the first block in one field, as described in Figure 1.
In track a, several sets of data are inserted into horizontal scanning lines, including a clock synchronization signal, a clock run-in signal for data synchronization, and a data synchronization signal. Clock and data word synchronization will be established. This 10xA section is called the field sync and is shown in detail in Figure 10 of this 11" configuration. The data transmission rate is 408fH, No digital data is inserted into the 64 bits from the falling edge of 11 sync.The field sync data string is 320 bits.
~ is used. 320 bits are further divided into 10
The unit is 2 pips 1 to 1, and each unit constitutes one set of clock signal 111J and data synchronization signal ff+7. 3
Out of 2 pins 1, 24 pins 1 are clock run-in signals, and 10 consecutive signals of 1010...10 are inserted for 12 cycles, followed by 11100010.
0's partner father-in-law is 1φ person at 8 pits 1. A combination of these 24 Pit I and 8 Pit 1 - 32 Pit 1
- 10 consecutive sets of -C data are inserted (there are). In addition, the equivalent of 24 bits is taken as [ln1~bove]. In this example, 1, a = 1 'r'' 221-1 [:J
This signal YJ column is inserted for 1φ. Various control signals for the contents of the information inserted in block C are inserted into block b. When inserting digital data into blocks b and C, the effective data range consists of 320 pits as in the field sync, as shown in Figure 11, and from sync 11 to the beginning of the data string is 64 bits.
~． Furthermore, the front porch is equivalent to 24 pits, which is exactly the same as the field sink shown in FIG. Also, among the 320 bits, the first 24 bits of the data string,
12 cycles of clock run-in signal followed by 8 pips 1
- data synchronization signal continues. 288 pics left 1~
The information is divided into 36 parts (8 bits x 1 byte). In addition, in the case of the present invention, block b contains /l1-
1 is assigned. That is, 23.2/1.2
Each control signal is recorded in each H of 5.26. Furthermore, information in units of 8 pits (1 by 1) in block b is so interleaved and error corrected as to be completed. Next, when recording digital data in the block C, 26+-1 is set as 1 block]-1 block, and 1 node C is maximum 9 blocks. 1 Frame C Most People 18 B1-1 Tsuk C゛Digital-j
Data can be recorded, and any combination of full-scale digital data, full-scale images, and digital data and images is possible. The digital data of the block is structured so that interleaving and error correction are completed within one block. Next, Figure 12 shows a concrete example of the reproduction system.
be. In the case of the present invention, the digital data is a time-base compressed digital data C', and the apparatus for adding audio to a still image will be explained. This device amplifies the video signal by an amplifier '11, a V sink from the video signal, and an IV synchronized divider 12 which takes the sink by N1. Set the level to the level of the data ii'j' (8- and then automatically set it to
(NON RETU RN -1-○ / 1ku0
), the ΔIC circuit 13 converts it into a digital data string, and the R U N -I N detector 14 detects the first run-in signal from the digital data string. The data synchronization signals from 1 to 1 are detected and the leading position of the data in c is detected every 1-1. An S/P converter 24 that similarly reads data using a clock and converts the data string into 8-bit parallel data. A switching circuit 16 that detects the 23rd to 26th days in the field, separates the control data signal, and switches the output.
, a clock extractor 17 that extracts a clock component from a data stream using the RUN-IN signal as a reference, a system clock generator 18 that applies a PLL to the extracted clock and generates the clock necessary for system operation. Based on the tarokk signal obtained from the clock generator, '1
The timing for generating various timing signals is controlled in accordance with the v, to+sync signal obtained by the v synchronization separator 12 and the detection signal of the beginning of data obtained by the data opening detector 12. Signal generator 2, a field sync detector that receives control from this timing signal generator to detect field sync and establishes clock synchronization and data synchronization at the beginning of each field from the clock run-in signal and data cycle pattern. 19. Control!]-le buffer that temporarily stores the control code separated from the switching circuit 16 20. Error performing error correction processing of the con1~[''-rou1-code read from the con1-roll code buffer The corrector 4 performs error correction processing on the controller 1~roll''-1--C organizer interleaver 21. A series of skits “”−
7. System control unit 7. System control unit 7. Admission mail from the system controller
When inputting or reading data to the end 5, an initial address signal is obtained, and when reading 8 bits of data, the timing 13 generator 2 generates a [j shift pulse]. The digital data in the address counter 21.buffer C is processed and the address signal is supplied to the buffer counter 5.
, digital signal at J2 (W) -11, ¥
An error corrector 3 which performs a correction process at the medium level stores the information and reads it out using the f+ (R) signal. :Jj "De-interleaver 23 that converts processed data into a continuous data string. A digital interleaver that processes a series of digital data at the timing of f+ (R) obtained from the timing signal generator 2 and converts it into analog.・Receive control signal for VDP from analog converter 9 and system controller 7
The player controller 10 supplies control I/roll signals to the VDP. In such a configuration, when a recording bidet sub-format signal having a pattern as shown in FIG. The inserted digital data is sequentially stored in the memory 5. In the next period B, the VDP resumes still image or frame-by-frame playback. At this time, the digital data stored in the memory 5 is output. However, if this data is time-axis compressed audio digital data, it is time-axis expanded and output as analog audio during the still image or frame-by-frame playback.In addition, in period A, the TV monitor is shown in Figure 9. (The screen processing unit 8 is clamped to the black level. A) X - Matsu 1
- During the reproduction of the signal, the digital data in the period AC and block C are sequentially stored in the memory. During this time, the lower part of the monitor screen at -L is similarly processed to have a black level, and an image appears in the middle part. To be more specific, the video output terminal J of Vl)P, Rino?
Ij raw bidet stab A-Matsuh signal is bidet'Aj1'1
1 and is amplified. This amplified output is the Kaimei separator 1
The separated synchronizing signals (V, II> are applied to the timing signal @ generation type 2 and supplied to the '1 human power of the timing signal @ generation type 2. In addition, the amplified HIA signal is input to the input of the Δ10 circuit 1:3. This A10 circuit detects the peak and pedestal level of the data, and sequentially automatically sets the threshold level while following each node, and converts the video signal hH to N1 and 7θ pieces. j゛Retrieve the digital data string.
The UN-IN signal detector 14 detects a 24-bit, 12-cycle clock run-in signal under the control of the timing control signal from the timing signal generator 2. Detector 14
The output is a clock extraction circuit 17 that extracts a clock component from a normal data string based on a clock run-in signal.
is applied to the input of The extracted clock components are applied to system clock generator 18. This system clock generator uses the extracted clock components to generate a system clock for operating a system synchronized with a data stream using an LL circuit. The clock signal generated by the system clock generator 18 is applied to the timing signal generator 2. In the timing signal optical stopper 2, the synchronization signal (V,
-C within one field while being controlled by 1-1)
is applied to the control terminal of one field sync detector for detecting 22+-1 eyes and detecting field sync η
generates a timing signal. It also detects signals 23 to 261-1 and generates timing control signals for controlling call data 1 to 1. It also detects 27+-1 and issues a control signal/l- for writing and reading data after 27+1. The serial J-evening news output from the AC circuit 13 is also applied to the data synchronization detector 15 and the S/[) converter 2/I. These read the data in synchronization with the I rack, and the data synchronization detector 15-C detects a data synchronization signal in each 1-1 and applies it to the timing signal generator 2 to determine the starting position of the data. The same 1i1J relationship between the timing signal and the timing signal is maintained constant. In addition, the S/P converter 24 converts serial data into 8 hira1~
Convert to unit parallel data. Notes 8 to 1 are applied to the switching circuit 16. 1. In the II refinished circuit, the timing signal generator 2J, 23-2 (51-1 indicates that the The control code stored in the buffer 20 is the error correction circuit. The input fJ of 4 is applied to the input fJ of 81 in which the error is stopped by the error correction circuit.
- code is changed to i19 and applied to the system controller 7. The system controller decodes the 'n1~roll code,
Based on the timing control signal generated from the timing signal generator 2, C digital data writing, screen control,
It initializes the address counter 22 of the large-capacity buffer memory, and manages the digital data capacity M. Control-related signals such as operation and stop of play V are sent to play 1.
7 controller 10, and this play 17 controller converts the play V into a drive signal and supplies it to the drive signal V. Next, 2211 is applied from the timing signal generator 2 to the control terminal of the field sync detector 19. The detector generates a clock signal and data synchronization M quasi within the field from the repeated signals of the clock run-in signal and the data synchronization signal.
and is fed back to the timing signal generator 2. Next, the signal that detected 271-1 from the timing signal generator and the controller 1 code are ticked,
If a digital (digital)'-digit is recorded in the block = 1- or the system controller a++, the control 211 f is generated from the system controller.
The timing signal generator 2 generates the signal according to the timing signal (2
In response to the signal (W), the data is temporarily stored in the large-capacity pack ameshiri 55 one after another. When the storage of a certain amount of data is completed, the system controller 7 instructs the player to reproduce a still image at a specified frame, and the player 7 starts to reproduce the still image. From the large-capacity buffer memory 5, the system controller 21I unit 7 sets the read start address in the address counter 22, and the timing signal light 4
One device? Generated from: f+ (R) signal allows C to be sequentially read and output. The data sequentially read from the large capacity memory 5 is applied to the input of the correction circuit 3 and corrected by the correction circuit 3C.
(R is corrected and applied to the human power of the de-interleaver 23.
- Applied to the input power of the i'D/A converter 9 in place of the evening arrangement. The D/Δ converter C converts the sound into the sound Tijdengetsu and outputs it as audio. While audio is being output, the brake A7 is playing still images. Large capacity buffer memory 5
When a specified amount of data is output from the player, a control signal such as 1 notch or play is supplied to the player according to the program code. Here, a method of clock synchronization and data synchronization using the RUN-IN signal detector 14, data synchronization detector 15, and field sync detector 19 will be explained. In each field, 1 for each field 1 of 221.
First, tarock synchronization and data synchronization are established using a clock run-in signal and a data synchronization signal, which are included in each clock run-in signal and data synchronization signal. That is, the clock component included in the clock run-in is extracted by the clock extraction circuit 17, and the PIL circuit of the clock generator 17 is synchronized with it. Further, the leading position of the data is detected using a data synchronization signal, and this is applied to the timing signal generator 2 to synchronize this circuit with the data. The reason why the field sync includes 10 clock run-in signals and 10 data synchronization signals is that part of the signals may be missing due to dropouts, etc., and the C in the field sync must ensure clock synchronization and data synchronization. There is a place to pray. Once synchronization is performed with Field Sync,
At the beginning of each ``1'' containing data, each RU
N -, IN Signal detector and data synchronization detector C - Using the detected clock run-in and data synchronization signals, clock synchronization and data are the same while correcting clock phase shifts and bit shifts! Maintain IJ. Further, the clock run-in and data synchronization signal at the beginning of each 1-1 play the role of resynchronizing when the data synchronization is lost during the II footer period due to de-[1 block-out or the like. FIG. 13 shows a specific example of the data synchronization detector 15, and the pattern filter 151 detects a pattern 1100100 of the -7 data synchronization code and outputs a detection pulse. is for external sounds and fake data1
111 signal is detected and τ is iiJ function ↑ (since there is 1b,
Goo 1 at a predetermined timing using Nando Goo 1 to 152
~ signal (DSG signal) controls the input state of the detection pulse to subsequent circuits. This detection pulse is latched by a latch circuit 153 and held by another latch circuit 155 via a NOR gate 154. The data are then sequentially input to the next 7-bit shift register 156. The MSB of this register and the detection pulse at that time are detected to be in a non-coincidence state in the NOR gate 154. When a match is detected, a synchronization pulse is output, but the 10th
In the case of 2 2 +-1 shown in the figure, the synchronization pulse is output after detecting 10 sets of data synchronization signals, and after 2 3 +-1 shown in Fig. 11, one set of data synchronization signals is detected. The output timing of the synchronization pulses is different so that the synchronization pulses are output immediately after. Therefore, the generation timing of the synchronization pulse is controlled by the AND gate 157 to the gate signal (LDG signal) at a predetermined timing, and
2 +-1 and subsequent circuits are shared. Note that the AND gate 158 connects the shift 1 to the initial clear 17 of the register 156. Here, it is necessary to distinguish between the C image and the digital data in the block C, but at the same time, control the display of the next block at the start and end of the image. Insert as data. An example is shown in Figure 14, where the beginning of the image is S1Δ1<TBLO
4 bits are used for each CK. Also, its possible values are 1 to A (hexadecimal) C. Next block at the end of the image] Cook 13N +) +31.
, 4 pits I ~ are used as OCK, and the number (qr + i'i is 2 - 8 (hexadecimal). Furthermore, this number is calculated by dividing the block C into 4 knob blocks. In this example, in the case of x-9, the various video format A-mat signals shown in FIG.
and S - "△ Rl 13 1- OCK, to
Nl) 1. ) Shows the correspondence between each code of l-OCK and -C. . FIG. 15 is a jl-1 ivy diagram of the reproducing light that controls the reproducing operation using the needle indicating the insertion point of this image information, and shows the signal component III unit 1C b) ro 1 of FIG. 9. If 261-I UJ of 1-1 sync is detected among the synchronization signals, then what should be done in the field? 1252 binary counter 2
5. A flip-flop (FF) that uses the pulse output when the counter counts 16 as the clock input, output Q becomes 1, and outputs Q'IfiO with V sink.
26 is established (). The Q output of this FF 26 is connected to the input of an AND gate 27. The other inlet of the gate is connected to No. 18 of the I'' sink. The output j of the gate 27 is the AND logic of the output Q of the 1F26 and the 1-1 sync. That is 27
The 1-1 syncs after the 1-1 sync will be output. This 27th and subsequent 1-1 sync is clocked, V
There is a hexadecimal counter 28 which is cleared every time it is synchronized, and this is a counter that detects m of the cocks C1 to C9 in block C. In this example, m-
Since it is 26, it is a 26-decimal counter. There is a decimal counter 29 which performs a counting operation using a 26-decimal counter's signal and is cleared by a V sink. This counter corresponds to the four knob blocks in block C and Q in the blocks 1-rJ-b. Among the outputs from the control decoder 6 in FIG.
Similar to the 4-bit latch 30 that temporarily stores and decoys the 4 bits of the start block code signal, there is a 4-bit latch 31 that temporarily stores the 4 bits of the end block code signal. 1 - The output signal of the latch 30 is input to one side, and the output signals Q1 to Q-+ of the 4-pitch [. A matching circuit 32 outputs one pulse when all bits are equal, and similarly the output of a 4-bit circuit 31 is used as one input, and the other 4 bits are input to Q1 of the decimal counter 29. QI binding (there is a coincidence circuit 333 that outputs a pulse when all bits are equal. Also, the pulse signal output from the minus number circuit 32 is input as a clock input, and this pulse is inputted, and t=1ljl l
, :The Q output becomes "1", and the output of the -number circuit 33 is set to one input and the other input is set to the V sink signal, and when either signal is present, each Output A
The output of the I gate 34 is a FF whose Q output is l' OJ.
35, and when this Q output is 11'', a ll'l M
connected, and the Q output of F F35 is [1 when O-1)
There is a switch 36 connected to the side and a masking circuit 37 that forcibly sets the screen to black level. When the switch 36 is connected to the a side, the input video signal is output, and when it is connected to the b side, the input video signal is output. When the masking circuit 37 is present, the output of the masking circuit 37 is output. Further, the other output 0 of the FF 35 is connected to an AND gate 38 to control application of a write pulse +2 (W) to the large capacity buffer memory 5. In this configuration, a video format signal containing a mixture of image and digital signals is applied to the pano j of the signal separator 1 and is also applied to the a side terminal of the switch 36. Among the signals separated by the signal separator 1, the V sink is applied to the CL R terminal of the 25-bin counter 25, and the
It is applied to the L R terminal, the CIR terminal of the (X+1) base counter 29, and one input terminal of the A agate 34. 25 binary counter with V sync 25. FF26. m-ary counter 28. (X+1) base counter 29 and ["35 are then set to the initial state. Next, the I" sink separated by the signal separator is applied to the clock terminal Ck of the base 25 counter 25. L) (J, and gate 2
It is applied to one pano j terminal of 7. The 252 binary counter 25 is a counter for managing each field in the N-D SC I V signal.

【be. In each field, this counter performs a count-up operation every time a 11 to 1'' sync pulse is applied after V sync rises and the clear is released. Also, after counting 1-1 sync 16 times, a pulse is generated. This pulse corresponds to each field 1 to 2611 in the N"l' SCTV signal. This pulse is applied to the FF 26 terminal Ck. When a pulse is applied, a logic output 11 is output from the Q output. F "26 serves as a flag, and V sink is applied to the CIR terminal after 26H; 1CQ output is logic [1"]. F
The 0 output of F26 is applied to one input of ANDGOO 1-27. The other input terminal is applied with an l'' sink separated from the signal separator 1. Therefore,)
27I (hereinafter "I" sync) will be output from the 7-nd gate 27. This means that the 1" sync from block C in the screen division in FIG. 1 is applied to the clock terminal ck of the m-ary counter 28. Here, the m-ary counter is a counter for managing the block number. In this example, m = 26
It is. (2) The carry output of the progress counter is applied to the clock terminal Ck of the ×→-1 digit counter 29. X+
The quaternary counter 29 is a counter for managing the position of the subblock within the block C. This counter is
Since it counts not only the C area but also the Q area 1 or the V sink, it becomes x 1 in 1. In this example, since x is 9, it becomes a decimal counter. The outputs of the four pins -Q1 to Q6 indicating the state of this count are applied to one input of the matching circuit 32 and 33, respectively. On the other hand, among the control data separated from the signal valve 1IlI device 1, the code of the star h block indicating the start of the picture (9) is applied to the input of the latch 30 and temporarily stored.The stored period is one field or one frame. The output is applied to the other input terminal of the matching circuit 32. This minus number circuit compares every bit 1 to 1, and if 4 bits are reached, a pulse is generated at the output. Similarly, the signal divider 1J indicates the next block after the end of the image among the separated controllers 1-11, and the code in the divider block is latched 31. The output horn applied to the human power of the matching circuit 33 is applied to the other human power of the matching circuit 33, and each pin
. . . All 4 bits match, and a pulse is generated from IJ. - The output of the number circuit 32 is “F35
C is applied to the tarok terminal of the circuit. Moreover, the output of the minus number circuit 33 is applied to the human power of ΔAgate 3/l. A agate is applied to the clear terminals C1 and R of FF35 and C
There is. When the coincidence pulse of the number output circuit 32 is applied, the output Q becomes [1], and the -number output circuit 3ζ3
When a coincidence pulse of 2 is applied, the output Q becomes rOJ. 4
1 hO output is completely opposite to Q output. The Q j,ll force of F F 35 is applied to the switch 36, and “[
There is a switch set so that when the Q output of 35 is logic "1", it is on the a side, and when the logic is "○", it is on the side. Further, the Φ output of the FF 35 is applied to one input terminal of the AND gate 38. To use the AND gate 1, the input pulse +2 (W>) generated only in the block C from the timing signal generator 2 (see FIG. 9) is applied.Therefore, the AND gate 38 is applied to the Q When the output is "0", the input pulse f2 (W) is supplied to the large-capacity buffer memory 5, and the data separated by the signal separator 1 is sequentially stored.For example, as shown in FIG. In the case of the waveform C1, the code of the start block is 3 and the code of the end block is 8. At this time, latches 30 and 31 are set to 3 and 8. Initially, the Q output of FF 35 is "0". Since the switches 3 and 6 are on the b side, the video output is derived from the output of the masking circuit 37.The masking circuit is a circuit that masks the part of the video signal excluding the synchronization signal and color burst to the black level. C1 At this time, the screen becomes black.Also, "35's 0 output is impossible! L! l I J
Since there is C, the AND gate 38 is J2(W>
The pulses are output, and the data separated by the transmitting device 1 is written one after another into the input device 5. Next, when the X-1-i base counter 29 reaches 3, the coincidence circuit 32 generates a pulse, and the rising edge of this pulse changes the Q output of the rFF 35 to [1]. Therefore, the switch 36 is set to the a side, and the input video signal, that is, the image is outputted. As soon as the Φ output of 1-35 becomes rOJ, no pulse is generated from 1-38, and therefore no write operation is performed (at the end of buffer tightening).Similarly, the x + l base counter becomes 8 Then, the pulse from the coincidence circuit 33 becomes a valve and is applied to C1, R0iii f of the LTFF 35 through the A-1-35.
The Q output of this 1-[ becomes rOJ, and the switch 3G becomes b
On the side, the output masking circuit 37 outputs 10 lines. In other words, a black screen will be output. Also, the 0 output of [-135 becomes [1], and the output of the AND gate 38 becomes f2 generated from the timing signal S generation type again.
By (W), the data separated by signal separation is sequentially stored in the large capacity buffer memory 5. The timing of the above operation is shown in FIG. 16. Although FIG. 16 shows the video signal of the first field of one frame of NTSC, the same applies to the video signal of the second field. In the above example, in order to identify the image and digital data and detect the position of the digital data, data indicating the block where the image starts and the next block after the end of the image is inserted into the control data.
The start block 1 of digital data may be the next block after the end of digital data, and the same applies to -y-6 indicating the start and end blocks of digital data. There are various programs such as spray Δ, which is limited to the case where the audio digital data (SWS data) to be inserted is monaural, human explanation, music, etc., and such cases will be explained below. FIG. 17 is a diagram of the reproducing apparatus for the Hi'A-no-A-mat signal when the J-audio data has various contents, types, and sound quality. It is input to the lljl period separator 12, and the V and l-1 syncs are separated and supplied to the timing signal generator 2 to generate a timing signal (ij signal) synchronized with these syncs.Meanwhile,
Input Kahide'A] A-Matsu (The signal is also input to the △-IC circuit 13, and the signal is input to this circuit due to the dispersion of the video signal between the resollayers and the dispersion of the video disc, etc.)
In order to prevent misreading, etc., the highest threshold level is automatically determined based on the peak level and baseline level of the data inserted into the video signal, and the Data is waveform shaped N1
<7 j (becomes a digital signal. Becomes a digital signal I
7' - The clock run-in separator 1 /11JJ
, 1 min run-in signal is extracted and the SURE generator 18 generates 1 min run-in signal (i'/411 system clock). After the minute tall L IC, the serial data is converted into S/1 converter 24 and the timing signal generator 2 converts the serial data into 8 bits 1-parallel data.
It is converted by the signal from . The controller data is separated from the 8-bit parallel data by the three clock control data separators based on the timing from the timing generator 2, and the sampling code (to be described later) in the controller 1 data is separated by the sampling code discriminator 40. It is determined and held by a latch signal from the signal generator 2. Control data other than the Zumbling code is stored in the control code buffer 20 at the timing from the timing signal generator 2. The audio data other than the control data that has passed through the controller 1-roll data separator 39 is stored in a large capacity buffer memory 5, the address of which is designated by the address counter 22 as J:. After the f2 (W) signal is connected to the tarlock input terminal of the address counter and the first address is designated from the system controller 7, the next address is J2.
At (W), the address counter is incremented and sequentially written. Here, f2 (W) is to transmission line 1 during time axis compression. Next, the clock f+(R) read from the large-capacity buffer memory 5) is a "non-pulling clock" generated according to the output of the non-pulling discriminator 40;
]]/A converter 9 to command the start of 1)/7Δ conversion. Readout 1], the first 11-res of Y is designated as J to the system controller 7, as in the case of input, and the address counter 22 is designated as J (up is L+(I
t) to J. The rimbling code is represented by 2 bits and is latched by the bit discriminator 40. No. 1 Nonbringuk]
This system can generate three types of 32K.
l-l 7, 64 K l l l, 96 l
(to(l's link 1) generates C0
Cover with. These three types of sampling frequency r+)/
The A converter 9 is operated. Here, the C audio signal is digitized by I dubtive delta modulation (ΔDM > C, l)/Δ converter converts the ADM audio data into an analog audio signal. Furthermore, the decoder 42 controls the switching circuit 43 and the selection circuit 44 based on the sampling codes of 2 bits 1~, and filters 45~47 corresponding to each code.
and the Zumbling clock is 32K f-I.
Z throat is filter 45, 6 with band 2.5Kl-lz
4. For K1-1z, the band is 5 Kl (for z filter 46,96Kl-1z, the band is 7.5K I-I
The Z filter 47 is selected. Further, each code stored and decoded in the clock code buffer 20 is controlled by the system controller 7 according to each code, and control regarding play V is performed by the play\7 controller 10 such as stop, playback, frame advance, etc. Execute control. Next, the operation of hide A software 1 to 1, which is not shown in FIG. 18, will be explained. The SWS data for still image 1 is SWS data 1. S
WS data 2. The SWS data for still image 2 is S
WS data 3. SWS data 4° SW for still image 3
The S data becomes SWS data 5° and SWS data 6. Also, a sampling of two pits 1 to 1 in Con I-II-Luata is shown in Table 2 (listed at the end of the detailed description of the invention). It is assumed that control 1 control data is recorded in frame 11, which is one frame before the data frame to be controlled by it, and when VDP is in playback operation, 5WSj--in the frame before playing back 1] 1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-1-11
Detected at 0, rsws data 1. SWS' data 2 is stored in a large-capacity storage space L (), and SWS data 1 is stored in still image 1. SWS data 2 (5/lK l-IZ's 4
Plays at non-bringing frequency. Next, at the time of still image 1, the SWS data 3.8WSi-Evening sampling playback frequency is 32Kllzc and "11" is detected,
Stores SWS data 3.5WSl-ta 4, and still image 2 is 32KII7. Heigozuru on the ring frequency. In the same way, the static 11 strokes (3) is played back at 96 kHz. In this way, it is possible to record and play back by changing the limp ring frequency depending on the content and type of SWS data, as well as the sound quality of the original audio information. Here, the case where the SWS data is monaural and stereo will be explained using C, Figures 19 and 20.
The figure is a block diagram of the reproduction system in such a case, and only the parts different from FIG. 17 will be described. The stereo/monaural identification data inserted in the control code is extracted and discriminated by the discriminator 48, and the discrimination result is sent to the sampling clock generator 41. It is sent to four switching timing generators and audio output line switching relays RY+ and 2. The switching circuit 43 switches the analog A-D A signal using a switching timing signal generated from the timing generator 49 according to the discrimination result of the subarea i and t noral and sends it to the filter 4.5.46. These filters remove high frequency components such as zumbling frequency components. Relay R
Y+, 2 is for switching the A-D signal depending on whether the signal is spray A or monaural. Next, using the video format in Figure 20 to explain the operation of the block in Figure 19, hV [,) I) is amphibiously controlled, and the control data in the frame before SWS data 1 is The stereo image 1'/E normal identification data is extracted and discriminated by the discriminator 48, and the SWS data 1 and 2 are stored in the memory 5. When playing back, it is read out and played back in monaural mode.Next, it is determined that it is stereo Δ based on the control data of the still image 1 frame, SWS data 3./l is stored in the memory 5, and still image 2 is played back. At the time of -E Noral, f+(R) is equal to the ring ring frequency, and at stereo, the ring 1 ring j7, has a frequency twice the 1 wave number, and J, (I+, 'i axis is extended.The relationship between fl (1) in stereo and monaural is as follows:
When trying to obtain the i'i range, f + (R) at stereo = 2X (f + ( at 17211)
R)) becomes. Therefore,] nonpringuku [-1 ivy light'I
i! i/11 generates zumbling in the above relationship according to the monaural/stereo identification data and reads the data from the memory 5. In the above example, the output of the D/A converter 9 is separated in stereo by the switching circuit 43, but if these two are replaced,
The output j of the large-capacity buffer memory 5 is divided by a switching circuit, a D/A converter is connected to each separated output, and the output of the D/A converter is connected to a filter 45 and a filter 46, respectively. It may be covered. Assuming that the roll data to controller 1 is recorded in the frame immediately before the frame of the data to be controlled by it, lζ may be recorded in the same frame as the data to be controlled. In the example shown in Fig. 17, three low-pass filters corresponding to the Zumbling frequency were used and switched independently for each band, but a switched capacitor filter (basically, It consists of a switch and a capacitor, and by changing the clock frequency, the transmission characteristics can be shifted similarly along the frequency.
(7′1 C゛can be done using
→The clock frequency is changed in accordance with the non-bringing frequency, and the movement of the filter in each band is determined. Also, the microphone III computer is used for the υ control, and the control is good. FIG. 21 is an example Cd using a switched:l:t pacita filter and a micro convenience store I-type filter, and explanations of the same parts as those shown in FIG. 17 will be omitted. The ILL microcomputer supplies the address (4>6) to the entry buffer memory 5 at the time of writing and outputting DiY, respectively. In addition to generating the control signal for play 17, it also decodes the Leanbling frequency switch-1 code.
: Supplying the timing signal@generator 2 with a control code that generates the clock frequency to the I7 bacita filter 51. In the timing signal generator, the internal pulse ■. In addition to (W), three types of 1 non-bringing pulses f1<R) are generated under the control of the control unit of the microphone-Nippon combination coater.
f3 to function as a filter for the corresponding band.
(B), j+ (R) is sent to the large capacity buffer 7 memory 5 and D/A converter 9, and f3 (
B) is supplied to the switched repass filter 51. Switched capacitor filter [1] The transmission characteristics are moved similarly according to the frequency to achieve the function of each band filter. In the above, digital data is audio data corresponding to images, that is, SWS (Still PicLur
In addition to this data, if software information related to external equipment such as a personal computer or other digital signal processing device is added, the video data as a recording medium can be added. Use of disks makes it possible to connect VDPs and computers. Therefore, in addition to the C internal SWS data, external digital data is also inserted into block C as necessary, and the relevant identification information is inserted into the control data in the block to distinguish between internal and external data. Figure 22 shows an example of the identification information signal, in which internal and external digital data identification signs l-Y are inserted at predetermined positions in the call data of CON1 to F, and Yh (f'OJ or If it is "1", it means that there is an external digital data C.As shown in the figure, an internal/external roll identification bit X is also inserted in another predetermined position. If it is rOJ, then it can be assumed that there is control data for internal control (1), and if it is "1", then there is control data for external control (C1). By determining and reading X and Y during playback, it becomes possible to control external devices such as personal computers. Yes, the input video forman 1 to signal contains (J internal and external digital data and]n1 to roll 7') mixed, and such a signal is input to the signal separator 1 and also to the screen processor 8. The separated synchronization signal is applied to the input of the timing signal generator 2. The control 1 to roll data separated by the signal separator 2 is applied to the input of the error corrector 4. Also, internal (@voice) data or external data is sequentially transmitted and stored in the buffer memory 5 for time axis expansion using the f2 (W) timing signal generated by the timing signal generator 2.Next, , is read out from the buffer 7 memory 5 by the f+(R) signal output from the timing generator 2, and applied to the input of the error corrector 3.The internal (audio) or external data subjected to error correction processing is , is applied to the input of the data separator 52.The audio data separated here is applied to the input of the D/A converter 9.The D/A converter converts the digital signal into an ablog signal, The sound lji signal is used. At this time, f2 ('W')
The audio signal is time-axis expanded by a frequency relationship of >fl (R). The corrected control data output from the error corrector 3 is applied to the control code decoder 6. Here, the data output from the internal controller 7, such as the redata collector, is applied to the input of the system controller 7, and the external control data output is The horn is applied to the external cisler interface 53. A digital data control signal according to the bit at position Y in the internal control data, which is one of the outputs of the system controller 7, is applied to the data separator 52. In addition, the data separator 52 applies external data output to the external interface 53. One of the outputs of the system controller 7 is the inflow of meth 5;
It is applied to the read switching control terminal. Other outputs are applied to the control terminal of the timing signal generator 2 and to the screen processor 80 input terminal. This 1Tii side design 11 vessels 'C4;
Also, the digital part is replaced with the black level and output. The brake A7 controller 10 transmits control signals for playback, frame forwarding, etc., and controls the output of the interface 53, which transmits control signals such as playback and frame advance. is an external system
54 external inputs. With this, computer 5
4 can perform various operations. Further, an external output signal from the personal computer 54 (generally, a player control request and SWS playback control can be considered) is applied to an input of the external interface 53. This signal is applied to the input of the system control 7 and processed together with the internal control data. RGB (three primary colors) output of computer 54 and screen processor 8
The processed video output is applied to the input of an external screen processor 55. A control signal from the Pasonic 1/5/I is applied to the control terminal of the screen processor 55. This screen controller has video output and RGB output. The video/RGB composite output can be switched and the output can be adjusted. Note that the keyboard 56 is an input device for a general personal computer. Another example of a video format in which digital data from an external device such as a personal computer and internal SWS data in a VDP are mixed is shown in FIG. In this example, each field contains three blocks C7 to c3 (here, the content is SWS data for explaining a still image (frame 3), and the block C in field 1 is 01 to 01 in field 1).
Block of ~c3 and next field 2 Cl, C2
``1 set of fft 5 blocks [consists of 1 set. Higemen l-2 is external data, and 03 of field 2
It consists of a total of 516 blocks, including block 1-1 of block 1-1), blocks C1 to c3 of field 3, and blocks c1 and c2 of field 4. Furthermore, 0 in field 4
Block 3 produces an image with a black level. The relationship between these fields, block information, and internal and external data identification codes for legmen 1 is shown in FIG. The count contents of the counter 63 are shown.
o, is ``I'', and the data load of each leg 1- is → Knobuf [] tsuku number (represented as ``(''). There is a block diagram of a playback system suitable for playback, where 57 is a circuit that switches and outputs control data and other digital data, and 52 is a circuit that converts SWS data into D/D.
This is a switching circuit that selectively outputs digital data to the A converter 9 and other digital data to the interface circuit 53, respectively. When data is input to the memory 5, 63 is inputted to the pulse of the system clock generator 18 as needed by the clock l-1 every block period.
58 is a data identification code decoder that decodes a data identification code indicating whether the digital data is SWS data or other external data from the control code. 59 indicates the number of blocks constituting each digital data from the control 1-roll code; block number data 1 which decodes the J code and sends it to the comparison circuit 61;
60 is a legmen 1 to number decoder which decodes the code indicating each legmen 1 to number from the control data and outputs it to the C comparison circuit 61. The comparison circuit 61 reads the block of C3WS data from the memory 5 based on the segment number, block number, data identification code, and output of the block counter 63 decoded at steps 58 to 60, and sets the level to 1. , outputs a 1fjl level for reading a block of external data to the switching circuit 52, and generates a pulse to reset the E F 62 when the data reading is completed. It should be noted that among the control data, each decoder 5B. FF 621: Leg 1 is set by the output of the U system RAM section I III unit 7. In this configuration, the data is sequentially transferred from the first data of the hairline 1''1 of FIG. 24 to the mail 5. μ (is inserted, and the data included in leg 1 and leg 1 to 2 is transferred and stored in the buffer. Continuing (, VI) 1.) or when the still image starts to be played back, the tall device 7 (If you turn the 3L grout counter 63 from releg 1, the same +1.'+
+: Marking 5 is defined as a read state. As soon as the reading of the first part of legmen 1-1 is completed, the counter 6ζ
3 becomes "1" and from then on, each time the I T7 "J tsuku" is successively outputted, it increases by 1. In this case, the block corresponding to 1 to Digmen 1, that is, the counter, changes from "0" to "4". ” is the data identification code” 1
” (see FIG. 25), one torque is sent to the switching circuit 52 indicating that it is SWS data, and the block J counter corresponding to segment 2 changes from “5” to “ 10" is the data identification code"o
Therefore, the -L level indicating that it is external data is output to the switching circuit 52. When the counter 63 reaches "11" and all data have been read out, the comparison The circuit 61 releases the FF62.
However, at this F[:Q output)j, the memory 5 stops reading. With the above operation, the content of segment 1 is output as an audio signal from the CI)/Δ converter 9, and the content of segment 1 is output as external data to the interface 53.
It is output to a computer etc. via the . Next, if there is only SWS data for the still image, record f characters Ab and other codes, and also record the SWS data and characters with largely different contents. Next, we will explain the system for 3 degrees or less, which can be applied in many fields if you select the desired value. FIG. 27 is a diagram showing an example of recording of the bit A format of the system, in which each:]control 1-route J-do is a control target and a 4T image and a b block one frame before the digital data. [In addition, for one still image, several seconds of content, text, and other digital data are recorded.In this example, four types of audio are recorded. Figure 28 (△) is an example of sound 1h and character data, (13) is similarly 4 types of data (?) on the car side, and (C) is 4 types of data. Data 1 is data to be compared with external input (Yes. Also,
Data 2 to data 4 are character code 1-. FIG. 29 shows various control codes and corresponding processing contents. =1- is an ASCII code in its entirety. Figure 30 is! !
The video format shown in Figure 27 (I) and Figure 28 (A
) shows the con1 to [1-rules of each frame. FIG. 32 is a block diagram of the SWS decoder in this example of the system. In the figure, a buffer memory 20 is provided for storing the control code of the previous frame, and the control code is read out from this memory, decoded, and thereafter subjected to various processes. The system controller 7 determines whether the digital data is SWS data, character data, or comparison data with an external signal, and controls the supply of each data to each block. It also has a control function for directly using the video signal, setting the screen to a black level, displaying characters in this black area, or adding characters to the video signal in case of IJ. Meanwhile, the operations of the character baranoa 65 and the video processor 8 are controlled to perform video processing. The character buffer 65 is a memory that temporarily stores character codes of characters to be displayed in image composition and the like. The audio/text data in Figure 28 (Δ) is converted to the video A in Figure 27.
The contents of the controller code recorded in block b of each frame when recorded on a format A-mat C recording medium are shown in Figure 30. Generally, video signals are divided into odd fields and even fields. Playback is performed in the order of No. 1.The odd field block a is played first.The play A) internal control code recorded here is:
Since it is processed inside the playback 17, the 5WSI) (adding audio and data to both sides of the playback 1) does not interfere with the playback at all. Next, what about block b? lj
11 Next, play part b, and set the next room control ]-F to the control code in 5WSD. 〔〔〔〔〔〔〔〔〔〔〔〔〕〔〔〔〔〔〔〔〔〔 , images and audio will be supplied to the outside by each signal supplied from the play AI.If it is digital data, read the specified digital data of the previous frame into the buffer memory of the officer. And the screen and audio become meet 2-.Then, the reproduction of C is completed, Q is reproduced, and then the even numbered field is reproduced, and a and b are reproduced in the same way as the odd numbered field. This time, the 5WSD control code recorded in even field b is similarly stored in the even field area of the control code buffer memory.When the reproduction of b is completed, the next frame should be controlled. , has been read into the control code buffer memory in the coder.Next, C is to be played back, but the processing of C in this frame is similar to the odd field. According to the control code read in, the same processing as the odd field is performed, and in parallel, the control code read in this frame is corrected, de-interleaved, and decoded, and control signals are set to each part in the system control. When the playback of C and Q is finished, before playing the next frame, the control signals read in this frame and set in each part are output, and screen, audio, and data processing is performed. Next, Figure 27 and Figure 30 C will be explained in detail.4127
The frame shown in (A) in the figure is reproduced and covered. ΔM, 1] M, DA
When the codes of WO1006018 to DΔW 03006078 are stored in the buffer memory, they are corrected by the error corrector 4, and after the correction process, they are decoded by the ICC synthesis code system system 911 unit 7, and each control signal is used for control output. I hit the latch with ref 1. Note that in this frame, C
Since images and moving images are recorded on the decoder, the video and audio outputs of the decoder are supplied to the outside from the player. Next, frame 1 in FIG. 27 ([3)
Prior to 1J students, each control section in the system control
The signals that were previously used are shifted from shift 1 to
-l～] -C audio output (, L mikot is one. Also, PM is screen mer, -1-, so a video signal that makes the screen black is output.Next Each block is played back in sequence, and the control code for the next frame is read in b℃−゛, and in C, the specified SWS
Digital data is stored in the buffer memory. In this way, for each frame C1 (C) and (D>), the control code is always read into the decoder in advance of one frame to be controlled in order to control the next frame, and Each control is performed using ([).
The (E) frame is controlled by the control code read in the D) frame. First, since the AS does not have an audio output of 5WSD, the SWS digital data of S W S f) is D/A converted, and the still image audio that has been passed through a low-pass filter is output. l) A will output a combination of the video signal and text output from Brake-7. At this point, the character code has not yet been read, so the image output from the player is output. As a matter of course, a stop code is recorded in a of this frame, and the player decodes it internally to play back a still image. Here, SCT is a command for outputting a data group specified from the outside, so unless specified from the outside, neither voice nor characters are output. SW from outside here.
When the second S and the second letter L are specified, the SWS digital data is read from the specified address in the admission buffer I, D/A converted, and the 1''-bus noise is output through. Also, is the character data also 11 buffs? After being read from the memory and stored in a character buffer, it is combined with the video signal output from the playback 17 and supplied to the outside. In this case, the sound is rma IJ"-j, and the text is W M at
ber j are output respectively. Next, if you want to output another voice and text, you can supply another code from outside and do C, then match the short sentences, intermediate characters, etc. and store them in a large capacity buffer memory in association with control code 1~. d3, a skewer is created which can selectively output other digital data including arbitrary reputations and characters. If you want to move from the still image playback state to the next motion ('+), send a 21 (・1"-) signal from the remote control to the play AI. Figure 31 shows (1) frame. (2) Frame time axis "-C" processing is shown in a timing chart.3 Next, we will cover the operation explanation in the block diagram of Fig. 32.The video signal is TV synchronous signal valve 1111 unit 1 input]
It is also applied to the input of the video processor 8. The 1-1°V synchronization signal separated by the TV synchronization signal separator is applied to the input terminal of the timing signal generator 2. The timing signal generator uses the system clock (7, 1
6MHz > to 1-1. Timing signals for each block within the decoder are generated based on the V synchronization signal. In particular, the timing signal fa (CW) temporarily stored in the control code buffer memory 20 is a signal generated at 231-1 to 26H of each field. Also, from the control code buffer memory to the system controller 7
Timing signal f3 to read the control code into
(CR) is a timing signal generated after 271-1 in the even field. f2 (W) is a timing signal that is generated when digital data is taken into the large-capacity buffer memory 5, and is generated during the period from 271-1 to 260 +-1 when data is recorded in block C. It is a timing signal. f+(R) is a timing signal generated when data is read from the large-capacity buffer memory 5. It is generated as a timing signal gC+ when a still image is reproduced, and is dependent on the rimbling frequency of the audio. Here, if f2 (W)>fl (R) in terms of frequency, time axis expansion processing will be performed on the SWS digital data. Each timing is controlled by obtaining control signals from the system controller 7 and generating these various timing signals. T
The video signal outputted from the V synchronizer 1 (the one from which the synchronization signal has been removed is referred to as a signal 8b) is applied to a threshold circuit 1330. In the threshold circuit, after converting into a digital signal string, e [if the amplitude value is larger than the desired level, it will be converted to 11'' in digital 1C, and if it is smaller than the desired level, it will be converted to l-Oj, and so on. ~Y1 row, and supplies it to control row 1 to hard-boiled memory 20 and large-capacity buffer j/memory 5. Go 1 control] - Dobutsufu memory, when the system controller is odd field, odd number - noil 1
Get the address of the controller that stores the control code of ~, or if it is an even field, get the address of the even field, and generate it from the timing signal generator 2.
(CW) signal to store sequentially and go to -C. When the storage of the control code is completed in the even field, the f3 (CR) signal is then subjected to correction processing by the error correction circuit 4 and then applied to the input of the system controller 7. The system controller decodes the code and sets signals to each processing unit. In the case of a code for managing the number of customers in digital data, convert it from ASCII code to binary data, write it to the data management register, and send it to the video processor 8 and the audio changeover switch 6 before playing the next frame.
6 is controlled. Digital data supplied from the threshold circuit 13 is applied to the input terminal of the large capacity buffer memory 5. In this large-capacity buffer, the timing signal f2 is supplied from the timing signal generator.
(W) and the address signal at the time of writing from the system controller are sequentially stored. Next, when the writing of data to the large-capacity buffer 7 memory is completed, in the case of sending,
f+N of timing signal generation 2? ) and the read address signal from the system controller to 1! ? C1 person size I? ! It is supplied from the buffer memory to the input of the read error correction circuit 3. After correction processing and interleaving in the error iJ positive circuit, the SWS digital data sent to the system controller is applied to the input of the 1)/Δ converter 9. After converting the digital signal into an analog signal, the D/Δ converter C (1) is supplied to the outside through a 1-1-pass filter and an audio signal changeover switch 6G.In the case of character data, the system The control signal is sent from the controller to i!7 U and the video processor C through the character buffer 65.
It operates to combine the video signals supplied from the brake and supply them to the outside. Nu late kind of content? 'l In the case of small and character notes, select the selected reading in advance. ]−
The voice character 0 will not be output unless the character 0 is supplied. When a specified code 1- is supplied to the system 911 from the outside, the system controller (deciphers -'l-1~,
Specified SWS data and character data are recorded in the large-capacity buffer 7 memory, and a control code is written to supply the A address to the large-capacity buffer memory and generate a pulse of f+ (R) to the timing signal generator. is supplied to the timing generator, a control signal is also supplied to the D/A converter 9, and a control signal is also supplied to the character buffer, so that specified speech and characters are outputted. Next, if different voices and characters are supplied, the same process will be performed to output the voices and characters.If the digital data is comparison data with an external signal, the system controller will output the data after error correction. In addition, in the case of normal video, analog audio is superimposed and recorded by frequency multiplication, which is generally done, and in this case, the switch 66 and 60, the analog audio is derived as a playback output. 1) Block control data in each of the above is converted into digital data processed by this control data. When inserted in the same frame as the image information, high-speed processing (i-1) is required to reproduce, decode, and override the control data and the image information. For this purpose, a circuit using a bipolar 1-transistor that operates at high speed as a control code processing circuit (such as a circuit with an electric coupling or a Schottoshiki IC) is required, which reduces the size of the circuit and reduces power consumption. The transformation becomes rotation. Therefore, as described above, control 1 to roll data corresponding to digital data and image information to be processed are inserted at least one frame before the insertion frame of the digital data, etc., and this 1-1 control data The processing time for reproducing, de-writing, etc. is set to take a period equivalent to at least one frame. That is, as shown in the timing charts 1 to 1 in FIG. 31, example C of the video A format in FIG. Processing such as correction and decoding is performed during the raw processing of the image of the (△) frame, and then the data processing of the frame is performed according to this control [] - code. It is. In addition, as the amount of information in the control code increases, 1
Control codes are assigned and inserted over corresponding horizontal scanning lines of two fields (odd and even fields) that make up a frame. The mode is shown in FIG. 33, where ■ is a vertical synchronizing signal section, a, b
, c and Q are the same as in the example in Figure 1, and each subscript 1, 2
The numbers 1 indicate odd fields and 2 indicate even fields. An example of each number of scanning lines is shown in FIG. The control code in block b is structured so that interleaving and error correction are completed in two fields, ie, one frame.In block C, interleaving and error correction are performed in each →knob block (see Figure 1). It is designed to be completed. Block b is a variety of control codes and contains important information for controlling equipment, so it is added with error correction codes with high correction ability, such as 1-word sin l'roam correction, 2-word erasure, etc. 17 corrections are made regularly. On the other hand, regarding the digital data of block C, even if some uncorrectability occurs, there is no problem as long as it does not result in abnormal sounds or undecipherable characters. Perform J:
It will be done. FIG. 34 is a diagram showing the error correction of the controller 1], which is recorded in block b.
6 + - 1, 2 fields 2311 to 261'', totaling 81-1, and the total is C288 bytes, but the right effect information capacity is lJε30 by I-'T:iZ, and the remaining 208 bytes are x, y of the jr cube shown in Figure 34
and the parity in the Z direction (I-), Q (there is 1). C corresponds to the number of the word.The word P x P Yo is the parity in the X direction l)X'? 11,
"■ is also the parity in the Y'tJ direction, and the first 1) , which is also the Y-direction check word QY and indicates the Z-direction parity. The same goes for other words expressed by P or Q combinations and subscripts. Note that one word is 8. Here, the word group Wo belonging to the Y7 plane at the left end of the figure,
W, Wzt+, W4111. W4+, %o
, Vht, PYO, QYO, PYI, QYI 1
Two words are used as a frame identification code, which will be described later. First, for error detection, (n, k) = (1
2, 10) No. 79 is configured and detected. This is the third/
1 in Figure 1 corresponds to error detection in the X direction by QX. Next, for error correction, (n, k) every 2H
Construct the code of = (6°4) and correct it. This is the PY in the diagram. This corresponds to Y-direction error correction using Qy. Furthermore, 2HjJ
Correction is performed by constructing a code of U(n, k)=(4,2) for 4 words of 3 times. This corresponds to error correction in the Z direction using IT) 7°Qz in the figure. In this example, error detection and error correction are performed in 8-bit word units, and the atomic element x is P (x
) =x"-+-x'(-x 3+X 2-1-1
root and zuru. However, α-(00000010) is taken. In addition, the check matrix 1-1 is (n; congratulations), and when this is expressed using a matrix 10 in units of 1 pi, it becomes as follows. However, 1 is reversed with a matrix of 8 rows and 8 columns such as the unit matrix C1-1 of 8 rows and 8 columns; 1 superposition. Now, in order to know the location of the error and the content of the error, we need the sind []-m S defined as follows. S= [SP S(]” =l-1・cwn-1,
wn-2°...W2, P, Q]t' P and Q are recorded together with the information word so that Sp=So=O is satisfied in the above equation. There C, when recording the frame identification code in even frames, "0000"
0000'', '001111 for odd frames
In this case, Pvo is set to 10''. The parity of Qvo, Pv+, and Qy+ is ``OOO00000'' for an even frame and ``00111111'' for an odd frame, and can be used as a frame identification code. n between adjacent frames
If a change is made in 21-1- and recorded in (block 1), the change in frame identification code will be detected during playback. It is possible to quickly detect that a moving image is displayed when the signal is changed, and a still image ("it" is displayed when the signal changes). -1-ru 1-
1. A moving/still image detector for extracting and identifying frame identification codes is provided, and the detection output is sent to the system controller 7. This 1 FIJ image/still image detector configuration example is number 53! It is shown in figure j (, (Tari, hereafter)
The structure is as shown below. Frame identification] -1 ~ 3rd part 1 ~ /) r + et al. 7th
In fact, it is necessary to detect whether or not there is
'Gate 350, Libe ('+ (Detect whether there is or not) 'Dogu h 351, J to both goo 1-, Su (0
As soon as (00 Q) and (1111) are detected, the detection pulse is sent to the clock GK and the same IV1 as the next stage)) to the ARA f and KUUNNONOJ nont control terminals of the down counter J352. Among people +111 ruru)'
N1~G1~:s E):s. 354, A-purflow with a count of 16 or more. In order to prevent an underflow of 0 or less, the counter outputs 4 bits Q8, Qe, Qc, and Q so as not to prohibit the input of the detection pulse to the counter. is monitored, and when it reaches 16 or O, it generates a low level signal and closes the gates 353, 354. 2-bit shift 1 to read the most significant bit output of the counter 352 and shift it with a clock synchronized with the frame Detect whether it is a moving image or a still image using the two outputs of the register 356 and shift register 356 and output the detection flag - Shivorgate 357. Among the read control codes, the frame identification code requires high-speed detection, so error correction is not performed, and instead, a 12-word identification code is used to increase reliability and sent to the circuit shown in Figure 35. is input. The input identification code is detected by checking whether the third to seventh bits are all 0 or 1 in h350, 351. If it is O, I will count up 352 to Goo 1, and if it is 1 (
, [Da Cun Count berates. At this time, it/j G8 is reversed, that is, 4 pins (if you set the highest level 1- of ~ to 1, if the frame ID is (0000 (n000)), 1 In other words, while playing an even frame, the most significant bit QL) of the 4-bit output of the gate is always 1, and 11 of <00111110).
110. During playback of odd frames, (, lo is always O.
becomes. As a result, it is possible to know the res 74' of even and odd frames, and the detection of 1 pit r LU Ol:4f. . Here, if only one word of the frame identification code is read, it is possible to detect either a moving image or a still image, but even if J:Riko-II-l; 12 words are recorded. There,
The counter 352 is designed to count the same frame identification code many times. Therefore, the output of the counter) j is A-ba-no7duff11-
It is input to the preventer 355, and when its output becomes 15) or 0, the gate's manual stage's AND GO 1-3! □5 go 3゜3
54 to avoid stopping the count. The most significant bit QD of the output of the power counter 352 is serially input to a 2-pin 1-shift register 356 using a clock synchronized with the frame. At this time, when playing a moving image, the counter outputs input to the shift register are different, so if these are manually input to the goo 1-357, the output will be 1-1. On the other hand, in the case of still image playback, the outputs of the shift 1 to registers make it possible to distinguish between the playback status of a moving image and a still image. This detection output is sent from the system controller 7 to each part of the system and, if necessary, to an external device such as a concave coater via the interface 53.
Wear. = 1 nt 11 - Runi] - As an example of a sen to deal with the increase in the number of containers, kon 1 ~ which responds to 1 frame with 1 ~
Roll = 1-Divide into multiple frames and record C insert [)
(A3<7'j formula can be considered. In this case, ret1:
A schematic block diagram of the system is shown in FIG.
)4-Separator 1, V, l-1 sink and f - Timing signal generator 2.5WSj, which generates the timing signal 8 from the evening synchronization signal to each part of the system; digital audio processor 69, controller, which converts the timing signal into an analog signal; Meshiri 20, Comte [1-
Error correction unit 4 for error correction of control data; end detector 68 for detecting completion of control data;
Denier 1-6 who sells data from memory 20
7. System that receives 11 commands from the side and input information from input devices (2J computers, etc.) and generates control credits to each part of the VDP. Control unit 7, screen processor 8 which performs divine processing for the same day A Shingetsu, and SW Si' - switching between evening output and general A - day A signal 'j'-> A - The processor 70 to 4 responds to a certain frame.
-Router j"-Router multiple frames (7) 7
T a>, then the next frame (-]n i・I]
- Identification of whether the router is continuous or not;
Next, the operation will be explained. At J'3 in the figure, the signal to the video camera A-matsu 1 is applied to the signal separator 1, and the vertical synchronization signal, horizontal synchronization signal, and data The same 1111 signal, controller 1 to roll program, and digital audio data are separated.The separated vertical synchronization signal, horizontal synchronization signal,
The data synchronization signal is applied to a timing signal generator 2;
Generates timing signals to be sent to each part. The digital audio data 4 and 6 digital audio processors are written to the buffer memory of the IC, and after error correction, time! 111 decompression readout and a D/A converter to extract it as an analog audio signal. The control data is written into the buffer memory 20, and the error corrector 4 corrects the error π1. At this time, the data end detector 68
Detects an identification signal indicating whether the roll data is completely overturned or continuously overturned in the next frame. Control 1 - When the roll data continues to the next frame, the buffer memory 20
The control data within is not sent to the decoder 67 and is held as is. Ma1=, Control 1-Roll data is complete J
- At this point, the decoder 67 reads and decodes the 11th to 1st grams in the buffer memory 20. The system controller 7 receives control commands from the decoder, information from the human headset, and subbutus signals from the player, and generates a timing signal generator, a digital audio processor, a double-sided processor,
Audio signal processor, J3 and video A/F screener X7
various control signals are sent to the The screen processor 8 performs functions such as masking the digital audio data portion of the signal input to the Deoff A-Matsu 1 and turning the TV screen black, and superimposing characters and graphics. , video signal output. The audio signal processor 70 demodulates the digital audio data t'h Nj (1. Play 17 control for switching between the ij signal and the sound signal panono (the ij signal is the play 17
[11 is added to the control input terminal of the controller Tl-1 to control normal playback, sub-O-1 output, frame No. 71-1, etc. Next, by recording ordinary moving images (audio, qsa), and SWS on a recording medium, it is possible to diversify the so-called digital A software 1. In this case, for example, each frame is One possible method is to record an identification code between the normal video and the SWS in advance, read this identification code during playback, and switch the playback operation accordingly. As is done on video discs, the audio remains in analog form, for example 2.
The audio subcarrier of 1 MHz (in stereo, 2°3 M l-I Z) is FM modulated and frequency multiplexed with video information (this video signal is also FM) and recorded. In the case of still images The digital SWS
Data is inserted into block C, time-division multiplexed, and recorded. FIG. 37 shows the contents of the control code in such a case, in which the upper 4 bits of the 8-bit configuration are the output horn control code, and the lower 4 bits are the input control code. The output control code is a ]-code to distinguish between stereo and monaural, and the input control code is for selecting SWS data when monaural, or c] for analog audio.
It determines whether to select 11 or c112, or to mute, and logic ``1'' selects, and ``o'' indicates non-select. still,
X is a bit not involved in control, and in this example it is assumed that it is forcibly set to "O". By the way, A's 11
4, A-dio input is VDP 2c1) stereo playback horn (frequency multiplexed recording but ilj <
l output) is selected, and the priority is "S-R A".
Gai! '! + becomes J5, logic to stay-A” 1
” is made so that other bits become irrelevant. FIG. 6-bit latch 71 for temporarily storing (Fig. 37), the output of this latch 71 is connected to the output of J, S, voice; 1 to roll ni I-l” /j) A protection circuit 72 and this circuit 7 that operate so as not to cause a failure when the F&4 data is legged without being able to be corrected.
7'4 t' controlled by 8 > , 17 by the output of 2
: Selection relay 1 (Y1 to RY6 is shown on the right. Figure 39 shows ]n 1 to 1 to 1 to relay 1<Y1 to
This is a diagram showing the operational relationship of RY6, with logic 1 in monaural.
The same sound is heard from the R output, and the bottom 4 hits (
The audio source specified in (see FIG. 37) is output. When a logic 1 occurs in C1]1, the lch output of VD I) is output, and when a logic 1 occurs in ch2, the VDP Rcb output is output, respectively.In general, audio with different content is inserted into a video. This is used when the user is asked to select according to his or her preference. When SWS is set to logic 1, the time-base compressed SWS data is subjected to time-base expansion processing, D/A converted, and output as analog audio. Furthermore, when a logic 1 is set to mu1, no audio output is produced. FIG. 40 is a J diagram showing an example of the protection circuit of FIG. 38,
It is constituted by an inverter and an AND gate using 6 bits 1 to 1 excluding 2 bits 1 to shown by X in FIG. FIG. 41 is a diagram showing the video mat of this example. In the period Δ, the SWS data is inserted into the entire block C, so the audio is set to MU1~. Therefore, the SWS data is sequentially stored in the buffer memory 5 while being played back as a moving image. Note that the code during this time is 11. Period B
4T, VI) P will play a still image, but at this time the SWS data stored in menu 5 will be +l\17! I+Iql+is expanded and read out from the memory as 1, and the analogized audio of this SWS data is derived as 1, and the code in between is 18. In period C, the SWS data is stored in memory and the video is replayed four times, but the audio at this time is cl+1,
Replay the sound of cl+2: V (there. The code at this time is 80). Read from memory 1j L r 16r 17i1 +Iq# Expanded and output as audio -C1 During this time -1-1-
is 18T'. Next, J) of f-internal data is one, +( is about il, -
LX 'IJ states. First, referring to FIG. 42, the equivalent is conventionally shown in the block diagram of the data separation 1 circuit in J3.
422 is a comparator that compares digital data at a threshold (threshold co-hold) Vo and shapes the waveform to a digital signal of 1.0; 423 is a detector that detects V sync; 4.24. l;L PLL with V sink as input
(face 'locked loop) circuit, 425 is a data synchronization (DS>pulse taken out t l') S detector inserted at the front of the data in the 1'' section, and 426 is a DS pulse from the clock from PLL 424. Generates the reference signal for data read lock (DCK)
A circuit 427 is outputted from the reset circuit 426, and a delay circuit 428 is used to avoid delaying the rising edge of the data at the center of each bit interval, and 428 is a delay circuit based on DCK from the delay circuit 427. Read data 1: “
It is. Here, an enlarged partial waveform diagram of the digital data including the DS pulse of the digital signal waveform in the section 11-1 shown in FIG. 11 is shown in FIG. 43(a).
The field is pedestally clamped by a clamper 421, and waveform-shaped by a comparator 422 as a digital signal of 1.0 according to a threshold value VD as shown in the 713th output). On the other hand, the PI 1424 operates based on the sync detected by the detector/I23, and a clock with four times the data bit rate frequency is output as shown in the figure. is detected as shown in Figure (C), and the reset circuit/
Activate 126 movements! Then, the clock from the PLL 424 (point A in the figure) is reset and the clock having the same frequency as the data bit rate h is output as shown in the figure (C41). The delay circuit 427 generates DCK as shown in ([) by delaying the signal [] by 8 so that the rising edge of the data occurs at the center of each interval.This 1] OK
becomes the Syscam clock.'' L to l l /I 28
0) Used as a clock, data synchronized with this DCK can be obtained as a read output. In the circuit system shown in FIG. 42, the slice level (threshold (iFj level) , does not follow the amplitude fluctuation of the human input signal and remains constant <1. Therefore, accurate data slicing is impossible, and data reading is not accurate. Also, the DCK reference clock The relet point for generating (e) should be precisely the falling point of the DS pulse (C+), but in reality it is the rising point of the tarok pulse ((1)).
) is reset. For this reason, the clock (e) causes a phase shift by one period of the maximum clock pulse (small), and in the end, it is not possible to obtain a DCK that exactly matches the data phase. For example, in order to read the data of the first section as the DCK phase reference,
If the DS pulse shown in the figure cannot be detected due to dropout, etc., or is detected at the wrong position,
If one section is not correctly read, a data reading error occurs. In the past, instead of generating a DCK in such a manner, a DCK that constantly monitors and follows data reversal is used.
If a method of generating Pl-1- is adopted, for example, a method using Pl-1-, the above-mentioned drawbacks can be solved to some extent, but not completely. Therefore, by using the field sync data shown in Figure @10, which is inserted in block a at the forefront of the field, a so-called ATC (automatic threshold control) circuit is constructed using this data. A concrete example of the block is shown in Fig. 4/I. When the video A format signal is pedestally clamped by the pedestal clamper 421, this clamper 4
Pedestal level VI) is output from 21 to video hook 1 and video hook 1. Since other image signals of digital signals are also present in the signal, only the digital signal is gated in gate circuit 429. be done. In the next peak bold circuit 430, the positive peak of the digital signal is bolded, and the previous pedestal level Vp and this bold output are equally divided by the resistors R+ and R2, and this is set as the threshold level by the comparator/I22.
Becoming a one-man force. This threshold level and the output of the clamper 421 are compared in level and waveform shaped. Out of this comparator output, only the digital data is gated in the GOO circuit 431, and a pulse that rises when the GOO1~ output is inverted is generated in the clock extractor 432. The I
) CK is generated by the PLL circuit 43/I. This D
Digital data synchronized with DCK is read by F F 428 which uses CK as a clock input and the output of comparator 422 as a data input. In the peak bold circuit 4.30, the time constant of C is selected to be large so as not to follow drastic amplitude changes due to data top-out or noise. In this way, the field sync data that has been inserted at the front of the field is J, peak hold and P L.
Since the lock of L is maintained for a certain period of time, even if images continue and digital data arrives thereafter, peak hold and PLL lock can be performed immediately, and stable data separation is possible. It should be noted that, if the PLL lock is lost in the middle of the field, it is no longer possible to lock it by the DS signal immediately before the digital data -b1 as shown in FIG. If the interval between image signals 1111 is long to some extent, l) 1
．． -1- is in danger of becoming unlocked, so the 4th
;] As shown in the figure, a pulse of several Hz synchronized with the clock synchronization signal is inserted at the beginning of each 1-1 bright interval to which the image signal belongs (for example, P in the middle of the field).
Even if the L L11 lock is released, the P L L can be locked by the next one-tick pulse. In the above example, the method 1) using PLL434 is used, but the method shown in FIG.
It is okay to use. For example, each block 431 to 434 in Figure 4/I is replaced with 423 to 42 in Figure 42.
You can change it to each block of 7. By the way, as shown in Fig. 4, the clock run-in signal and I) S signal are intermediated at the front of the digital f-9, but in the method shown in Fig. 42, a part of this signal is There is a device that detects and performs a C switch (because there is one, it works well as long as almost the whole of this signal is 4f). In addition, unless a lock is inserted before the image signal using the relet method (-1°L, as shown in Fig. 45), relet is not performed during the image signal period, so the phase of If the deviation is superimposed and the data changes to digital data again, if the corresponding [] vine signal is missing from drop alarm 1~, then the 11th section reset! is not obtained and is incorrect?iTr? The data is read, but the 45th
Since the clock signal is inserted at the beginning of each "I" as shown in the figure, the above-mentioned inaccuracy is eliminated. However, in this one-way reset method, it is unavoidable that a shift of at most one cycle occurs. In the above explanation, a video A disc was described as a recording medium, but a video tape or the like may also be used.
- In addition to SWS audio data, matted digital data includes text information, storage information in the mechanical field, medical information such as electrocardiograms in the medical field, and physical information such as temperature. Information etc. can also be included. This digital data can be processed using straight line or broken line PCM method, adaptive differential 1) CM (ADPCM> or A
A divine encoding method such as DM can be used. Furthermore, the video signal type can be other than the Mtsc system, such as the 1]△L or SECAMIj system. It is clear that the number is not limited to the example shown in Fig. 3 and can be modified in various ways.As described above, according to the present invention, a clock synchronization pulse is also inserted in the image signal part. In particular, the following effects can be obtained: (1) l) One type is used for every four parts of CK. f) Generates CK-(
Wear. (2) Also, compared to the conventional Noricera 1 ~ method - (1) 1
- Since the method monitors the data reversal, it is used like a data sync pulse in the conventional Riketno) method. As mentioned in the previous section), when the method of this invention is used, the clock 1ii 1st period pulse (see Figure 45) and the clock Since the reset is performed by detecting a part of the spot pattern in the run-in (see Figure 10), the conventional NoriSera 1 method is not affected by the re-reg 1 I-out of the ground. No. (Table-1) (Table-2)

[Brief explanation of drawings]

? ? , Fig. 1 is a diagram showing the block division mode of both tJ3t and 1/1 field according to the present invention, Fig. 2 is an enlarged view of the hidden A/A-mat signal, and Fig. 3 is a close-up view of 1st
Figure 4 shows an example of the number of horizontal scanning lines of the block in the figure. Figure 4 shows an example of the number of digital data in 11-1.
Figures to Figures 7 and 7 show the manner in which images are inserted into Digital i2-Yu, Figure 1 and Figure 8 are Video Format 1 by Mitsuaki Ki.
- Signal recording formula 1 is shown in Figure 9.
The figure shows an example of the 71.1 ivy of the re-q2 system.
Fig. 11 (11-1 of digital data of J/C
Figure 1 shows an example of the waveform for 1 minute, Figure 12 shows another example of the waveform of the reproduction system, and Figure 13 shows the waveform example 1 of the data synchronization detector in Figure 12. -1 system circuit diagram, Figure 1/I is control 1-
Figure 1 shows an example of 1.
1-1 A diagram showing another example of the ivy, and FIG. 16 shows the operation of the block in FIG. 15.
The figure shows yet another example of the ITJ cow type block.
Figure ε3 shows an example of video A software, Figure 19 shows another example of playback system blocks, Figure 20 shows another example of video software, and Figure 21 (J FIG. 22 is a diagram showing another example of the reproduction system; FIG. 22 is a diagram showing another example of control data; FIG. 23 is a diagram showing still another example of the reproduction system blocks; FIG. The figure shows another example of the video software (-), Figure 25 shows the relationship between block C and the data identification code, Figure 26 shows yet another example of the playback system, and Figure 27. Figure 28 shows still another example of the video A software 1-.
The figure shows the content of digital data, Figures 29 and 30 show examples of control data, and Figure 3 shows examples of control data.
Figure 1 does not show the operation timing of the playback system for the video A/SO 71 in Figure 27, Figure 32 shows another example of the playback system, and Figure 33 shows the operation timing of the playback system. ] Figure 3/I is a diagram showing an example of insertion into the video format signal of roll data; Figure 3/I is a diagram explaining the error correction method for control data; 36 is a diagram showing another example of a playback system block, FIG. 37 is a diagram showing an example of control 1"-control data, and FIG. Figure 3 showing another example of the block of
Figure 9 shows the control data in Figure 37 and sound 7 in Figure 38.
)・The operational relationship with the switching relay is shown in Figure 1IO.
Figure 42 is a block diagram of a conventional example of the data portion H section; Figure 43 is a waveform diagram of each part that explains the operation of block 1 in Figure 31 and Figure 712; FIG. 114 is a block diagram of the data portion H portion used in the present invention, and FIG. 15 is a diagram showing an example of the 111-hi waveform used in the block of FIG. 44. Explanation of symbols of main parts 1... Signal separator 2... Timing Shinzuki Kojuki 3.4... Error correction circuit 5... Time axis expansion Menu 6... Control code decoder 7...
...System controller 8...Screen processor 9...D/A converter 10...Player controller Applicant: Buy A Near Co., Ltd. Agent Patent attorney: Motohiko Fujimura (1 other person)

Claims (1)

[Claims] When inserting and recording digitized digital data of predetermined information into a video format signal, if the digital data and image information are mixed in the same field, a tarok signal synchronized with the clock timing of the digital data is inserted. A recording method for a Zuruji-def A-matte signal, characterized in that the digital data is inserted and recorded not only in the horizontal scanning section in which the digital data is inserted, but also in the horizontal scanning section in which the image information is inserted.