JPS6062712A - Noise blanker circuit - Google Patents

Noise blanker circuit

Info

Publication number
JPS6062712A
JPS6062712A JP17086783A JP17086783A JPS6062712A JP S6062712 A JPS6062712 A JP S6062712A JP 17086783 A JP17086783 A JP 17086783A JP 17086783 A JP17086783 A JP 17086783A JP S6062712 A JPS6062712 A JP S6062712A
Authority
JP
Japan
Prior art keywords
noise
agc
circuit
signal
amplification stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17086783A
Other languages
Japanese (ja)
Other versions
JPH0152943B2 (en
Inventor
Takeaki Ohira
武昭 大平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaesu Musen Co Ltd
Original Assignee
Yaesu Musen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaesu Musen Co Ltd filed Critical Yaesu Musen Co Ltd
Priority to JP17086783A priority Critical patent/JPS6062712A/en
Publication of JPS6062712A publication Critical patent/JPS6062712A/en
Publication of JPH0152943B2 publication Critical patent/JPH0152943B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/34Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
    • H03G3/345Muting during a short period of time when noise pulses are detected, i.e. blanking

Abstract

PURPOSE:To decrease a noise pulse of a large amplitude at a noise amplifier stage from being detoured to signal circuits after a noise gate by providing the 2nd AGC which decreases an output of the noise pulse having an amplitude of a set value or over. CONSTITUTION:The noise gate 2 provided at a signal passing stage of a radio receiver is controlled by a noise blanker circuit so as to eliminate a pulse noise mixed in a reception signal. A noise amplifier stage 5B of the noise blanker circuit is controlled by the 2nd AGC9 of a type decreasing an output of the noise pulse of the amplitude of the set value or over in addition to the 1st AGC7 to make a noise signal component output constant thereby uniforming the noise pulse output and also preventing generation of a noise pulse with a large amplitude to the noise amplifier stage 5B and succeeding stages.

Description

【発明の詳細な説明】 この発明は無線受信機の信号通過段(主に第1中間周波
段)に設けたノイズ・f−)を制御して受信信号に混在
するノfルス性ノイズを除去すべくしたノイズ・ブラン
カ回路において、ノイズ増幅段で増幅された大振幅のノ
イズ・パルスが、ノイズ・ダート以後の信号回路に回シ
込むことによシ、ノイズ・ブランカとしての性能を低下
するのを改善するにある。
Detailed Description of the Invention The present invention controls the noise f-) provided in the signal passing stage (mainly the first intermediate frequency stage) of a radio receiver to remove noise noise mixed in the received signal. In the desired noise blanker circuit, the large-amplitude noise pulses amplified by the noise amplification stage will inject into the signal circuit after the noise dart, thereby degrading the performance as a noise blanker. The goal is to improve.

ノイズ・ブランカ回路は高感度無線受信機においては普
偏的に使用されている、特にパルス性ノイズを効果的に
除去する回路であって、最近はFM受信機ではAF段で
類似回路が使用されているが、ここでは本来の前段部で
パルス性ノイズを除去する回路を称してお夛、その一般
的構成例を第1図に示す。信号以外の不要成分はなるべ
く前段部で除去するのが望ましく、その第1の理由は回
路(特にアクティブ回路)を重ねるほど、また増幅され
て振幅が大きくなるほど、受信信号と隣接信号やノイズ
の不要成分との間の混変調や相互変調によって分離が不
可能になること、第2には帯域間の狭いフィルタを通る
ほどノ4ルス波の経過時間が延びてブランキングによる
除去が困難になることがある。従って基本的には第1図
の回路構成例に示すように、中間周波段の最前段部、第
1ミクサの出力部にノイズ・r−)を置き、またダート
の入力側から分岐してノイズ増幅段を通してノイズ整流
して得たノイズ・ノ4ルスをダート制御部で波形成形そ
の他の操作(単にパルスを制御に必要な極性とレベルに
増幅する場合とシュミット・トリガ等で制御/4’ルス
を発生する場合とがある)を行い、ノイズ・ノ臂ルスが
ダートを通過する期間中はダートを閉鎖してノイズ・ノ
クルスの通過を阻止するものである。ff−)通過後は
信号通過に必要な、なるべく狭帯域なIFフィルタを通
して隣接信号を除去している。またゲート前段のIFフ
ィルタは信号回路にわずかな時間遅延を与えてダート制
御信号とのタイミングを合わせるのを主目的とし、i4
ルス波形の鈍化を減するために帯域幅は後段の主フィル
タの数倍以上としている。
Noise blanker circuits are commonly used in high-sensitivity radio receivers, and are particularly effective at removing pulse noise.Recently, similar circuits have been used in the AF stage of FM receivers. However, here, we will refer to the circuit that originally removes pulse noise in the front stage, and an example of its general configuration is shown in FIG. It is desirable to remove unnecessary components other than the signal in the front stage as much as possible.The first reason is that the more circuits (especially active circuits) are stacked, and the more the amplitude is amplified, the more unnecessary components such as adjacent signals and noise will be removed from the received signal. Separation becomes impossible due to cross-modulation and intermodulation between the two components.Secondly, the elapsed time of the Norse wave increases as it passes through a filter with a narrow band, making removal by blanking difficult. There is. Therefore, basically, as shown in the circuit configuration example in Figure 1, the noise (r-) is placed at the front end of the intermediate frequency stage, at the output of the first mixer, and the noise is branched from the input side of the dart. The noise/noise obtained by rectifying the noise through the amplification stage is used for waveform shaping and other operations in the dart control section (in cases where the pulse is simply amplified to the polarity and level required for control, and when controlled with a Schmitt trigger, etc.) ), and during the period when the noise noculus passes through the dirt, the dirt is closed to prevent the noise noculus from passing through. ff-) After passing through, adjacent signals are removed through an IF filter with as narrow a band as possible, which is necessary for signal passage. The main purpose of the IF filter before the gate is to provide a slight time delay to the signal circuit to match the timing with the dart control signal.
In order to reduce the blunting of the pulse waveform, the bandwidth is set to be several times or more that of the main filter in the subsequent stage.

このようにノイズ・ブランカをIF前段部に置いた場合
の信号レベルは数10μVからmVのオーダーである。
When the noise blanker is placed in the front stage of the IF in this way, the signal level is on the order of several tens of μV to mV.

除去すべきノイズ・パルスは信号の数倍程度以上のピー
ク値のものが対象となるが、これをノイズ整流に必要な
1v程度のレベルまで増幅するノイズ増幅段は千倍ない
し数千倍の高増幅度とする必要があシ、特に強力のノイ
ズ・ノ4ルスが入力した場合にはノイズ増幅段出力はI
OV以上にも達することに彦る。そのような高レベルの
ノイズは他の回路に回シ込みを生じ易く、ノイズ・ダー
ト以後に混入するとノイズ・ブランカの効果を殺滅する
ことになるため、ノイズ増幅・整流部を厳重にシールド
したシ、配置上もダートやIF回路と接近しないようK
しなければならない等の制約を受けることになる。
The noise pulses to be removed are those whose peak value is several times that of the signal or more, but the noise amplification stage that amplifies this to the level of about 1V required for noise rectification is a thousand or several thousand times higher. It is necessary to increase the amplification level, especially when a strong noise noise is input, the output of the noise amplification stage is
I'm excited to reach even more than OV. Such high-level noise tends to be transmitted to other circuits, and if it enters after the noise dirt, it will destroy the effect of the noise blanker, so the noise amplification/rectification section must be strictly shielded. Also, be careful not to get close to dirt or IF circuits in terms of layout.
You will be subject to restrictions such as having to do the following.

第2図はノイズ・ブランカの従来回路例のプロ、り図で
あって、1は広帯域IFフィルタ、2はノイズ・ダート
、3は狭帯域IFフィルタ、4はIP増幅段であって第
1図の構成と同様である。また5Aはノイズ増幅段、6
は整流器、7は整流出力の直流分を増幅してノイズ増幅
段にAGCを掛けるためのAGC電圧増幅器であって、
AM受信機一般の(5) AGCと同様に、信号の振幅変調度に無関係に振幅平均
値に比例するAGC制御電圧をノイズ増幅段に加えて、
信号出力がなるべく一定値になるように構成し、信号出
力の最大値を越えた付近に設定したスレシ璽−ルト・レ
ベルlJするノイズe ノ4ルスヲ検出・整流してダー
ト制御部8Aに加えている。この回路の動作例を第4図
囚に図解して示す。図において■はノイズ増幅器5Aに
入力するIF倍信号あシ、■は入力信号の整流平均値で
動作するAGC(1)でAGO電圧増幅器7で十分に増
幅したAGC電圧をノイズ増幅段5Aに加えるため、大
振幅の信号は抑圧されてその出力は■のa−bのように
均一化される。
Figure 2 is a diagram of a conventional circuit example of a noise blanker, in which 1 is a wideband IF filter, 2 is a noise dirt, 3 is a narrowband IF filter, and 4 is an IP amplification stage. The configuration is similar to that of . Also, 5A is a noise amplification stage, and 6A is a noise amplification stage.
is a rectifier; 7 is an AGC voltage amplifier for amplifying the DC component of the rectified output and applying AGC to the noise amplification stage;
(5) Similar to AGC in general AM receivers, an AGC control voltage proportional to the average amplitude value is applied to the noise amplification stage, regardless of the amplitude modulation degree of the signal.
The configuration is such that the signal output is as constant as possible, and the threshold level is set near the maximum value of the signal output. There is. An example of the operation of this circuit is illustrated in FIG. In the figure, ■ is the IF multiplied signal input to the noise amplifier 5A, and ■ is the AGC (1) that operates with the rectified average value of the input signal, which applies the AGC voltage sufficiently amplified by the AGO voltage amplifier 7 to the noise amplification stage 5A. Therefore, large amplitude signals are suppressed and their outputs are made uniform as shown in (a) to (b).

一方でノイズ・ノ臂ルスは持続時間が非常に短いため、
たとえ振幅は信号の数倍と大きくても平均値は極めて小
さくなるため、■のAGC(1)出力にはほとんど現わ
れず、従ってノイズ・ノ4ルスはフルに増幅されて、ノ
イズ増幅段の後段部からノイズ整流出力部には大振幅の
ノ9ルス■が現われる。ダート制御部8Aの出力は■で
ある。このようにAGCは平均値形あるいは平均値形に
近い機能である(6) ため、ノイズ・パルスのように持続時間の非常に短い入
力に対してはほとんど全(AGC作用をしないので、大
振幅のノイズ・パルスがノイズ・デート以後の段に回)
込む作用については第1図について述べたと同様である
On the other hand, noise noise has a very short duration, so
Even if the amplitude is several times as large as the signal, the average value will be extremely small, so it will hardly appear in the AGC (1) output in (2), so the noise noise will be fully amplified and will be transmitted to the rear stage of the noise amplification stage. A large-amplitude noise appears at the noise rectification output section. The output of the dart control section 8A is ■. In this way, AGC is an average value type or a function close to an average value type (6). Therefore, for very short-duration inputs such as noise pulses, it has almost no full (AGC effect), so large amplitude (noise pulses are repeated in stages after the noise date)
The filling effect is the same as that described with respect to FIG.

本発明はそのような問題点に対処するためKなされたも
のであって、無線受信機の信号通過段に設けたノイズ・
ダートを制御して受信信号に混在するノ9ルス性ノイズ
を除去すべくしたノイズ・ブランカ回路のノイズ増幅段
に信号分出力を一定とする形式のAGCを掛けることに
よりノイズ・7母ルスを分離してノイズ・r−ト制御を
する回路において、前記信号分出力を一定とする形式の
第1のAGCの他に、設定値以上の振幅のノイズ・ノ々
ルスの出力を低減する形式の第2のAGCを設けること
により、ノイズ増幅段の大振幅のノイズ・・やルスがノ
イズ・?−)以後の信号回路に回り込むことを軽減すべ
くしたノイズ・ブランカ回路である。
The present invention has been made in order to deal with such problems, and the present invention has been made to address such problems.
Noise and 7 Lus are separated by multiplying the noise amplification stage of the noise blanker circuit, which controls dirt and eliminates 9 Lus noise mixed in the received signal, by applying AGC that keeps the signal output constant. In addition to the first AGC that keeps the output of the signal constant, the circuit that controls the noise and noise r-t controls the circuit that reduces the output of noise noise having an amplitude greater than a set value. By providing No. 2 AGC, large-amplitude noise in the noise amplification stage and pulses can be reduced to noise. -) This is a noise blanker circuit designed to reduce the noise that goes around to subsequent signal circuits.

第3図は本発明の詳細な説明する基本回路ブロック図で
あって、1は広帯域IFフィルタ、2はノイズ・r−)
、3は狭帯域IFフィルタ、4はIF増幅段であって第
1図および第2図の構成と同様である。また5Bはノイ
ズ増幅段、6は整流器、7は整流出力の直流分を増幅し
てノイズ増幅段5Bに第1のAGC(1)を掛けるため
のAGC電圧増幅器、8Bはff−)制御部であって、
6で検出・整流されたノイズ・パルスを波形成形その他
、ノイズ・ダートの制御に必要な操作を行うと同時に、
一定振幅以上のノイズ・ノ母ルスにより動作する第2の
AGO(2)出力を得て、これをAGC電圧増幅器9を
通してノイズ増幅段5BK第2のAGCを加えることに
より、ノイズ増幅段以後に大振幅のノイズ・ノ4ルスが
発生するのを防止する構成である。図ではAGC(1)
とAGC(2)とはノイズ増幅段5Bに対して別に加え
ているが、両方のAGCを合成して1個所に加えるよう
にしてもよい。この回路の動作例を第4図(B)に図解
して示す。図においてノイズ増幅段5Bに第4図(B)
■のようなノイズ・ノ4ルスを含むIF倍信号入力する
と平均値形AGC(1)は■のようになり、r−ト制御
部8Bで分離したノイズ・i4ルスによるAGC(2)
は■である。ノイズ増幅段には信号AGC(1)とノJ
?ルスAGC(2)が動作する結果、その出力は■のよ
うにノイズ・ノ4ルス出力も均一化されている。
FIG. 3 is a basic circuit block diagram explaining the present invention in detail, in which 1 is a wideband IF filter, 2 is a noise r-)
, 3 is a narrow band IF filter, and 4 is an IF amplification stage, which has the same structure as in FIGS. 1 and 2. Further, 5B is a noise amplification stage, 6 is a rectifier, 7 is an AGC voltage amplifier for amplifying the DC component of the rectified output and multiplied by the first AGC (1) on the noise amplification stage 5B, and 8B is an ff-) control section. There it is,
At the same time, the noise pulse detected and rectified in step 6 is subjected to waveform shaping and other operations necessary for noise/dart control.
By obtaining the output of the second AGO (2) that operates with a noise pulse of a certain amplitude or more, and adding this to the second AGC of the noise amplification stage 5BK through the AGC voltage amplifier 9, it is possible to generate a large output after the noise amplification stage. This configuration prevents amplitude noise from occurring. In the figure, AGC (1)
and AGC(2) are added separately to the noise amplification stage 5B, but both AGCs may be combined and added to one location. An example of the operation of this circuit is illustrated in FIG. 4(B). In the figure, the noise amplification stage 5B is shown in Fig. 4 (B).
When inputting an IF multiplied signal containing noise and noise as shown in ■, the average value type AGC (1) becomes as shown in ■, and AGC (2) with noise and noise separated by r-to control unit 8B.
is ■. The noise amplification stage has signals AGC (1) and No.
? As a result of the operation of the Lux AGC (2), the noise and Lux output are also made uniform as shown in (2).

本発明の特許請求の範囲第2項には本発明の実施上で有
効なAGC回路の構成を提示している。すなわち、第5
図においてノイズ増幅段の整流出力■を抵抗R,と容量
Cとよシなる積分形時定数回路を通してAGC)ランジ
スタQlのペースに加え、そのコレクタ電位■の変化を
ノイズ増幅段のAGCとして供給する構成と、エミ、り
に/イオードD1を直列接続した?−)制御トランジス
タQtのペースにノイズ増幅段の整流出力■を加え、Q
lのコレクタとQlのコレクタとをダイオードD2で連
結する構成とすることによ、9.1’−)制御パルス■
の発生時に、AGC増幅トランジスタQlのコレクタに
信号とノイズ・パルスの双方に動作するAGC電圧■を
得ることを特徴とするノイズ・ブランカ回路である0 AGC増幅トランジスタQlの入力側の積分型時(9) 定数回路は例えばR1=10にΩ、C=10μF1時定
数=0.1秒とすれば、は#’!’100Hz以上のり
ラブル分は平均化されるので、Qlで増幅された出力は
第6図■のようになり、周波数成分の高いノイズ・ノ臂
ルスは除去されている。ダート制御トランジスタQ寓に
は抵抗R2を経て整流出力■が加わるが、そのエミッタ
に直列に入れたダイオードD1の初期電圧(シリコン・
ダイオードでは0.6V前後である)が逆バイアスとし
て加わるので、Qzのペース・バイアスの初期値(これ
も0.6V位)と合わせて約1.2v以下の入力ではQ
lは導通しないので、■中の信号出力のピークが1.2
v以下にAGC(1)で抑圧されていればQlは動作せ
ず、それよシ振幅の大きいノイズ・ノ4ルスによっての
みQ3の出力■が現われることになる。抵抗R2は寄制
振動防止のためには1にΩ以下の小抵抗が用いられるが
、整流出力■が大き過ぎる場合には入力レベル調整用と
して必要な抵抗値を採用することもある。Qlがオフの
状態では電源vccよシ抵抗FL5を通ってノイズ−f
−)部のダート・ダ(10) イオードに破線矢印のように導通電流が流れている。(
図のノイズ・ダート部は原理的に最も簡単な構成で示し
である)。Q2にノイズ・パルスが入力してQxが導通
すると抵抗R11による電圧降下でコレクタ電位は■の
ように低下し、その期間はダート・ダイオードは非導通
となって、ノイズ・ダートの作用をしている。本発明で
は■の電圧変化をノイズ・ノ臂ルスのAGCに利用する
のに際して、QlとQ3のコレクタ間をダイオードD!
で接続する構成としたのが特徴である。D!はQl側の
電圧変化がQl側に印加されるが、Ql側の電圧変化は
Q3側に影響しないような極性とし、両回路の電位差V
Dを適当に保つためにツェナ・ダイオード、ダイオード
の順電圧降下および、これ等を直列として使用する。こ
のようにして合成されたAGC電圧Oがノイズ増幅段に
加えられる結果として、第6図最上段のような入力中の
大振幅のパルスも抑圧されて■のように均一化されるも
のである。第5図において、QtsQsはもともとそれ
ぞれの用途に必要な回路であシ、これにD8を追加する
のみで所望のAGC動作が得られるのみならず、AGC
(1)とAGC(2)を別個にノイズ増幅段に加える構
成での相互干渉を考慮する必要が無い利益がある。
Claim 2 of the present invention presents a configuration of an AGC circuit that is effective in implementing the present invention. That is, the fifth
In the figure, the rectified output ■ of the noise amplification stage is added to the pace of the transistor Ql (AGC) through an integral time constant circuit consisting of a resistor R and a capacitor C, and the change in the collector potential ■ is supplied as the AGC of the noise amplification stage. Is the configuration and Emi, Rini/iode D1 connected in series? −) Add the rectified output ■ of the noise amplification stage to the pace of the control transistor Qt, and
By configuring the collector of l and the collector of Ql to be connected by diode D2, 9.1'-) control pulse ■
This is a noise blanker circuit characterized by obtaining an AGC voltage ■ that operates on both signals and noise pulses at the collector of the AGC amplification transistor Ql when 0 occurs. 9) In the constant circuit, for example, if R1 = 10Ω, C = 10 μF, and time constant = 0.1 seconds, then #'! Since the noise of 100 Hz or more is averaged, the output amplified by Ql becomes as shown in FIG. 6, and noise noise with high frequency components is removed. A rectified output is applied to the dirt control transistor Q through a resistor R2, but the initial voltage of the diode D1 (silicon) connected in series with its emitter is
(For a diode, it is around 0.6V) is added as a reverse bias, so when combined with the initial value of Qz pace bias (also around 0.6V), if the input is about 1.2V or less, Q
Since l is not conductive, the peak of the signal output in ■ is 1.2
If it is suppressed below v by AGC (1), Ql will not operate, and the output of Q3 will appear only due to noise noise with a larger amplitude. For the resistor R2, a small resistor of Ω or less is used to prevent parasitic vibration, but if the rectified output (2) is too large, a resistor value necessary for adjusting the input level may be adopted. When Ql is off, noise -f flows from the power supply Vcc through the resistor FL5.
A conductive current flows through the Dart Da (10) iode in the -) section as shown by the broken arrow. (
The noise/dirt section in the figure is shown in principle with the simplest configuration.) When a noise pulse is input to Q2 and Qx becomes conductive, the voltage drop caused by resistor R11 causes the collector potential to drop as shown in ■.During that period, the dart diode becomes non-conductive and acts as a noise dart. There is. In the present invention, when utilizing the voltage change (2) for noise noise AGC, a diode D! is connected between the collectors of Ql and Q3.
The feature is that it is configured to connect with. D! The voltage change on the Ql side is applied to the Ql side, but the polarity is such that the voltage change on the Ql side does not affect the Q3 side, and the potential difference between the two circuits V
To keep D reasonable, a Zener diode, diode forward voltage drop, and the like are used in series. As a result of the AGC voltage O synthesized in this way being applied to the noise amplification stage, the input pulses with large amplitudes as shown in the top row of Figure 6 are also suppressed and are made uniform as shown in ■. . In Figure 5, QtsQs is originally a circuit required for each application, and by simply adding D8 to it, not only can the desired AGC operation be obtained, but also the AGC
There is an advantage that there is no need to consider mutual interference in a configuration in which (1) and AGC (2) are added separately to the noise amplification stage.

本発明の特許請求の範囲第3項には本発明の実施上で有
効なAGC回路の別の構成例を提示している。すなわち
、第7図においてノイズ増幅段の整流出力■を抵抗R1
と容量Cとよ勺なる積分形時定数回路を通してAGC)
ランジスタQ1のペースに加え、そのコレクタ電位の変
化をノイズ増幅段のAGCとして供給する構成の第1の
AGC増幅器Q1の積分形時定数回路の時定数抵抗R1
と並列にダイオ−PDlを接続することにより、入力信
号の振幅よう該ダイオードの初期導通電圧以上の振幅の
大きいノイズ・パルスで動作する第2のAGCとして共
用し得る構成のノイズ・ブランカ回路である。
Claim 3 of the present invention presents another configuration example of the AGC circuit that is effective in implementing the present invention. That is, in Fig. 7, the rectified output ■ of the noise amplification stage is connected to the resistor R1.
AGC through an integral type time constant circuit with a large capacity C)
The time constant resistor R1 of the integral time constant circuit of the first AGC amplifier Q1 is configured to supply the pace of the transistor Q1 as well as the change in its collector potential as the AGC of the noise amplification stage.
By connecting a diode PDl in parallel with the input signal, this noise blanker circuit can be used as a second AGC that operates with a noise pulse having a large amplitude equal to or higher than the initial conduction voltage of the diode. .

入力側に抵抗R1と容量Cとより成る積分形時定数回路
を備えた第1のAGCの動作については、前記特許請求
の範囲第2項の説明で詳述した通シである。本発明では
その時定数抵抗R1と並列にダイオードD3を接続する
という簡単な構成にょJ)、AGC増幅器Q1のコレク
タに信号の平均値で動作する第1のAGC(1)と信号
よ多振幅の大きいノイズ・パルスのみで動作する第2の
AGC(2)の合成のAGC,電圧を得ることができる
ものである。
The operation of the first AGC, which has an integral time constant circuit including a resistor R1 and a capacitor C on the input side, is as described in detail in the second claim. In the present invention, the simple configuration is that the diode D3 is connected in parallel with the time constant resistor R1 (J), and the collector of the AGC amplifier Q1 is connected to the first AGC (1) that operates with the average value of the signal and the signal that has a large amplitude. It is possible to obtain a composite AGC and voltage of the second AGC (2) that operates only with noise pulses.

ここに使用するD3は通常の小信号ダイオードでよく、
周知のようにシリコン・ダイオードでは順方向抵抗は極
めて小さいが、初期導通電圧(o、6Vぐらい)以下で
はほとんど導通しない(極めて高抵抗と等価)のである
から、ピーク0.6 V以下の小振幅入力に対してはD
3の無い回路と考えてよい。従ってAGC(1)が十分
に効いて信号の整流出力をQlの初期バイアス0.6V
とを考えた1、2v以下に抑圧しておけばAGCQ)の
ための動作は通常に行われる。ノイズ・i4ルスのよう
な大振幅入力はD3を通過してQsのベースに加わるが
、Cの容量が大きい状態では波形の立上シが遅れるので
、Cと直列に若干の抵抗Rを入れることがある。この場
合のRの値は時定数に大きく影響しなh範囲(13) で、R1の1/10内外に選ぶことが多い。このような
回路構成においてQlの動作は第8図のようにQlのコ
レクタ電位がAGC電圧■となることから、他には何等
の変更・加工を要することなくノイズ増幅段における大
振幅ノ4ルスの抑圧の目的を達することができるもので
ある。なお第7図においてQlはノイズ・ff−)の制
御に専用されるので、r−)制御回路の構成の自由度が
大きい利益がある。
D3 used here can be an ordinary small signal diode,
As is well known, silicon diodes have extremely low forward resistance, but they hardly conduct (equivalent to extremely high resistance) below the initial conduction voltage (o, about 6 V), so a small amplitude of 0.6 V or less peaks. D for input
You can think of it as a circuit without 3. Therefore, AGC (1) is sufficiently effective and the rectified output of the signal is adjusted to the initial bias of Ql of 0.6V.
If the voltage is suppressed to 1 or 2 V or less, the operation for AGCQ) will be performed normally. Large amplitude inputs such as noise and i4 pulses pass through D3 and are added to the base of Qs, but if the capacitance of C is large, the rise of the waveform will be delayed, so insert a small resistor R in series with C. There is. In this case, the value of R is within the h range (13) that does not significantly affect the time constant, and is often selected within 1/10 or less of R1. In such a circuit configuration, the operation of Ql is such that the collector potential of Ql becomes the AGC voltage ■ as shown in Figure 8, so the large-amplitude noise in the noise amplification stage can be easily detected without any other changes or processing. The goal of oppression can be achieved. Note that in FIG. 7, Ql is dedicated to controlling noise/ff-), so there is an advantage that there is a large degree of freedom in the configuration of the r-) control circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は無線受信機におけるノイズ・ブランカの解説図
、第2図はノイズ・ブランカ回路の構成例のブロック図
、第3図は本発明のノイズ・ブランカ回路の構成を示す
ブロック図、第4図は第2図および第3図回路各部の動
作波形図、第5図は本発明に適用するAGC回路の実施
例、第6図は第5図回路各部の動作波形、第7図は本発
明に適用する他のAGC回路の実施例、第8図は第7図
回路各部の動作波形である・ 1・3・・・IFフィルタ、2・・・ノイズ・ゲート、
(14) 5A・5B・・・ノイズ増幅段、6・・・整流器、7・
9・・・AGC増幅器、8A・8B・・・ケ9−ト制御
部、C・・・容量、D−Dl −D鵞 ・D3・・・ダ
イオード、R・R1・R2@R3°R4@R5°°°抵
抗1Q1 @Q2・・・トランジスタ。 特許出願人 八重洲無線株式会社 (15) 第 1 図 第 2 図 ■■ @ 0 ■@○ 手続補正書(方式) %式% ) 1、事件の表示 昭和58年特許願第170867号 2、発明の名称 ノイズ・ブランカ回路 3、補正をする者 連絡先 電話 03−759−71114、補正命令の
日付 第 7 図 Iイス゛整流部 、717 よ 乙;)
Fig. 1 is an explanatory diagram of a noise blanker in a radio receiver, Fig. 2 is a block diagram of a configuration example of a noise blanker circuit, Fig. 3 is a block diagram showing the configuration of a noise blanker circuit of the present invention, and Fig. 4 The figures are operation waveform diagrams of each part of the circuit in Figures 2 and 3, Figure 5 is an example of an AGC circuit applied to the present invention, Figure 6 is an operation waveform of each part of the circuit in Figure 5, and Figure 7 is a diagram of the present invention. Another example of an AGC circuit applied to the circuit, Fig. 8 shows the operating waveforms of each part of the circuit shown in Fig. 7. 1, 3... IF filter, 2... Noise gate,
(14) 5A/5B... Noise amplification stage, 6... Rectifier, 7...
9... AGC amplifier, 8A/8B... Gate control section, C... Capacitance, D-Dl -D ・D3... Diode, R・R1・R2@R3°R4@R5 °°°Resistance 1Q1 @Q2...Transistor. Patent applicant Yaesu Musen Co., Ltd. (15) Figure 1 Figure 2 ■■ @ 0 ■@○ Procedural amendment (method) % formula % ) 1. Indication of the case Patent Application No. 170867 of 1982 2. Invention Name: Noise blanker circuit 3, Contact number of person making the correction: Telephone: 03-759-71114, Date of correction order: 7 Figure I, Rectifier section, 717 Yotsu;)

Claims (3)

【特許請求の範囲】[Claims] (1) 無線受信機の信号通過段に設けたノイズ・ダー
トを制御して受信信号に混在するパルス性ノイズを除去
すべくしたノイズ・ブランカ回路のノイズ増幅段に信号
分出力を一定とする形式のAGCを掛けることによフノ
イズ・ノ母ルスを分離してノイズ・ダート制御をする回
路において、前記信号分出力を一定とする形式の第1の
AGCの他に、設定値以上の振幅のノイズ・・ノヤルス
の出力を低減する形式の第2のAGCを設けることによ
り、ノイズ増幅段の大振幅のノイズ・t4ルスがノイズ
・ゲート以後の信号回路に回シ込むことを軽減するよう
にしたことを特徴とするノイズ・ブランカ回路。
(1) A form in which the signal output is kept constant at the noise amplification stage of a noise blanker circuit that controls the noise dirt provided in the signal passing stage of a radio receiver and removes pulse noise mixed in the received signal. In a circuit that performs noise/dirt control by separating noise and normal pulses by multiplying them by AGC, in addition to the first AGC that keeps the output of the signal constant, noise with an amplitude greater than a set value By providing a second AGC that reduces the output of Noyalus, it is possible to reduce the large amplitude noise/t4us from the noise amplification stage from entering the signal circuit after the noise gate. A noise blanker circuit featuring:
(2) 前記のノイズ増幅段の整流出力を積分形時定数
回路を通してAGC増幅トランジスタのペースに加え、
そのコレクタ電位の変化をノイズ増幅段のAGCとして
供給する構成と、エミッタにダイオードを直列接続した
r−)制御トランジスタのペースにノイズ増幅段の整流
出力を加え、そのコレクタと前記AGC増幅トランジス
タのコレクタとの間をダイオードで連結する構成とする
ことにより、ゲート制御ノ4ルスの発生時に、AGC増
幅トランジスタのコレクタに信号ノイズ・パルスの双方
に動作するAGC制御電圧を得ることを特徴とする特許
請求の範囲第1項記載のノイズ・ブランカ回路。
(2) Adding the rectified output of the noise amplification stage to the pace of the AGC amplification transistor through an integral time constant circuit,
The configuration is such that the change in the collector potential is supplied as the AGC of the noise amplification stage, and the rectified output of the noise amplification stage is added to the pace of the r-) control transistor whose emitter is connected in series with a diode, and the collector of that collector and the collector of the AGC amplification transistor are connected. A patent claim characterized in that an AGC control voltage that operates on both signal noise and pulse is obtained at the collector of the AGC amplification transistor when a gate control noise occurs by connecting the two with a diode. The noise blanker circuit described in item 1.
(3) 前記のノイズ増幅段の整流出力を積分形時定数
回路を通してAGC増幅トランジスタのペースに加え、
そのコレクタ電位の変化をノイズ増幅段のAGCとして
供給する構成の第1のAGC増幅器の積分形時定数回路
の時定数抵抗と並列にダイオードを接続することによ)
、入力信号の振幅よシ該ダイオードの初期導通電圧以上
の振幅の大きいノイズ・ノ4ルスで動作する第2のAG
Cとして共用し得る構成の、特許請求の範囲第1項記載
のノイズ・ブランカ回路。
(3) Adding the rectified output of the noise amplification stage to the pace of the AGC amplification transistor through an integral time constant circuit,
By connecting a diode in parallel with the time constant resistor of the integral time constant circuit of the first AGC amplifier configured to supply the change in collector potential as the AGC of the noise amplification stage)
, the second AG operates with a noise noise whose amplitude is greater than the initial conduction voltage of the diode than the amplitude of the input signal.
2. The noise blanker circuit according to claim 1, having a configuration that can be shared as a noise blanker circuit.
JP17086783A 1983-09-16 1983-09-16 Noise blanker circuit Granted JPS6062712A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17086783A JPS6062712A (en) 1983-09-16 1983-09-16 Noise blanker circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17086783A JPS6062712A (en) 1983-09-16 1983-09-16 Noise blanker circuit

Publications (2)

Publication Number Publication Date
JPS6062712A true JPS6062712A (en) 1985-04-10
JPH0152943B2 JPH0152943B2 (en) 1989-11-10

Family

ID=15912780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17086783A Granted JPS6062712A (en) 1983-09-16 1983-09-16 Noise blanker circuit

Country Status (1)

Country Link
JP (1) JPS6062712A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007028290A (en) * 2005-07-19 2007-02-01 Sanyo Electric Co Ltd Am radio receiving circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007028290A (en) * 2005-07-19 2007-02-01 Sanyo Electric Co Ltd Am radio receiving circuit

Also Published As

Publication number Publication date
JPH0152943B2 (en) 1989-11-10

Similar Documents

Publication Publication Date Title
CA1176336A (en) Noise blanker which tracks average noise level
US6838862B2 (en) Pulse width modulator having reduced signal distortion at low duty cycles
EP0066110A2 (en) Noise removing apparatus in an FM receiver
JP4092206B2 (en) FET band amplifier
US4975953A (en) Combined deemphasis circuit and noise blanker
JPS61157033A (en) Wireless receiver
JPH0248830A (en) Pulse noise suppression device for fm receiver
JPH0787387B2 (en) Wireless receiver
JPS6062712A (en) Noise blanker circuit
US5414313A (en) Dual-mode logarithmic amplifier having cascaded stages
US10574212B2 (en) Method and circuit for low-noise reference signal generation
US4278901A (en) Pulsive component detecting apparatus
EP0067585A2 (en) Noise sensitivity reduction for a TV receiver AGC system
US4271535A (en) Noise eliminating system
US2797258A (en) Sync separator
EP0069843B2 (en) Lf amplifier for a television receiver
US4289981A (en) Pulsive component detecting apparatus
JPS6224979Y2 (en)
US5664022A (en) Noise gate control circuitry for electronic systems
JP3213495B2 (en) Noise removal circuit
RU2246173C2 (en) Broadband amplifier
GB2113047A (en) Noise blanking in a radio receiver
JPH0352695B2 (en)
JPH0648994Y2 (en) Noise blanker circuit
JPH0737381Y2 (en) Radio receiver S-meter circuit