JPS6061959A - Clock synchronizing circuit of multi-track type magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To ensure the easy control of a clock synchronizing circuit by using a voltage controlled oscillator needing control only to a clock synchronizing circuit for >=2 selected tracks, and using a phase locked loop composed of a phase comparator and a phase control circuit to a clock synchronizing circuit of non- selected track. CONSTITUTION:The output of an equalizer 13-2 is applied to a phase comparator 51, and the phase of the output of a changeover switch 35 is compared with the phase of a signal obtained through a delay circuit 52, NAND gate circuits 53 and 54, exclusive OR circuit 55 and a 1/M divider 56. When an output 57 outputs a pulse of ''1'', the circuit 54 opens to supply the output of the circuit 52 to the circuit 55. Thus the number of pulses supplied to the circuit 56 is increased by one. The divider 56 consists of a counter and receives pulses with extra one. Therefore, the output of the divider 56 advances in phase. When an output 58 outputs a pulse of ''1'', both circuits 53 and 54 are closed. Thus the pulses applied to the divider 56 are decreased by one. In such a way, the output of the divider 56 is delayed in phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a lock synchronization circuit necessary for recording and reproducing digital signals in a multi-track magnetic recording and reproducing apparatus using a magnetic tape as a medium.

[Technical background of the invention and its problems]

Conventionally, a demodulation circuit in a multi-track digital magnetic recording device using magnetic tape as a recording medium includes a preamplifier 2 equalizer identification circuit for each track.

It has a clock synchronization circuit and is demodulated into a digital signal, which is then converted from parallel to serial at the digital signal stage.

FIG. 1 is a block diagram schematically showing the reproduction side of a conventional N-track digital magnetic recording device. playback head 11
The signals regenerated by -1 to 11-N are sent to the preamplifier 1
After being amplified by 2-1 to 12-N, equalizers 13-1 to 1
The frequency characteristics and phase characteristics of the recording/reproducing system are equalized at 4-N and identified by identification circuits 14-1 to 14-N. The lock required for the identification circuit is provided by the clock synchronization circuits 15-1 to 15.
-N provides phase synchronization with data.

The identified data is decoded by decoders 16-1 to 16-N frame synchronization circuits 17-1 to 17-N,
After time axis jitter is compensated for by the buffer memories 18-1 to 18-N, the parallel data of each track is converted into serial data by the parallel-to-serial converter 19 and output to the signal processing circuit. The clock synchronization circuits 15-1 to 15-N in the block diagram of FIG. 1 constitute a phase synchronization circuit, and a more detailed block diagram of the clock synchronization circuit 15-1 is shown in FIG. That is, the output of the equalizer 13-1 is input to the phase comparator 21-1, and the output of the voltage controlled oscillator 2
2-1 and the phase error output of the phase comparator 21-1 is input to the control terminal of the voltage controlled oscillator 22-1 via the loop filter 23-1, thereby forming a phase locked loop. . Then, the phase-synchronized output of the voltage controlled oscillator 22-1 is input to the identification circuit 14-1, and the output signal of the equalizer 13-1 is identified.

In the demodulation circuit of the multi-track digital magnetic recording and reproducing device configured in this way, one clock synchronization circuit is required for each track, but the voltage controlled oscillators 22-1 to 22-N constituting the clock synchronization circuit are The center frequency varied greatly between tracks and needed to be adjusted. For example, the number of tracks N is often set to about 16 in the case of a PCM recorder using a compact cassette, which has the disadvantage that N becomes large and adjustment is extremely difficult with conventional clock synchronization circuits. Ta.

[Purpose of the invention]

The present invention has been made in consideration of these circumstances, and its object is to provide a clock synchronization circuit for a multi-track digital magnetic recording/reproducing device that is easy to adjust.

[Summary of the invention]

The present invention selects 2 to N/4 non-adjacent tracks from N tracks, and for the selected tracks, increases the oscillation center frequency of the voltage controlled oscillator of the clock synchronization circuit by M times, which is more than 10 times the conventional frequency. This frequency is divided by 17/M and phase comparison is performed to construct a phase-locked loop, and a voltage that is phase-locked to the frequency M times that of the one track that has not caused a dropout among the selected tracks mentioned above. A phase control circuit including a 1/M splitter is constructed using the output of the controlled oscillator, and clock synchronization is performed for tracks other than the selected track using a phase locked loop consisting of a phase comparator and a phase control circuit. This is how it was done.

〔Effect of the invention〕

In this way, according to the present invention, voltage controlled oscillators that require adjustment are used only in the clock synchronization circuits of 2 to N/4 tracks selected among the N tracks, and the clock synchronization circuits of the remaining tracks that are not selected are used. By using a phase-locked loop consisting of a phase comparator and a phase control circuit, the clock synchronous circuit can reduce the number of adjustment points, making it very easy to adjust the clock synchronous circuit when applied to a multi-channel digital magnetic recording/reproducing device. It has the advantage of becoming

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a schematic block diagram on the reproduction side of a multi-track type digital magnetic recording and reproducing apparatus constructed by applying the clock synchronization circuit of the present invention. 33-(J-1), 33-(J
+1) to 33-N clock synchronization circuits, 34 dropout detection circuits, and 35 changeover switches have the same configuration as the schematic block diagram of FIG. 1 of the conventional example, so they are given the same numbers as in FIG. 1 and explained. omitted. In FIG. 3, as an example, the selected tracks are non-adjacent tracks 1 and J (JN2
) as a truck. The clock synchronization circuits 31 and 32 of the selected first and first tracks have the same configuration, and the detailed block diagram of the clock synchronization circuit 31 of the first track is shown in the fourth track.
As shown in the figure. The difference from the conventional four-wheel synchronous circuit shown in Fig. 2 is that the oscillation center frequency of the voltage controlled oscillator is 1.
The difference is that the signal is multiplied by M, which is 0 times or more, and the phase comparison is performed through a 1/'M splitter. The clock synchronization circuit shown in FIG.
The phase is compared with the frequency divided by /'M, and the voltage controlled oscillator 42 is controlled via the loop filter 44 to form a phase locked loop. Therefore, the output of the voltage controlled oscillator 42 is phase-locked to a frequency M times the clock frequency of the data input from the equalizer 13-1. The output of the frequency divider 43 is applied to the identification circuit 14-1, and the output of the voltage controlled oscillator 42 is applied to the changeover switch 35. The dropout detection circuit 34 detects a dropout from the signals of the first and J-th tracks and adjusts the clock frequency M from the clock synchronization circuits 31 and 32.
The changeover switch 35 selects the signal of the track with no dropout among the two signals of double the frequency. Therefore, the phase is always synchronized to M times the clock frequency of the first track or the J-th track, except when the first and J-th tracks are simultaneously experiencing dropout. The output selected by the changeover switch 35 is supplied to the clock synchronization circuits of all tracks except the first track and the J-th track. Clock synchronization circuits 33-2 to 33- (J-1),
33-(J+1) to 33-N are all circuits with the same configuration, and a detailed block diagram of the clock synchronization circuit 33-2 of the second track is shown in FIG. 5. Simple waveforms for explaining the operation of FIG. 5 are shown below. A diagram is shown in FIG. The output of the equalizer 13-2 is applied to the phase comparator 51, and the output of the changeover switch 35 is applied to the delay circuit 52, NAND gate circuit 53, 54, Exc
The phase is compared with the signal passed through the frequency divider 56 of the lusive OR circuit 55.1/M. As a result of the box comparison, the branch unit 5
If the phase of the output of the phase comparator 51 is delayed, if it is advanced to the output terminal 57, a pulse of logic "1#" is outputted to the output terminal 58.The output 57 of the phase comparator 51 is sent to the NAND gate 54, The signal is applied to the NAND gate 53 via an inverter 59.The delay circuit 52 is a circuit that delays the output of the changeover switch 35, which is M times the target frequency, by a phase of about π/2. In the circuit configured in this way, the delay circuit 52, the NAND gate circuit 53, 54, the exclusive OR circuit 55.1/M frequency divider 56, and the inverter 59 are connected to the output 57 of the phase comparator 51.
．． 58 as a control input, the circuit of FIG. 5 becomes a type of phase-locked loop that controls only the phase. The operation of the variable phase shifter will be briefly explained with reference to the waveform diagram in FIG. FIG. 6(a) shows the changeover switch 35
The input signal (b) from the delay circuit 52 is the output tel of the phase comparator 51, and the input signal (d) is the output 58 of the phase comparator 51. When the outputs 57 and 58 are "0", the NAND gate circuit 53 is open and the NAND gate circuit 54 is closed, so the input shown in FIG. Since the frequency is divided and output, the phase remains unchanged. When the output 57 outputs a "L" pulse as shown in FIG. 6(e), the NAND gate circuit 54 opens and the output (b) of the delay circuit 52 becomes Exclus iv OR.
There is one more pulse applied to circuit 55 and to divider 56. Since the frequency divider 56 is composed of a counter, the phase of the output of the divider 56 is advanced due to the addition of one extra pulse. Also, Figure 6 (
When the output 58 outputs a pulse of 11'' as in dJ, the NAND gate circuits 53 and 54 are both closed, and the number of pulses applied to the divider 56 is reduced by one. The phase of the output will be delayed. FIG. 6(e) shows the input of the frequency divider 56 at this time. By controlling the output phase of the frequency divider 56 by the output of the phase comparator 51 in this way, A phase-locked loop is often constructed.The four-track synchronized circuit in Figure 5 is phase-locked using a signal with a frequency M times higher than that of the clock synchronized circuit of the J-th track of the first straddle, which is synchronized in frequency. Since there is no need for a voltage controlled oscillator, there is no need to adjust the frequency.

As explained above, in the clock synchronization circuit of FIG. 3 according to the present invention, it is only necessary to adjust the oscillation frequency of the voltage controlled oscillator of the clock synchronization circuits 31 and 32, and the clock synchronization circuits of other tracks do not require adjustment. In other words, the conventional clock synchronization circuit shown in FIG. 1 requires adjustment at N locations, which is difficult, but the clock synchronization circuit according to the present invention, shown in FIG. 3, requires only two adjustments, which is extremely easy. Particularly in a multi-track magnetic recording/reproducing device having a large number of tracks N, the conventional method requires a great deal of effort and difficulty in adjustment, but the example shown in FIG. 3 according to the present invention allows for very easy adjustment.

Similarly, the present invention is not limited to the above embodiments. For example, a clock synchronization circuit using a voltage controlled oscillator is used as the first track and the first track, but the selected tracks may be arbitrarily selected from several non-adjacent tracks, and the configuration of the variable phase shifter is as shown in Fig. 5. However, various other configurations of the variable phase shifter are also possible. In short, the present invention can be implemented with various modifications without departing from its gist.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of the reproduction side of a conventional multi-track magnetic recording and reproducing device, FIG. 2 is a detailed block diagram of the clock synchronization circuit of FIG. 1, and FIG. 3 is a multi-track diagram of an embodiment of the present invention. 4 and 5 are detailed block diagrams of the clock synchronization circuit shown in FIG. 3, and FIG. 6 is a waveform diagram for explaining the operation of FIG. 5. . 1l-1-11-N...Reproduction head, 12-1 to 12
-N... Preamplifier, 13-1 to 13-N... Equal volume, 14-1 to 14-N... Identification circuit, 15-1 to 1
5-N... Clock synchronization circuit, 16-1 to 16-N.
...Decoder, 17-1 to 17-N...Frame synchronization circuit, 18-1 to 18-N...Buffer memory, 19
... Parallel-serial converter, 21-1 ... Phase comparator, 22-1 ... Voltage controlled oscillator, 31.32.
... Clock synchronization circuit, 43... Branch.

Claims (1)

[Claims] In a multi-track magnetic recording/reproducing device having N tracks, 2 to N/N tracks that are not adjacent from among the N tracks
Four tracks are arbitrarily selected, and the clock synchronization circuit of the selected track constitutes a phase synchronization circuit using a voltage controlled oscillator having a center frequency at least 10 times the recorded digital data p-track frequency. Also, means for extracting the voltage controlled oscillator output of a track that has not dropped out among the selected tracks;
Clock synchronization is performed for tracks other than the selected track by using the output of the voltage-controlled oscillator as input, and using a controllable variable phase shifter including a frequency divider and a phase comparator to constitute a phase synchronization circuit. A clock synchronization circuit for a multi-track magnetic recording device, characterized in that: