JPS6061855U

JPS6061855U - FM/AM receiver

Info

Publication number: JPS6061855U
Application number: JP15279683U
Authority: JP
Inventors: 今川　敏幸
Original assignee: クラリオン株式会社
Priority date: 1983-09-30
Filing date: 1983-09-30
Publication date: 1985-04-30

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図および第２図は従来および本考案実施例を示す一
部に回路図を含むブロック図、第３図乃至第６図はいず
れも本考案を説明するための特性図である。１・・・ＦＭチューナ回路、２・・・ＡＭチューナ回路
、４・・・ＦＭ用中間周波増幅段および検波段、８・・
・ＡＭ用中間周波増幅段および検波段、６・・・ＦＭマ
ルチプレックス復調回路、Ｑ・・・トランジスタ、Ｄ、
〜Ｄ６・・・ダイオード、Ｒ１−Ｒ１５・・・抵抗、Ｃ
１〜ＣＩＯ・・・コンデンサ、ｖＲ・・・ボリュウム、
ＳＷ・・・切換スイッチ、Ｘ１〜ｘ８・・・出力点。第４図１ンデｊ）くな（ｄＢｌｌ　）第６図FIGS. 1 and 2 are block diagrams, some of which include circuit diagrams, showing conventional and embodiments of the present invention, and FIGS. 3 to 6 are characteristic diagrams for explaining the present invention. 1... FM tuner circuit, 2... AM tuner circuit, 4... FM intermediate frequency amplification stage and detection stage, 8...
・AM intermediate frequency amplification stage and detection stage, 6...FM multiplex demodulation circuit, Q...transistor, D,
~D6...Diode, R1-R15...Resistance, C
1~CIO...capacitor, vR...volume,
SW...Choice switch, X1 to x8...Output point. Fig. 4 1nd j) Kuna (dBll) Fig. 6

Claims

[Claims for Utility Model Registration] I In a receiver equipped with an FM multiplex demodulation circuit, a control signal corresponding to the input signal level from each of the FM tuner circuit and the AM tuner circuit is transmitted to the high cut control terminal of the FM multiplex demodulation circuit. An FM/AM receiver characterized in that, in addition to the above, the high frequency signal is controlled according to the input signal level. 2. The FM/AM receiver according to claim 1, wherein a control signal corresponding to the input signal level is applied to the high-cut control terminal of the FM multiplex demodulation circuit through each diode. .