JPS6059650U - wireless selective calling receiver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a radio selective calling receiver according to an embodiment of the present invention, FIG. 2 is a diagram showing the structure of a signal received and demodulated by the receiver of FIG. 1, and FIG. 1. FIG. 4 is a flowchart showing the operation of the decoder 40 in FIG. A block diagram showing the configuration of the message data processing unit 60, FIG. 6 is 1 in FIG.
A block diagram showing the configuration of chip CPU 1 GG,
FIG. 7 shows the configuration of the LCD driver 200 in FIG.
8 is a block diagram showing the configuration of the RAM 300 in FIG. 2, FIG. 9 is a circuit diagram showing the frame synchronization signal/stop signal detection circuit in the decoder 40 in FIG. 1, and FIG. 10 is a block diagram showing the configuration of the RAM 300 in FIG. is a circuit diagram showing the selective call signal detection circuit in the decoder 40 of FIG. 1, FIG. 11 is a circuit diagram showing the configuration of the buffer 70 and call display means 80 of FIG.
FIG. 2 shows an example of the symbol structure and display of the display 90 in FIG. 1. FIG. DESCRIPTION OF SYMBOLS 10... Antenna, 20... Radio part, 30... Waveform shaping circuit, 40... Address decoder, 50...
P-ROM, 60...Message data processing section, 61
...Diode, 62...Capacitor, 70...
Buffer, 80...first display means, 90...second
display means, 100...1 chip CPU,
101...Crystal, 101-106...Input port, 107...Interrupt □Interrupt port, 108...
Serial interface, 111-117... Output port, 120... Bus, 130... Program counter, 140... Program memory, 150... A
LU, 160... Instruction decoder, 17
0...ACC, 180...RAM, 190...System clock generation circuit, 200...LCD driver, 210...Column driver, 220...Row driver, 230...LCD voltage control controller , 24
0...LCD timing controller, 250...
Data memory, 260... System clock controller, 270... Command decoder, 280... Data pointer, 290... Character generation circuit, 29
5...Serial interface, 300...RAM
, 310... serial interface, 320...
Address counter, 330...X-Y decoder, 34
0...Memory, memory array, 350...Control circuit, 50
0:...Shift register, 510,520.530...
・Inverter, 540...And gate, 600...
・Counter, 61 G-EXCLUSIVENOR circuit, 710 and 720...Resistor, 730...NPN transistor, 740...PNP transistor, 800
...Alarm horn, 1000...Battery, SO, S
l, S2. S3...operation switch. Figure 8, Jo. −−+−+$+1

Claims (1)

[Claims for Utility Model Registration] 1. A radio selective calling receiver that receives a selective calling number and message information, including at least a first means for decoding the message information, and a first means connected to the first means, a second means for storing the message information decoded by the first means; and a third means connected to the second means and including at least an element having capacitor characteristics, for backing up the second means when the power is cut off. A wireless selective calling receiver comprising means for and. 2. Utility Model Registration In the radio selective calling receiver as set forth in claim 1, the first means has a fourth means for storing management information corresponding to each message information, and the first means has a fourth means for storing management information corresponding to each message information, and A radio selective calling receiver capable of saving the stored contents of the fourth means to the second means.