JPS6053977B2 - Frequency shift demodulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulated data discrimination method in an FSK demodulation circuit using a DPLL circuit or a monostable multivibrator.

A conventional circuit of this type is shown in FIG.

In the figure, 1 is the FSK reception power, 2 is the line transformer and reception filter, 3 is the N°C circuit, 4 is the beam transmitter, 5 is the DPLL (or monostable multivibrator), 6 is the baseband low-pass filter, and 7 is the threshold. In the judgment circuit, 8 is a demodulated data signal, 9 is a beam transmitter output signal, 10 is a DPLL output signal, and 11 is a baseband signal. Next, the operation will be explained.

FSK receiver power 1 is line transformer and reception filter 2
The signal is impedance matched and band limited, and after being adjusted to a constant amplitude by the M°C circuit 3, the waveform is shaped by the emitter 4 into a rectangular wave having a conversion point at the zero crossing point. The limiter output 9 is input to the DPLL circuit 5 and the input frequency is fHb-
- DPL with impact coefficient dH or dL depending on fL
It is converted into an L output signal 10. High frequency components of this output are cut off by a baseband low-pass filter 6, resulting in a baseband signal 11, which is sliced at a certain threshold to obtain a demodulated data signal 8. Since the conventional FSK demodulation circuit is configured as described above, the baseband low-pass filter 6 must be a high-grade filter with excellent cutoff characteristics, and the threshold value determination circuit 7 must be designed to be sensitive to temperature and power supply fluctuations.
The disadvantages were that it was unstable and required adjustment due to drift. The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and the ever-changing impact coefficient of the DPLL output signal 10 is calculated by counting the output signal using a high-speed samp pull counting circuit. It is an object of the present invention to provide a circuit that can digitally determine a demodulated data signal by calculating a value for one cycle for each falling edge, storing this as an instantaneous impact coefficient, and linearly interpolating the contents. It is said that

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, 12 is a digital determination circuit that determines the impulse coefficient of the pulse of the DPLL output signal 10 by high-speed sampling and pulse counting;
Since the output of the digital judgment circuit 12 is different from the DPL
A conversion circuit for converting the pulse repetition period of the L output signal 10 into a DC component; 14 is a digital determination circuit 12;
is the output signal of In FIG. 3, 15 is a differentiation circuit that generates output pulses 16a and 16b at the rise and fall of the DPLL output signal 10, respectively, 17a and 17b are both fixed time delay circuits, and 18a and 18b are two N-bit reversible The counters 19a and 19b count up when the reversible counters 18a and 18b are ゛゜1゛, respectively.
20 is a high speed clock pulse, 21a, 22a, 23a, 21b,
22b, 23b are N4 circuits, 24a, 24b, 24c are 0R circuits, 25 is a register that alternately stores the contents of reversible counters 18a and 18b, 14a, 14b, 14c
is the output signal of the N-bit register 25. In FIG. 4, 26 is a ROM including a decoder that multiplies the N-1 bit binary input excluding the sign bit 14a by the value of FL/FH. 27a and 27c are AND circuits, and 28 is a NOT circuit.
The circuits 29b and 29c are AND circuits, and 30b and 30c are 0R circuits. In FIG. 5, 31 is an N-bit comparison circuit, 32 is an M-bit counter, where M>N, and 33 is the output of the comparison circuit, which decreases when the content of the counter 32 is large compared to the content of inputs 11a, 11b, and 11c. The counter 32 is controlled to increase the count when the count is small. 34 is a count pulse.

In FIG. 6, 35, 36, 37, 40, 41, and 42 are the output waveforms of 1, 9, 10, 14, 11, and 8, respectively, and 3
8 and 39 are time charts showing waveforms obtained by analog conversion of the contents of 18a and 18b, respectively. Ru. Next, the operation will be explained.

The reversible counter 18a counts the clock pulse 22 up when the DPLL output signal 10 is ゜゜1゛, and counts down when the DPLL output signal 10 is ``0''.Furthermore, the rising signal pulse 16a is passed through the delay circuit 17a every time the DPLL output signal 10 rises. Since it is reset by the passed pulse, the reversible counter 18a is DP
A value corresponding to the instantaneous impact coefficient is counted for each pulse cycle of the LL output signal 10. Reversible counter 18b
The same operation is performed with a shift of half a cycle from the above operation. As a result, a value corresponding to the instantaneous impact coefficient for one cycle is held in the register 25 every half cycle. Now, when the pulse repetition period of the DPLL output signal 10 is F, the content of the reversible counter 18a or 18b after l cycles is M, the impact coefficient is D, the count pulse frequency is FO, and the output DC component is e. BJ! It is.

Here, assuming that FO is constant, it can be seen that even if the impact coefficient d is the same, the value of m varies depending on the value of f, and Mf is proportional to d. Therefore, the value of d can be found by dividing the value of m by t=11f. This operation is executed by the ROM 26 including the decoder. In the figure, since it is only necessary to perform this conversion on either FL or FH, the need for conversion is determined by the sign bit. Note that this correction multiplier is FL. Since it is determined by the ratio of l5fH and only the amplitude axis direction is corrected, if this term does not have a large effect on code distortion, code errors, etc., converter circuit 1
You can omit step 3. D converted as above
The DC component 11 of the PLL output signal 10 is linearly interpolated as shown in FIG. 6 by comparing the magnitude of the DC component 11 with the counter 32 that counts the count pulses 34 in the determination circuit 7.

That is, when the contents of the DC component 11 and the counter 32 are different, the control is controlled to increase or decrease until they match, and a certain threshold value is detected to obtain the demodulated data 8. In the above embodiment, two reversible counters 18a and 18b are provided, but it is also possible to use only one counter.

Further, although the conversion circuit 13 is provided, it may be omitted depending on the values of FL and fH. Further, although the determination circuit 7 has been described as having no hysteresis, it will be even more effective if it is a determination circuit with hysteresis. As described above, according to the present invention, since the impact coefficient of the DPLL output signal is determined digitally, it is possible to completely digitalize the signal, and it is possible to perform forced adjustment without temperature drift. This has the effect of providing excellent properties.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional FSK demodulation circuit;
FIG. 3 is a block diagram showing an FSK demodulation circuit according to an embodiment of the invention, FIG. 3 is a block diagram showing a digital determination circuit according to an embodiment of the invention, and FIG. 4 is a block diagram showing a conversion circuit according to an embodiment of the invention. FIG. 5 is a block diagram showing a threshold determination circuit according to an embodiment of the present invention, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. In the figure, 10 is a DP ratio output signal, and 8 is a demodulated data signal.

Claims (1)

[Claims] 1 Original data is divided into two different frequencies (f_L and f_H)
In the demodulation circuit, a demodulated data signal is obtained from the output signal of a digital phase-locked loop (DPLL) circuit (or monostable multivibrator) from the zero-crossing waveform of the frequency-shift modulation signal. A demodulated data signal is obtained by instantly calculating the DC component for one cycle and interpolating the output with a straight line with a constant time constant to determine whether the waveform is larger or smaller than a certain threshold. A frequency shift demodulation method characterized by: