JPS6052504B2 - PCM signal transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is used in a device that converts a PCM signal obtained by PCM modulating an audio signal into a signal format similar to a television signal, and records and plays the converted signal using a VTR (video tape recorder). The present invention relates to a suitable PCM signal transmission device.

If the PCM signal has the same signal format as a television signal,
There is an advantage that a television signal recording and reproducing apparatus such as a video desk (VTR) can be directly used as a PCM signal recording and reproducing apparatus.

By the way, in the case of a television signal, a video signal cannot be inserted in the horizontal blanking period that includes the horizontal synchronization signal and the vertical blanking period that includes the vertical synchronization signal, and in the case of the PCM signal, the same lack of data occurs during these blanking periods. It is necessary to set a period. Since the data missing period corresponding to this vertical blanking period is quite long, there is a problem that data cannot be extracted accurately unless the timing of the start of data after this data missing period is accurately detected. Taking this into consideration, the present invention inserts a data synchronization signal in order to detect the timing of the first data after a data missing period. In particular, by making this data synchronization signal a pulse signal of a specific frequency, A data synchronization signal can be easily formed and added, and its separation can be easily performed using a tuning circuit.
Further, in the present invention, even if a data synchronization signal is lost due to dropout or the like in a VTR, an equivalent synchronization pulse corresponding to the data synchronization signal is automatically generated.
Hereinafter, one embodiment of the present invention will be described. FIG. 1 shows its PCM encoder, FIG. 2 shows its PCM decoder, and in FIGS. 1 and 2, 1 indicates a VTR.

This VTR1 supplies a television signal applied from its recording signal input terminal 11 to a pair of rotating magnetic heads via a recording system, and records one field of the television signal on a magnetic tape as an inclined track. Also, VTR
A television signal formed by a signal reproduced from a magnetic tape passing through a reproduction system is taken out from the reproduced signal output terminal 10 of FIG. This VTR1 generally has a wider transmission band than fixed head systems;
A PC whose signal format is the same as that of a TV signal by TRl
This is for recording and reproducing M signals. The PCM encoder and PCM decoder are configured as an adapter for the VTR1, and when this adapter is loaded into the VTR1, a PCM signal recording and reproducing apparatus can be realized. That is, 2L and 2R are terminals to which left and right signals of the stereo audio signal are respectively supplied.

These left and right signals are transmitted through amplifiers 3L and 3R, respectively.
1 low pass filter 4L and 4R1 sampling hold circuit 5L and 5RAD converter. PCM modulation is performed by passing through 6L and 6R. Since the digital outputs of the pigeon converters 6L and 6R are parallel codes, they are converted into a serial format by the parallel-serial converter 7 and supplied to the time axis compression circuit 8. The time axis compression circuit 8 forms a data missing period that roughly corresponds to the vertical blanking period in a television signal, and by making the read clock frequency higher than the write clock frequency of the RAM constituting the time axis compression circuit 8. The time axis can be compressed. In this case, the RAM is controlled so that writing and reading are performed asynchronously. The output of the time axis compression circuit 8 is an error detection code such as C.
The signal is supplied to a CRC encoder 9 for adding an RC code.

The output of the CRC encoder 9 is sent to the data synchronization signal addition circuit 1
0. This data synchronization signal adding circuit 10 adds a data synchronization signal Pd for indicating the first timing after the data missing period. Further, a synchronization signal mixing circuit Jll adds synchronization signals corresponding to the vertical synchronization signal and horizontal synchronization signal in the television signal (these synchronization signals are also referred to as vertical synchronization signal and horizontal synchronization signal). The output of this synchronizing signal mixing circuit 11 is supplied to the recording signal input terminal 11 of the VTR1. Reference numeral 12 indicates a pulse generation circuit on the write side, and reference numeral 13 indicates a pulse generation circuit on the read side. Clock pulses from a reference clock oscillator 14 are supplied to these pulse generation circuits 12 and 13.

From the pulse generation circuit 12, a sampling pulse is sent to the sampling hold circuits 5L and 5R, a clock pulse is sent to the oil converters 6L and 6R, a clock pulse is sent to the parallel-serial converter 7, and a write clock pulse and write control are sent to the time axis compression circuit 8. A pulse is generated.The frequency of the sampling pulse is, for example, 4
4.1 [KHz], one sample value is converted into a one word 26-bit PCM signal by a clock pulse of 1.4112 [MHz], and is stored in the RAM of the time axis compression circuit 8.
written to. Further, from the pulse generation circuit 13, a read clock pulse and a read control pulse are sent to the time axis compression circuit 8, and a control pulse is sent to the CRC encoder 9.
A composite synchronization signal is generated which is supplied to the synchronization signal mixing circuit 11. In the time axis compression circuit 8, the write clock pulse is gated by the write control pulse to write continuous data, and after a slight delay after the start of this write operation, the read control pulse gates the read clock pulse (for example, 1
．． 764 [MHz)) is gated to perform a read operation, and after a predetermined period of time, a read control pulse stops supplying read clock pulses to the RAM, thereby pausing the read operation and restarting it again after a predetermined data missing period. Time base compression is performed as the read operation is started. Reference numeral 15 denotes a data synchronization signal generation circuit, which generates a data synchronization signal Pd at a timing corresponding to a horizontal period before the horizontal period in which data is inserted at the beginning of one field period.

The data synchronization signal Pd is formed from a read clock pulse for the time axis compression circuit 8, and for example, ゜゜1゛ and "゜0゛" are alternately repeated (101010...
)belongs to. The frequency of the data synchronization signal Pd at this time is (1.764 [MHz)) 112 882 [KH]
z]. Data synchronization signal Pd is ゜゜1 d゛ and ゜゜0
0'' is repeated alternately (110011001100
..., and the frequency of the data synchronization signal Pd in this case is 44.1 [KHz]. In order to form such a data synchronization signal Pd, a pulse generation circuit 13
A composite synchronization signal for generating a data synchronization signal from the data synchronization signal at a predetermined timing and a read clock pulse for forming the data synchronization signal itself are supplied to the data synchronization signal generation circuit 15. Figure 3 shows the odd field period (i.e. 263111, where H is the horizontal period) of the PCM signal to be recorded, and the vertical synchronization signal V
The measured vertical blanking period including the Dl equalization pulses EQl and EQ2 and the preceding ? period and thereafter? A data missing period 1RG of 18H in total is provided, and in the remaining 245H period, three words of the PCM signal and a CRC code are inserted every 1H period specified in the horizontal synchronization signal book.

Then, the data synchronization signal Pd is inserted in the 1H period immediately before the even field data starts after the data missing period 1RG. As shown in an enlarged view in FIG. 4, the signals inserted in this 1H period start after the period 1BG that includes the horizontal synchronizing signal HD with a pulse width equivalent to 8 bits and the subsequent backport with a pulse width equivalent to 8 bits. , each word is 26
Three words of a bit code are inserted, followed by a 16-bit CRC code, and the 1H period is equivalent to 112 bits. This one word consists of left and right audio signals of 13 bits arranged in series, and for the sake of simplicity, Fig. 4 shows the case where "゜1゛" and "゜゜0゛" alternate. As shown, the data missing period 1RG has a shift of νH between odd and even fields, similar to the television signal.
Data missing period IRG in odd field is 181
If it is 1, it is 17H in an even field, and the average of both is 17.5H. Next, the demodulation of the reproduced PCM signal appearing at the reproduction output terminal 10 of the VTR1 will be explained with reference to FIG.
A PCM signal having a waveform similar to that shown in FIGS. 4 and 5A and B is supplied to the synchronization signal separation circuit 21.

The vertical synchronization signal D separated by the synchronization signal separation circuit 21 is supplied to a clock pulse generation circuit 33, and data other than the composite synchronization signal is supplied to the data extraction circuit 22 and tuning circuit 34. The output of the data extraction circuit 22 is CR
The signal is supplied to the C decoder 23. CRC decoder 23 is 1
This is to determine whether or not an error has occurred in the information bits for 3 words (total of 78 bits) inserted in the period H, and a 1-bit determination bit, which is the result of this determination, is added to each word. The data is written to the RAM of the time axis expansion circuit 24 in the same format as the original data. The time axis extension circuit 24 extends the time axis to remove the zeta absence period 1RG, and obtains continuous data from which time axis fluctuations have been removed.

In this case, the discrimination bit is read out as the first bit of each word by controlling the read address, and the discrimination bit is separated by the gate circuit 25. Then, by the serial/parallel converter 26, one word of 26 bits is converted into a 13-bit parallel code corresponding to the left signal and a 13-bit parallel code corresponding to the right signal, and these are supplied to the DA converters 27L and 27R, respectively. be done. This DA converter 27
The outputs of L and 27R are sent to average value interpolation circuits 28L and 28R that replace one erroneous word of data with the average value of the correct one word of data before and after it, mutating circuits 29L and 29R, and a low-pass filter 30L. and 3
0R to amplifiers 31L and 31R, respectively. Then, demodulated left and right audio signals appear at output terminals 32L and 32R of amplifiers 31L and 31R.
The clock pulse generation circuit 33 to which the above-mentioned regenerated vertical synchronization signal VD is supplied is configured as a PLL circuit with extremely low cut-off frequency characteristics, and therefore has an extremely low frequency called drift contained in the regenerated signal. For example 0.
For example, 14.1 that follows time axis fluctuations of 3 [Hz] or less.
Generates a 12 [MHz] clock pulse.

This clock pulse may have a constant frequency, but if the drift is also corrected, the capacity of the RAM constituting the time axis expansion circuit 24 becomes large, and even if the demodulated audio signal contains drift, This is done as described above because it does not have a big effect on the auditory sense.
In other words, the clock pulses from the clock pulse generation circuit 33 are supplied to the pulse generation circuit 35 on the read side, and are used as read clock pulses and read control pulses for the time axis expansion circuit 24, clock pulses for the serial/parallel converter 26, and clock pulses for the DA converters 27L and 21R. A clock pulse is formed. On the other hand, the pulse generation circuit 3 on the writing side
6, a gate pulse for the data extraction circuit 22, a control pulse for the CRC decoder 23, and a write clock pulse and a write control pulse for the time base expansion circuit 24 are formed.

The write-side pulse generation circuit 36 is supplied with clock pulses from the clock pulse generation circuit 33, but the write-side control pulses are used to control relatively high frequency time axis fluctuations called jitter in the reproduced signal. Therefore, the vertical synchronization signal D and horizontal synchronization signal from the synchronization signal separation circuit 21 are sent to the pulse generation circuit 36.
supplied to Furthermore, the horizontal synchronization signal D and vertical synchronization signal VD from the synchronization signal separation circuit 21 and the synchronization pulse Pdl corresponding to the data synchronization signal Pd from the tuning circuit 34 are supplied to a data synchronization circuit 37, which will be described later, and the output thereof is used for pulse generation. is supplied to circuit 36. Further, the discrimination bits separated by the gate circuit 25 are supplied to the pulse generating circuit 35 on the read side, and the previous. As described above, when the word read from the time axis expansion circuit 24 is incorrect, the read address is controlled so as to read the next correct word.

The discrimination bit is then supplied to the error correction control circuit 38,
This controls the average value interpolation circuits 28L and 28R, and a correction is made in which the erroneous word is replaced with the average value of the correct words before and after it. In order to perform such error correction, the PCM encoder performs word-by-word interleaf (rearrangement) in order to disperse burst errors caused by dropouts and the like that occur in the VTR1, and the PCM decoder performs word-by-word decoding. It is effective to interleave (restore the order). The expansion of the time axis in the time axis expansion circuit 24 is the opposite of the time axis compression of the PCM encoder, in which the frequency of the read clock pulse is lower (1.4112 [MHz)] than the frequency of the write clock pulse (1.764 [MHz)].
MHz)).

Since this write operation is not performed during the data missing period 1RG, the write clock pulse is gated by the write gate pulse PWG shown in FIG. 5D, which becomes 0° in the data missing period 1RG of the odd field shown in FIG. 5A. It is made to be done. This write gate pulse PWG also serves as a gate pulse for the data extraction circuit 22. 39 is a muting control circuit. The muting control circuit 39 is supplied with the discrimination bits separated by the gate circuit 25 and a signal indicating the state of the PLL circuit constituting the clock pulse generation circuit 33, and when a predetermined number or more of discrimination bits indicating that an error has occurred is generated. Then, the muting circuits 29L and 2
Muting occurs when a muting signal that indicates 9R is a muting operation (referred to as muting on) is generated, and the PLL circuit of the clock pulse generation circuit 33 is in a locked state even though the discrimination bit indicating that an error has occurred has disappeared. A muting signal is generated to turn off circuits 29L and 29R. This muting signal is also supplied to the data synchronization circuit 37. Further, to describe one embodiment of the present invention in detail, FIG. 6 shows a data synchronization circuit 37, to which a synchronization pulse Pdl corresponding to the data synchronization signal Pd from the tuning circuit 34 is applied to a terminal 41.

The tuning circuit 34 uses the frequency of the data synchronization signal Pd, for example, 88
2 [KHz], and the maximum value is approximately at the center of 1H at the 26th hour, corresponding to the data synchronization signal Pd, as shown by the broken line in the data missing period 1RG of the odd field shown in FIG. 5A. The following output is generated, and the synchronization pulse Pdl whose waveform has been shaped by the level discrimination circuit in the tuning circuit 34 is output. Further, terminals 42 and 43 are supplied with a horizontal synchronizing signal HD and a vertical synchronizing signal V from the synchronizing signal separation circuit 21, respectively.
D is supplied, and the muting control circuit 3 is supplied to the terminal 44.
A mutating signal is supplied from 9. The synchronizing pulse Pdl is then guided to the output terminal 46 via the OR gate 45 and supplied to the write-side pulse generating circuit 36 described above. In this case, if there is data with a frequency close to 882 [KHz], a pulse similar to the synchronization pulse Pdl will be obtained from the tuning circuit 34, so the pulse generation circuit 36 will generate a pulse at the beginning after the vertical synchronization signal VD. The generated synchronization pulse Pdl is used. It is sufficient to use only the synchronizing pulse Pdl without considering dropouts that occur in the VTR1, but when the data synchronizing signal Pd is dropped due to dropout, the synchronizing pulse Pdl cannot be obtained, so the synchronizing pulse Pd
The data synchronization circuit 37 is configured to generate an equivalent synchronization pulse Pd2 corresponding to Pd2.

That is, the horizontal synchronization signal HD from the terminal 42 is supplied to the counter 47, and the counter 47 outputs the equivalent synchronization pulse P.
d2 is formed. As mentioned above, the odd field is 26.
Since the period is 3H and the period for even fields is 262H, the counter 47 is 2H for odd fields.
The counter 47 operates as a 63-decimal counter and generates an equivalent synchronizing pulse Pd2 when counting 2 horizontal synchronizing signals HD.In the even field, the counter 47 operates as a 262-decimal counter and generates an equivalent synchronizing pulse Pd2 when counting 262 horizontal synchronizing signals HD. A synchronizing pulse Pd2 is generated. Here, the synchronization signal separation circuit 21 is used not only for the original horizontal synchronization signal book, but also for
Even during the data missing period 1RG, a horizontal synchronizing signal is formed from the equalization pulse, and even when the horizontal synchronizing signal HD cannot be obtained due to dropout, etc., a separately formed equivalent horizontal synchronizing signal is interpolated. 47, the equivalent synchronizing pulse Pd2 can be obtained with sufficient accuracy. 48 is a field discrimination circuit, and this field discrimination circuit 48 detects the phase relationship between the vertical synchronization signal D from the synchronization signal separation circuit 21 and the synchronization pulse Pdl from the tuning circuit 34, thereby distinguishing between an odd field and an even field. A discrimination signal is given to the counter 47.

Once this determination is made, a determination signal is automatically generated to cause the counter 47 to operate as 26 digits (odd field) or as 262 digits (even field). Reference numeral 49 is a synchronization pulse verification circuit, which detects the phase (
When the two phases match, the output is ``1'', and when the two phases are out of phase, the verification output is ``0''.

Furthermore, when the muting is on, the verification output is set to "0" by the muting signal.The verification output from the synchronization pulse verification circuit 49 is supplied to the AND gate 50 together with the equivalent synchronization pulse Pd2. , is supplied to the field discrimination circuit 48 to clear it.The equivalent synchronizing pulse PCl2 passed through the AND gate 50 is sent to the output terminal 46 via the OR gate 45.
can lead to According to the data synchronization circuit 37 described above, during normal operation, the phases of the synchronization pulse Pdl from the tuning circuit 34 and the equivalent synchronization pulse Pd2 match, and even if the data synchronization signal Pd is lost due to dropout, the equivalent synchronization Since the pulse Pd2 is supplied to the pulse generating circuit 36, that is, the equivalent synchronizing pulse Pd2 is interpolated, it is possible to accurately detect the timing of the start of data in a certain field. Therefore, data can be extracted accurately in the data extraction circuit 22. Furthermore, if the horizontal synchronization signal Pd2 cannot be separated correctly due to dropouts, noise, etc., and therefore the equivalent synchronization pulse Pd2 is incorrect, the AND gate 50 is turned off by the verification output from the synchronization pulse verification circuit 49, and the equivalent synchronization pulse Pd2 is incorrect. Pulse Pd2 is prohibited from being interpolated. In this example, if the phases of the synchronizing pulse Pdl and the equivalent synchronizing pulse Pd2 match for two field periods after the interpolation of the equivalent synchronizing pulse Pd2 is prohibited, the equivalent synchronizing pulse Pd2 is interpolated again from the synchronizing pulse verification circuit 49. In order to insert, a test output of "1" is generated.This is done because there is a difference between the odd field and the even field H.
Even though the odd field and even field are reversed from the original, what is the phase of the equivalent synchronizing pulse Pd2? This is because when there is a deviation before and after H, the phase of the equivalent synchronizing pulse Pd2 and the phase of the synchronizing pulse Pdl may coincide with each other. As is clear from the above, according to the present invention, P
Since the CM signal has a signal format similar to that of a television signal, a fairly long data missing period RG corresponding to the vertical blanking period occurs, but since a data synchronization signal is inserted, the data missing period RG is The timing of the start of the first data can be detected accurately.

This allows data to be extracted without error. Furthermore, in the present invention, the data synchronization signal Pd is a simple pulse signal in which ゜゜1゛ and "0" are repeated alternately, and is not a specific code, so it is very easy to form the data synchronization signal Pd. This detection can also be performed by the tuning circuit 34.Furthermore, even if the data synchronization signal Pd is considerably deformed due to the influence of head switching noise, dropout, etc., the difference between ゜1゛ and ゜0゛ within this period. As long as there is even a period in which the above is repeated, the data synchronization pulse Pdl can be obtained from the tuning circuit 34.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PCM encoder according to an embodiment of the present invention, FIG. 2 is a block diagram of the PCM decoder, and FIGS. 3, 4, and 5 are used to explain an embodiment of the present invention. The waveform diagram and FIG. 6 are block diagrams of essential parts of an embodiment of the present invention. 1 is TRl5L, 5R is a sampling hold circuit, 6
L, 6R are AD converters, 8 is a time axis compression circuit, 10 is a data synchronization signal addition circuit, 21 is a synchronization signal separation circuit, 22
is a data extraction circuit, 24 is a time axis expansion circuit, 27L,
27R is a DA converter, 34 is a tuning circuit, and 37 is a data synchronization circuit.

Claims (1)

[Claims] 1. PCM modulating an audio signal to obtain a PCM signal;
The time axis of this PCM signal is compressed to form a data missing period, and a first data synchronization signal, which is a pulse signal of a specific frequency, is generated immediately before the start of data after the data missing period, and a first data synchronization signal, which is a pulse signal of a specific frequency, is transmitted every predetermined period of data. When demodulating the PCM signal by inserting and transmitting the second data synchronization signal,
By separating the second data synchronization signal and counting the second data synchronization signal, an equivalent synchronization pulse having substantially the same timing as the first data synchronization signal is obtained, and together with this, the first data synchronization signal is counted. The synchronization signal is detected by a tuning circuit,
The PCM signal transmission device detects the timing of the start of data after the data missing period based on this detection output, and uses the equivalent synchronization pulse instead when the first data synchronization signal is not detected. 2 PCM modulate the audio signal to obtain a PCM signal,
The time axis of this PCM signal is compressed to form a data missing period that roughly corresponds to the vertical blanking period of the television signal, and a synchronization signal that is approximately the same as the horizontal and vertical synchronization signals of the television signal is added. to convert the PCM signal into a signal format similar to a television signal, and further insert and transmit a data synchronization signal, which is a pulse signal of a specific frequency, immediately before the start of data after the data missing period, and transmit the PCM signal.
When demodulating the signal, by separating the horizontal synchronizing signal and counting this one horizontal synchronizing signal, an equivalent synchronizing pulse having almost the same timing as the data synchronizing signal is obtained, and together with this, the data synchronizing signal is Detected by a tuned circuit,
The PCM signal transmission device detects the timing of the start of data after the data missing period based on this detection output, and uses the equivalent synchronization pulse instead when the data synchronization signal is not detected.