JPS6051941A - Multivariable comparing circuit - Google Patents

Abstract

PURPOSE:To execute quickly a multivariable comparing operation by comparing simultaneously all input variables, in case of detecting the maximum value and the minimum value in a multivariable comparing circuit. CONSTITUTION:Input registers 100-103 strobe a 4-bit data of each digit, respectively. A subscript of each variable bit shows identification of the digit. Basic function blocks 300-303 are constituted of a bit data detecting circuit, a mask bit generating circuit and a bit mask circuit. Connecting buses 200-203 and 400 -403 show connecting buses between registers 100-103 and blocks 300-303 and between each block 300-303, respectively. The buses 400-403 transfer a mask bit of an upper digit to the basic function block of a lower digit. A bus 500 connects the blocks 300-303 and an output register 600, to transfer the data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic unit in a data processing device, and particularly to a multivariable comparison circuit that performs multivariable comparison operations.

<Background> Conventionally, when detecting the maximum or minimum value in multiple variables, when the number of variables is n (n≧2), it is necessary to configure (n-1) two-variable comparison circuits. or by repeating the operation of this two-variable comparison circuit (n-1) times by determining the magnitude relationship between the two variables.

<Purpose of the invention> The purpose of the invention is to
By comparing all input variables at the same time, it is possible to avoid an increase in the amount of hardware due to multistage connection of variable comparison circuits or an increase in calculation time due to repeating this circuit operation many times, thereby speeding up multivariable comparison operations. The object of the present invention is to provide a multivariable comparison circuit that performs the following functions.

<Summary of the Invention> The multivariable comparison circuit according to the present invention masks n 1-bit data of each digit of the variable with mask data transferred from the upper digit circuit for n binary variables of m digits. Bit mask means for performing the operation and n obtained by this mask means
n-bit data detection means for detecting whether all bit data is "1" or "0"; mask bit generation for generating mask bits from data obtained by the bit mask means and the n-bit data detection means; It consists of means.

<Principle of the Invention> First, the operating algorithm of the multivariable comparison circuit according to the present invention will be described below.

1) When calculating the minimum value, 1) Compare the most significant 1-bit data of all variables that are operands, and calculate the minimum value (because it is a binary number, if all are "1", the minimum value is "1#", otherwise The mask data is set for the variable that is "1" among the 1-bit data and transferred to the lower order.

11) All 1-bit data of the next digit is masked with the mask data transferred from the higher order and excluded from the comparison target.

111) Compare the remaining 1-bit data and find the minimum value (
When all are “1”, the minimum value is “1”, otherwise it is °0”
), and using this minimum value, mask data is created for the variable whose 1-bit data is 1", added to the mask data from the 10th digit, and transmitted to the lower order.

! V) Perform the operations in ii) and 111) sequentially from the upper digit to the lower digit 3. As an example of the variables to be compared, 4-digit 4-variable data 7-a = 0
101, b=1001, c=0001.

Considering d=1010, the above operation is shown below for j.

Mask data after comparison abed Minimum value a 'b e d Most significant digit ``0,1,0.1''``0'' ``0,1,
0,1” Upper 2nd digit-11cIL O,r-::,,
* O” ” 1 + I HO+ 1” Upper 3rd digit
"rXJ+L2',0.':,7u "0""1,1
,0.1"Lowest digit IJ・L-J・l,-,1"1,
1・0,1'' 0=0001 is obtained as the minimum value, and M=lIO1 is obtained as the mask data. (The relationship between “1” and “0” is reversed (3).) 2) When calculating the maximum value, 1) Compare the most significant 1-bit data of all variables that are operands, and calculate the maximum value. (Since it is a binary number, when all values are "θ", the maximum value is "0", otherwise "1#"), mask data is created for variables that are 10 out of 1 bit data, and transferred to the lower part. do.

11) Mask all 1-bit data of the next digit with the mask data transferred from the higher order and exclude it from comparison.

111) Compare the remaining 1-bit data and find its maximum value (
When all are “0#”, the maximum value is “0”, otherwise “1”)
Based on this maximum value, mask data is created for a variable whose 1-bit data is ``0'', added to the mask data from the upper order, and transferred to the lower order.

iv) Perform operations ii) and 111) sequentially from the upper digits to the lower digits.

When the above operation (4) is performed on the above data a, b, c, and d, the following will be obtained: 1° comparison mask data abed Maximum value abed Most significant digit “0, 1, 0.1” ”1 "1,0,1.0"
, upper 2nd digit “Σ section, 0,5 Nico, 0” “O”i, o
, i, o" Upper third digit a7: -1,0+'T", 1"
1” -1,, 1, I-, 0” Least significant digit “L:'i+c
0=1010 is obtained as the maximum value of l'hku1,0'''``0''], i, 1.O'', and M=11]0 is still obtained as mask data. (In the circuit description below, the relationship between 1" and 0" in the mask data is reversed to simplify the hardware.) <Example> Next, regarding this invention. This will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the invention. For the sake of explanation, this example uses four variables (a.

b, c, d) Consider the case of 4 digits. Reference numerals 100 to 103 indicate input registers, which strobe the 4-bit data of each digit. The subscript of each variable bit indicates the digit identification. Reference numerals 300 to 303 indicate basic functional blocks, which are composed of a bit data detection circuit, a mask bit generation circuit, and a bit mask circuit. 200-203 and 400-4
03 are input registers 100 to 103, basic function blocks 300 to 303, and basic function blocks 300 to 303, respectively.
303 shows a connection bus between each other, and a connection bus 400
403 transfers the upper digit mask bit to the lower digit basic function block. 600 output registers are shown, 50
0 indicates a bus that connects each basic functional block 300 to 303 and the output register 600 and transfers output data.

FIG. 2 shows the configuration of the i-th basic functional block when calculating the minimum value. 1o(1-i).

40(i-1) and 30(i-1) correspond to input registers 100 to 103, connection buses 400 to 403, and basic function blocks 300 to 303 in FIG.
(i-1), 32(i-1), and 33(i-1) respectively indicate a bit mask circuit, a bit data detection circuit, and a mask bit generation N path, and 40(i-2) indicates (i-1 ) shows the transfer bus for the mask bit output of the basic functional block in the digit. For the most significant digit, transfer bus /10(i-
2) are all "1" inputs.

Figures 3 and 4 are based on the circuit shown in Figure 1 with a = Q10.
1, b=100], c=0001. An example of operation when a variable d-1011 is input is shown. FIG. 3 shows the operation to find the minimum value. Ma, Mb.

Me and M'd are mask data corresponding to variables a, b, c, and d, respectively, and a', b', c', and d' indicate data after masking. 0 represents output data, and the subscript j represents data at the i-th digit. The logical formula is shown below.

(So, the logical product up to the operation symbol (i-1) in the formula, and "+" indicates the logical sum) all-alIIMato1 b, -2bi・Mbi-1 (7) Ci' = Ci eMci-1 di ' = d i llMd1-tOl-ail・
biI@C1I″ ail, 1-1 Mci=Oi・c l+・(J:OM c j)Md
1=oi-di'・(j:oMdj), and for the most significant digit, MB o=Ml) 0=to'Ic o=M
do=1. al'+ b1'+ el'l dj
' is obtained as the output of the bit mask circuit 31 (i-1), Oi is obtained as the output of the bit data detection circuit a2 (i-1), Ma i +Mb i +Mc i ,
Md i is obtained as the output of the mask bit generation circuit a3(i-1). If this calculation operation is performed from the most significant digit to the least significant digit, the minimum value will be obtained at the output O, and the mask data of the least significant digit will have the mask bit corresponding to the variable with the minimum value “
1″ (9) (8) is output.

FIG. 4 shows the operation of calculating the maximum value, and FIG. 5 is an example at this time. Expressed as a logical formula, it is as follows.

ai' = ai -Mai-1 J' = b i -Mbi-1 ci' = c i @M(B-1 di' = d H*Mdj-t (] ”= ai'+ bi'+ci'- 1-di'-
, it Mai=O1@ai・(jr!,.Maj)−1 Mbi=0i−bi′・(jmi.Mbj), 1−l Md+=Oi・d iI・(jjiang.Mdj) So, regarding the most significant digit, Ma O=Mb O=Mc O=Md
Let O=1. When this operation is performed from the most significant digit to the least significant digit, the maximum value is obtained at the output O, and the mask bit corresponding to the variable with the maximum value is "1" in the mask data of the least significant digit.
” is output.

Furthermore, by connecting the circuits of the embodiments shown in FIGS. 2 and 5 in parallel, it is also possible to detect the maximum value and the minimum value simultaneously. FIG. 6 shows an embodiment of the bases connected in parallel, 100 to 600 correspond to the numbers of the embodiment shown in FIG. 1, and in particular, 300 to 303 indicate basic functional blocks that obtain the maximum value.

Also, 2001 to 6001 are 200 to 60 shown in Figure 1.
0, and in particular, 300' to 303' indicate basic functional blocks for obtaining the minimum value. By connecting as shown in FIG. 6, the maximum value of variables a - d is obtained for 01 to 03, and the maximum value of variables a - d is obtained for 011 to 03'.
The minimum value of is obtained. Further, mask data corresponding to the maximum and minimum values of variables a to d, respectively, are obtained as output "1" at 403 and 403'.

Also, by adding 1 bit of selection signal to Fig. 7,
An example of circuit connection when selecting the maximum value or minimum value is shown. , 100 to 600 correspond to 100 to 600 in FIG. 1, and 700 indicates a selection signal input.

In addition, Fig. 8 shows the basic functional block 3゜(i-
1), 34(j-1), 35(i-
1) and 36(i-1) show completely similar two-signal selection circuits. -1), 35 (+-1), 36 (i-1
The broken line in parentheses () represents the connection state when the minimum value is calculated, and the connection on the opposite side when the maximum value is calculated. Further, the connection state is controlled by a selection signal 700. For this circuit as well, the mask pit of the most significant digit, the input M'ao
, Mbo, Men, and Mdo are input with 11", and the least significant digit mask bit output Ma4.Mb4.Mc4.M
A mask bit corresponding to a variable having a maximum value or a minimum value is outputted as @1# to d+ according to the selection.

Effects〉 As explained above, this invention is based on the fact that the increase in the amount of hardware due to the increase in the number of variables is simply an increase in the amount of hardware associated with each signal, and that the bit data of each digit is On the other hand,
It can be configured using exactly the same circuit configuration, the time required for calculation does not depend on the number of variables, and especially when it comes to calculations with many variables and a small number of digits, it can be performed faster than calculations using a two-variable comparator. There are effects such as being able to do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the basic functional block 300 shown in FIG. Fig. 4 is an explanatory diagram of arithmetic operation showing the basic operation when calculating the maximum value, and Fig. 5 is a circuit showing an example of the configuration of the basic functional block when calculating the maximum value. Figure 6 is a block diagram showing a connection example in which the minimum value and maximum value basic function blocks are connected in parallel so that the maximum value and minimum value can be determined at the same time, and Figure 7 is similar to Figure 1. A block diagram showing an example of a configuration in which the maximum value and minimum value can be selectively determined by adding maximum value and minimum value selection signals to the shown circuit. Figure 8 is the basic functional block in Figure 7. FIG. 2 is a connection diagram showing an example of a circuit configuration. 100-103: Input register, 300-303: Basic function block, 600: Output register, 31 (i-1)
: Bit mask circuit, 32 (i-1): Bit data detection circuit, 33 (i-1): Mask bit generation circuit. Patent Applicant NEC Corporation Agent Takuro Kusano 223-

Claims (1)

[Claims] (1) For n m-digit binary variables, the first digit (m
≧i≧1), a bit masking means performs a masking operation using n-bit mask data transferred from the upper digit circuit, and all of the masked n-bit data is @1" or "0". ”, the bit masking means, and the n bit data detection means for detecting that the
A multi-variable comparison characterized in that the multi-variable comparison has a mask bit generating means for generating mask bits based on data obtained by the bit data detecting means and supplying the mask bits to lower digits, and detects the minimum value or maximum value of n variables. circuit.