JPS6051389A - Recording and reproducing device of color video signal - Google Patents

Abstract

PURPOSE:To make a time base of a color difference signal uniform against a luminance signal without increasing a scale of a circuit by constituting so that read-out of a compressing color difference signal against a memory element is executed basing on the first synchronizing signal inserted into the luminance signal. CONSTITUTION:An FM luminance signal SY-FM reproduced from a reproducing head HY is supplied to an FM demodulator 12 through a pre-amplifier 11, and a luminance signal SY is demodulated, and thereafter, supplied to a delay means 40. An FM compressing color difference signal SC'-FM is supplied to an FM demodulater 17 and demodulated, and supplied to a time base expander 20 through a drop-out compensating circuit 50. In order to expand a time base of the signal concerned SC' to its original time base, a memory element 21 is provided, and constituted of three pairs of CCD memories 21A-21F. Also, each color difference signal of red and blue, whose time base has been expanded is supplied to a switching means 31. Also, it is supplied to an encoder 33, respectively, supplied to a mixer 13 and converted to a color video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a color video signal recording and reproducing apparatus suitable for application to integrated video, etc.

BACKGROUND TECHNOLOGY AND PROBLEMS In recording and reproducing devices for color video signals such as integrated video,
There is a system in which a color video signal is divided into a luminance signal and a pair of component color signals and recorded simultaneously on separate tracks.

In this case, for the luminance signal SY as shown in FIG. 1A,
A pair of component color signals shown in B and C in the same figure, for example, red and blue color difference signals R-Y and B-Y, is used as a color video signal.As shown in the same figure, in this example, the time axis is compressed to %. Compressed color difference signals Sc′ are sequentially and alternately arranged temporally every 0.5 horizontal periods, and this compressed color difference signal S
c' and the luminance signal sy are simultaneously recorded on adjacent tracks as shown in FIG. 2A.

In such a recording/reproducing apparatus, it is necessary to align the time axes of the luminance signal SY and the pair of compressed color difference signals Sc', which are simultaneously reproduced from a special reproduction track.
As shown in the figure, a synchronization signal (in this example, a synchronization pulse) PRI + PR2 is inserted into each of the luminance signal sy and the compressed color difference signal Sc'. The first synchronization signal PR1 inserted into the luminance signal sy is a positive polarity signal having a pulse width of % of the horizontal synchronization pulse in this example, in the latter half of the period of the horizontal synchronization pulse pH, as shown in FIG. Similarly, a second synchronization signal PR2 of negative polarity is inserted as a pulse on the same time axis as the first synchronization signal PRI in the compressed color difference signal SC'.

During reproduction, the time axes of the color difference signal Sc with respect to the luminance signal sy are aligned based on the pair of synchronization signals pR1l and PR2, but in order to correctly align the respective time axes, the reproduction system requires a fairly complex time axis adjustment circuit. Currently, we are inserting . Therefore, such a recording/reproducing apparatus has the disadvantage that the circuit scale of the time axis adjustment circuit increases. In order to eliminate this drawback, a time axis expansion system for the compressed color difference signal Sc' may be considered. For example, writing of the compressed color difference signal Sc' is performed in synchronization with the write zero pulse 8l formed based on the second synchronizing signal PR2, and reading thereof is performed based on the first synchronizing signal Pold. This is done in synchronization with the read zero pulse PR.

In this way, the time axis of the expanded color difference signal SC coincides with the time axis of the luminance signal Y, so that the time axis adjustment circuit and the like can be greatly simplified.

However, when the compressed color difference signal Sc' is read out asynchronously with its writing, the writing operation and the reading operation may partially overlap.

That is, the reason why the write zero pulse and the read zero pulse PR are obtained at the same timing as shown in Figure 3 is because the spacing wH between the gears of the rotating magnetic heads HY and HC that contact the magnetic tape as shown in Figure 2B. is the same as the designed value. Therefore, if the interval wH between the gears changes due to manufacturing variations, or if this interval wH differs depending on the video used, or if jitter occurs between Y/C, the write zero pulse 8 l and the read zero pulse PR cannot be obtained at the same timing.

For example, when the gear spacing WH is wider than a specified value, the reproduced luminance signal sy and the compressed color difference signal S
c' is as shown in Figure 4 A and B, including t=
The output zero pulse PR is obtained in a temporally earlier state than the low pulse Pw K (Fig. 4 C, D).

In such a case, the read mode for the memory element starts regardless of the write mode, so as shown in FIG. There is a drawback that writing may start before it is finished.

Purpose of the Invention Therefore, in the present invention, when aligning the time axes of both based on a pair of synchronization signals, it is possible to align the time axes of both accurately with an extremely simple configuration, and it is possible to adjust the write timing. This is so that the read timings do not overlap.

SUMMARY OF THE INVENTION Therefore, in the present invention, data is written to a memory element for compressed color difference signals provided in the reproduction system based on the second synchronization signal PR2 inserted into the compressed color difference signal Sc'. Reading is performed based on the first synchronization signal PR1 inserted into the luminance signal sy. By doing so, the time axes of the pair of color difference signals relative to the luminance signal sy can be easily and accurately aligned.

Three pairs of memory elements, for example CCD memories, are used as memory elements; when the first pair of CCD memories is in the writing state, the second pair of CCD memories is in the sleep state, and the third pair of CCD memories is in the write state. The pair of CCD memories are controlled to be in the read state, and the read clock is one of the loading clocks! - (n is the compression ratio; in this example, n = 2), so that a pair of time-axis expanded color difference signals can be obtained with write timing and read timing completely separated. being done.

Embodiment Next, an example of a recording/reproducing apparatus according to the present invention will be explained in detail with reference to FIG. 5 and subsequent figures.

Luminance signal SY and compressed color difference signal S to be recorded on tape
c' is the synchronizing signal P as shown in FIG. 3A and B, respectively.
R1+P2N2 are inserted, and each is angle-modulated, for example, FM-modulated. The specific configuration of a recording system for producing such a signal format is not directly related to the present invention, so a description thereof will be omitted.

In FIG. 5, 00) indicates an example of a reproduction claw 1 which is the main part of the recording and reproduction apparatus according to the present invention.

FM luminance signal y −F reproduced by the reproduction head HY
M is supplied to the FM demodulator O3 via the preamplifier 7' (111) to demodulate the luminance signal sy, and then to the delay means f4G.
is supplied to

In this example, the configuration is such that it can also be used as a dropout compensation means, and includes a pair of cascade-connected delay elements, one of which is a CCD (411, (4) in the figure).
1 is selected for the IH delay time, while the other CC
D(42)ij: IH1Tp (F6 Figure B)
I) The delay time is selected.

In the case of forming the compressed color difference signal Sc', FIG. 4A.

As shown in B, there is a time difference of IH with respect to the luminance signal Y, and during playback, as shown in E and F of the same figure, the relative time relationship of the color difference signal Sc is further shifted by 11-1 minutes. By delaying the luminance signal Y by 2H, the relative time relationship with the time-axis expanded color difference signal SC is made to match.

The reason why the luminance signal Y is further delayed by TD is to create a predetermined pause period between the end of writing and the start of reading, as shown in FIGS. In this example, the delay time TD is selected to be about 15 μsec in consideration of variations in the inter-head spacing wH and jitter between Y/C.

[431, (44) are oscillators for supplying predetermined clocks to the CCDs (411, (421).
51 is a switching circuit, and when a dropout occurs, the luminance signal before IH, and therefore the output of CCD (411) is used for dropout compensation. A dropout detection signal is supplied to a terminal (46). .

The luminance signal Y delayed by a predetermined time is supplied to the mixer [131, where it is time-axis expanded as described later, and is converted into a luminance signal s.
It is mixed with the color difference signal SC whose time axis is aligned with respect to y, and a normal color video signal Sv is obtained from the terminal (141).

On the other hand, the FM compressed color difference signal C'-FM reproduced by the playback head l-IC is transmitted through the preamplifier (1, 61)
The compressed color difference signal Sc' is demodulated by being supplied to the M demodulator αη. The compressed color difference signal Sc' is sent to the dropout compensation circuit 5.
01 to compensate for dropouts.

As shown in the figure, the compensation circuit 60) includes a CCD 51 for IH delay.
1 and switching circuit I! i2.

The compressed color difference signal Sc' after dropout compensation is supplied to a time axis expander (Inc.).

The time axis expander (to) is provided with a memory element (21) for expanding the time axis of the compressed color difference signal Sc' to the original time axis. Memory element 01) has three pairs of CCD memories (2
1A) to (21F). Write and read clocks, etc. that drive the memory element I2D will be described next.

The luminance signal SY is supplied to the synchronization separation circuit (221), from which the first synchronization signal P old is separated, and based on this first synchronization signal PR1, the VCO (2) is controlled and the first synchronization signal P old is In this example 720 fH (f
A clock having a frequency of H (horizontal frequency) is formed, which is further divided by 1 in a counter C24) to form a read clock of 360 fH, which is supplied to the clock generator (2). The first synchronization signal PRI is further supplied to the clock generator (2) as its reference signal in order to form a write zero pulse PR as shown in the third diagram.

On the other hand, the demodulated compressed color difference signal Sc' is sent to the sync separation circuit (
26), the second synchronization signal PR2 is synchronously separated, and this is supplied to the VCO (5) to generate the second synchronization signal P.
A clock with a frequency of 720 fH synchronized with R2 is generated and supplied as a write clock to a clock generator (c). Then, based on this, the second synchronizing signal PR2 which is also synchronously separated is a write zero pulse Pw (in this example, a read zero pulse PR) shown in the third diagram.
A clock generator (2) is used to generate the same timing as
5).

Next, the loading and reading operations of the compressed color difference signal Sc' will be explained with reference to FIG.

Three pairs of CCD memories (21A) to (211, C
The CD memories (21A), (2IC), and (21E) are memories dedicated to reading and writing the red compressed color difference signal (R-Y)', and the other CCD memories (21B), (2]D
) and (21F) are memories dedicated for reading and writing to the compressed blue color difference signal (B-Y)'. When the first pair of CCD memories (21A) and (21B) are in the write mode, the second pair of CCD memories (21A) and (21B) are in write mode.
IC), (21D) are in hibernation mode, and a third pair of CCD memories (21E).

(21F) The sending timing of the write and read clocks is controlled so as to enter the read mode.

The write, pause, and read modes are sequentially rotated in the above-mentioned order at a cycle of 3H.

Therefore, the timing chart of the CCD memories (21A) to (21F) is shown as J to 0 in FIG.
) to (21F).
! 9 is provided.

Note that during the horizontal blanking period, the color difference signal 1'(, -Y.

Since B-Y does not exist, the line-sequential compressed color difference signals (R-Y)' and (B-Y)' include some no-signal sections (fourth
However, in Fig. 7, the compressed color difference number Sc' is zero writing, and the writing clock is 720fH in synchronization with the e-Rus mark (see Fig. B). −
As shown in G, CCD memories (21
A) to (21F).

That is, in this example, the red compressed color difference signal (R-Y)' on line n-1 is written to the first CCD memory (21A) over a period of 0.5H (D in the figure), and then the next In the 0.5H period, n- is also stored in the 20th CCIJ memory (21B).
A compressed blue color difference signal (B-Y)' (E in the figure) for one line is written. Then, the third CCD memory (2I
C) shows the red compressed color difference signal (R-Y
)' is written over a period of 0.5H in the first half (F in the same figure).
), and in the second half period of 0.5H, the compressed blue color difference signal (B-Y)' on line n is written (G in the same figure).

! 51. 6th CCD memory (21E), (21F
) is a compressed color difference signal (RY)' of n+1 lines,
(B-Y)' is written.

And, for example, the second pair of CCI) memory (21C)
.

(21D) is in write mode, the third pair of C
The CD memories (21E), (21F) are in sleep mode, and the first pair of CCD memories (21A), (21B)
) is in read mode, so the first pair of CCD memories (21A).

(21B) is in read mode at the same time, IJ and B in the same figure.
The color difference signal (R-Y) whose time axis has been expanded as shown in FIG.

(B-Y) is read.

As mentioned above, the write, read, and pause modes change in this order in each CCD memory in 3H cycles, so if a pause period TD is provided between the write mode and the read mode, the write, read, and pause modes change in this order in each CCD memory. Reading is never started.

Furthermore, since there is an IH idle period following the read mode, writing is not started before reading is completed.

When time axis expansion is performed using two pairs of CCD memories, the read mode is followed by the write mode, so there is a risk that writing will start before the read is finished. When time axis expansion is performed using memory, the IH following the read mode is always in the sleep mode, so reading and writing never partially overlap.

A first pair of CCD memories (21A), (21B) and a third pair of CCD memories (21E), (21F
The same is true for O These time-axis extended red and blue color difference signals RY,
B-Y is supplied to switching means C31).

The switching means 01) has first and second switching sections (31A) and (3113) as shown in FIG. 8, and the first switching section (31A) outputs red color difference signals R-Y, Switching control is performed so that blue color difference signals B-Y are output from the second switching unit (31B), respectively.

In this way, in the time axis expansion circuit (to), the time axis compressed red and blue color difference signals (R-Y)', (B-
Y)' is time-axis expanded and sequentially converted into signals and output, and these are each supplied to an encoder (supplied to a droplet, and after being encoded, the color difference signal 8C is supplied to a mixer 03) and becomes a luminance signal SY. The signals are combined and converted into a commonly known color video signal sy.

When writing the compressed color difference signal 8d to the memory element Q1) in this way, it is formed based on the second synchronization signal PR2*:
By writing at the timing of the input zero pulse Pw and reading at the timing of the read zero ξ pulse pR formed based on the first synchronization signal PRI inserted into the luminance signal SV, the time axis of the luminance signal sy and , it is possible to completely match the time axes of the color difference signals SC whose time axes have been expanded. Therefore, the time axis expansion circuit (2) can also be used as a time axis adjustment circuit, and the circuit configuration of the reproduction system is simplified.

If a TD pause mode is provided between the write mode and the read mode, and an IH pause mode is provided between the read mode and the write mode, variations in the inter-head spacing wH and thick spots between Y2O can be avoided. Even if this occurs, the write and read timings will not partially overlap, and a complete color difference signal SC whose time axis has been expanded can always be obtained.

As described in detail, according to the configuration of the present invention, the compressed color difference signal SC' is read out from the memory element (c) based on the first synchronization signal PRI inserted into the luminance signal SV. Therefore, the time axes of the color difference signals RY and HY relative to the luminance signal 8y can be perfectly aligned without increasing the circuit scale.

In addition, the memory element 01) is connected to three pairs of CCD memories (21A
) to (21F), it is possible to completely eliminate partial overlap between writing and reading even if mechanical errors of the rotating magnetic head or jitter occur between Y2O.

[Brief explanation of the drawing]

1 to 4 are diagrams for explaining the present invention, FIG. 5 is a block diagram showing an example of a reproduction system in a color video signal recording and reproduction apparatus according to the invention, and FIGS. 6 and 7 are FIG. 8, a diagram provided for the present invention, is a connection diagram showing an example of a switching means. HY, HC are rotating magnetic heads, sy is a luminance signal, S
G is a compressed color difference signal, (A) is a time axis expander, (C) is a memory element, (21A) to (21F) are CCD memories, (
C) is a clock generator, (C) is an encoder, PR11
PR2 is a first and second synchronization signal, and SV is a color video signal. Same Hidemori Matsukuma, knee) \ ″] -531- < r:D Q low

Claims (1)

[Claims] A pair of component color signals and luminance signals compressed in time axis within one horizontal section are simultaneously recorded on separate tracks,
During playback, the pair of component color signals are written into the memory element based on the second synchronization signal inserted into the component color signal, and the pair of component color signals are written into the memory element based on the first synchronization signal inserted into the luminance signal. A pair of component color signals written in the element are read out and their time axes are extended, and a pair of component color signals whose time axes are aligned with respect to the luminance signal are obtained, and the memory element is Three pairs of memory elements are used, and when the first pair of memory elements is in a write state, the second pair of memory elements is put into a dormant state and the third pair of memory elements is in a read state. A recording and reproducing device for color video signals.