JPS6051295B2 - Waveform shaping circuit - Google Patents

Waveform shaping circuit

Info

Publication number
JPS6051295B2
JPS6051295B2 JP5886280A JP5886280A JPS6051295B2 JP S6051295 B2 JPS6051295 B2 JP S6051295B2 JP 5886280 A JP5886280 A JP 5886280A JP 5886280 A JP5886280 A JP 5886280A JP S6051295 B2 JPS6051295 B2 JP S6051295B2
Authority
JP
Japan
Prior art keywords
duty
section
waveform shaping
output
level voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5886280A
Other languages
Japanese (ja)
Other versions
JPS56156053A (en
Inventor
裕治 西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP5886280A priority Critical patent/JPS6051295B2/en
Publication of JPS56156053A publication Critical patent/JPS56156053A/en
Publication of JPS6051295B2 publication Critical patent/JPS6051295B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/10Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14Demodulator circuits; Receiver circuits

Description

【発明の詳細な説明】 本発明は、正弦波信号等の非方形波信号を方形波信号に
変換する波形整形回路例えばFSK復調装置における受
信信号復調のための波形整形回路に関し、該回路の出力
デューティを安定化しようとするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform shaping circuit for converting a non-square wave signal such as a sine wave signal into a square wave signal, for example, a waveform shaping circuit for demodulating a received signal in an FSK demodulator. This is intended to stabilize the duty.

FSK復調装置で用いられる復調方法には、入力信号(
正弦波)を波形整形して方形波に変換した後、半周期毎
にその時間を測定して周波数が高い方か低い方かを判定
して、FSK信号を再生する方法がある。
The demodulation method used in the FSK demodulator includes an input signal (
There is a method of reproducing an FSK signal by shaping a sine wave (sine wave) and converting it into a square wave, and then measuring the time every half cycle to determine whether the frequency is higher or lower.

第1図は該装置の復調出力を示すもので、1.2KH2
が中心周波数である。FSK信号としては1.2±O、
1KH2の範囲て周波数が変化し、1.1KH2が復調
出力H(ハイ)に対応し、また1.3KH2がL(ロー
)に対応する。横軸のカツコ内は各周波数の半周期を示
したものてある。ところで、波形整形された方形波の出
力デューティサイクルが安定していないと半周期ごとに
測定される時間が違つてくるため、FSK信号を正確に
復調できなくなることがある。例えは土木±O、IKH
2(7)FSK信号を上記の復調方法て復調する場合、
デューティが4.16%以上すれると中央の1.2KH
2より高い(低い)信号が低い(高い)信号として判定
されてしまい、誤動作が生じる。これを第2図で説明す
る。同図aは周波数1.1KH2でデューティ50%の
波形を示したものであるが、これが5%ずれると、つま
り同図をのようにデューティが45%(55%)になる
と※印部分が1.2にH2の波Jの周期以下になる。逆
に同図cに示す1.3KH2の波形(デューティ50%
)が変動して同図dのようにデューティ45%(55%
)になると※印部分が1.2KH2の波の周期以上にな
る。波形整形回路の出力デューティが変動する原因丁と
しては、入力信号レベルの変動、電源電圧の変動による
閾値の変動等が考えられる。
Figure 1 shows the demodulated output of the device, which is 1.2KH2
is the center frequency. 1.2±O as FSK signal,
The frequency changes within a range of 1KH2, 1.1KH2 corresponds to demodulated output H (high), and 1.3KH2 corresponds to L (low). The box on the horizontal axis shows the half period of each frequency. By the way, if the output duty cycle of the shaped square wave is not stable, the time measured every half cycle will be different, which may make it impossible to accurately demodulate the FSK signal. For example, civil engineering ±O, IKH
2(7) When demodulating an FSK signal using the above demodulation method,
When the duty is 4.16% or more, the center 1.2KH
A signal higher (lower) than 2 will be determined as a low (high) signal, resulting in malfunction. This will be explained with reference to FIG. Figure a shows a waveform with a frequency of 1.1KH2 and a duty of 50%, but if this deviates by 5%, that is, if the duty becomes 45% (55%) as shown in the figure, the part marked * will become 1. At .2, the period becomes less than the period of wave J of H2. Conversely, the waveform of 1.3KH2 (duty 50%) shown in figure c
) changes and the duty becomes 45% (55%) as shown in d in the same figure.
), the part marked with * becomes more than the wave period of 1.2KH2. Possible causes of fluctuations in the output duty of the waveform shaping circuit include fluctuations in the input signal level, fluctuations in the threshold value due to fluctuations in the power supply voltage, and the like.

ところが、従来の波形整形回路1は第3図のように波形
整形部2とデューティ設定部3で構成されるのが一般的
であるため、設定部3で設定される波形整形部2の閾値
(動作点)は固定されているので入力信号のスライス希
望電位と閾値との相対関係が前記原因で変動した場合、
FSK信号等の入力信号囚を波形整形した方形波信号0
頃゛のデューティが変動することは不可避である。本発
明は、波形整形部出力のデューティ変動を打消す自動制
御系を設けることで出力方形波のデューティを常に一定
に保つようにしたものであるが、以下図示の実施例を参
照しながらこれを詳細に説明する。
However, since the conventional waveform shaping circuit 1 is generally composed of a waveform shaping section 2 and a duty setting section 3 as shown in FIG. Since the operating point (operating point) is fixed, if the relative relationship between the slice desired potential of the input signal and the threshold changes due to the above reasons,
Square wave signal 0 obtained by shaping the input signal such as FSK signal
It is inevitable that the duty of the driver will fluctuate from time to time. In the present invention, the duty of the output square wave is always kept constant by providing an automatic control system that cancels the duty fluctuation of the output of the waveform shaping section. Explain in detail.

第4図は本発明の概略ブロック図で、波形整形部2の出
力の一部を受け、そして方形波信号0UTの1周期のう
ちハイレベルになる時間の割合に比例した平均ハイレベ
ル電圧VH並びに1周期のうちローレベルになる時間の
割合に比例した平均ローレベル電圧を出力するデューテ
ィ検出部4と、該電圧■H,VLを比較し、両者に差が
ある場合にその差が減少する方向に波形整形部2の閾値
を制御するデューティ比較部5とでデューティ変動を打
消す自動制御系を構成する。
FIG. 4 is a schematic block diagram of the present invention, in which a part of the output of the waveform shaping section 2 is received, and the average high level voltage VH and The duty detection unit 4 outputs an average low level voltage proportional to the proportion of time at low level in one cycle, and the voltages H and VL are compared, and if there is a difference between the two, the direction in which the difference decreases is determined. and a duty comparison section 5 that controls the threshold value of the waveform shaping section 2, forming an automatic control system that cancels out duty fluctuations.

第5図は第4図を具体化した本発明の一実施例である。FIG. 5 is an embodiment of the present invention that embodies FIG. 4.

波形整形部2は結合コンデンサC3、該コンデンサによ
り直流成分が阻止された入力信号INの中心レベルを規
定する直列抵抗R3,R4、および該直列抵抗の接続点
電位を反転側入力とする差動増幅器A1からなり、該増
幅器A1の非反転側入力にデューティ比較部5の出力V
,が供給されることにより、デューティが50%の安定
した方形波信号0UTが得られる。デューティ検出部4
は、方形波信号0UTの一部を反転するインバータ11
のハイレベル出力で抵抗R1を通してコンデンサC1を
充電する第1の充電部4aと、インバータ11の出力を
更に反転するインバータ12のハイレベル出力で抵抗R
2=R1を通してコンデンサC2=.C1を充電する第
2の充電部4bからなる。充電部4aの出力が前述した
平均ローレベル電圧■,であり、また充電部4bの出力
が平均ハイレベル電圧■8である。デューティ比較部5
は上記電圧■H,VL.を入力とする差動増幅器A2を
要部とし、その出力が波形整形部2の閾値電圧■sとな
る。この電圧■,は電源電圧或いは入力レベルが変動し
ても常に出力0UTのデューティを一定(本例では50
%)に保つ様に変化する性質を有する。出力0頃゛のデ
ューティが50%ということは検出部4の出力がVH=
Vしになることを意味し、VH/VL或いはVH<VL
になれば増幅器A2はそれを打消す様に修正された電圧
■sを発生する。最も簡単には■DDを正電源、■sを
負電源として抵抗R3,R4の接続点を無人力で0Vと
し、且つ■8=■LでVs=0となるように設定すれば
よいが、実際には増幅器〜の利得をGA2とするととな
るので、定常状態では■,/G,,2なる制御誤差を生
じる。
The waveform shaping unit 2 includes a coupling capacitor C3, series resistors R3 and R4 that define the center level of the input signal IN whose DC component is blocked by the capacitor, and a differential amplifier whose inverting input is the potential at the connection point of the series resistors. A1, and the output V of the duty comparator 5 is connected to the non-inverting input of the amplifier A1.
, a stable square wave signal 0UT with a duty of 50% can be obtained. Duty detection section 4
is an inverter 11 that inverts a part of the square wave signal 0UT.
The first charging section 4a charges the capacitor C1 through the resistor R1 with the high level output of the inverter 11, and the resistor R with the high level output of the inverter 12 which further inverts the output of the inverter 11.
2=through R1 to capacitor C2=. It consists of a second charging section 4b that charges C1. The output of the charging section 4a is the above-mentioned average low level voltage ■, and the output of the charging section 4b is the average high level voltage ■8. Duty comparison section 5
is the above voltage ■H, VL. The main part is a differential amplifier A2 which receives as input, and its output becomes the threshold voltage ■s of the waveform shaping section 2. This voltage ■, always keeps the output 0UT duty constant even if the power supply voltage or input level changes (in this example, 50
%). The duty around output 0 is 50%, which means that the output of the detection section 4 is VH=
VH/VL or VH<VL
If so, amplifier A2 generates a modified voltage s to cancel it. The easiest way to do this is to use ■DD as a positive power source and ■s as a negative power source, and set the connection point of resistors R3 and R4 to 0V by hand, and set it so that when ■8=■L, Vs=0. In reality, the gain of the amplifier ~ is assumed to be GA2, so that a control error of {circle around (2), /G,, 2} occurs in a steady state.

しかし、GA2′.00とすれば・となるので、V:3
は常にVH=■Lとなるように変化すると考えて差し支
えない。上記実施例では出力0UTのデューティを50
%に保つ場合を例としたが、デューティ検出部4と比較
部5の間に第6図に示す様に分圧回路6を挿″入すれば
、出力0UTのデューティを任意の値で一定に保つこと
ができる。
However, GA2′. If it is 00, it becomes ・, so V: 3
It is safe to assume that VH always changes so that VH=■L. In the above example, the duty of output 0UT is 50.
%, but if a voltage divider circuit 6 is inserted between the duty detection section 4 and the comparison section 5 as shown in Fig. 6, the duty of the output 0UT can be kept constant at any value. can be kept.

即ち、分圧回路6は第1の充電部4aの出力VLを分圧
する可変抵抗VRlと、第2の充電部4bの出力VHを
分圧する可変抵抗VR2とを備えるが、差動増幅器〜の
入力は可変抵抗VRl,VR2の出力V″L,V″6と
なるため、出力V,はV″5=V″9で0となる。この
ため、可変抵抗■Rl,■R2の分圧比を異ならせれば
、■H半■。でV,=0にすることができるので、出力
0UTをデューティ50%以外の値で安定させることも
できる。第7図は入力レベルの変動に対する出力デュー
ティの安定度を示すものて、曲線イは第5図の本発明回
路によるもの、曲線口は第3図の従来回路によるもので
ある。
That is, the voltage dividing circuit 6 includes a variable resistor VRl that divides the output VL of the first charging section 4a and a variable resistor VR2 that divides the output VH of the second charging section 4b. are the outputs V″L and V″6 of the variable resistors VRl and VR2, so the output V becomes 0 with V″5=V″9. Therefore, if the voltage division ratio of the variable resistors ■Rl and ■R2 is made different, ■H and half■ can be obtained. Therefore, the output 0UT can be stabilized at a value other than the duty of 50%. FIG. 7 shows the stability of the output duty with respect to input level fluctuations. Curve A is for the circuit of the present invention in FIG. 5, and curve A is for the conventional circuit in FIG. 3.

同図から明らかなように、曲線イは全域て略一様てある
のに対し、曲線口の安定範囲は一部に限られる。第8図
は電源電圧範囲は一部に限られる。第8図は電源電圧の
変動に対する出力デューティの安定度を示すもので、曲
線イは同じく本発明回路によるもの、曲線口は従来回線
によるものである。この場合でも曲線イは電源変動の影
響を受けないのに対し、曲線口は電源源電圧と共にデュ
ーティが変化する。以上述べたように本発明によれば、
波形整形回路の出力デューティを常に一定に保つことが
できるので、これを精度が要求されるFSK復調装置に
適用すれば常に正確な復調出力が得られる利点がある。
As is clear from the figure, the curve A is approximately uniform over the entire area, whereas the stable range of the curve opening is limited to a certain part. In FIG. 8, the power supply voltage range is limited to a part. FIG. 8 shows the stability of the output duty with respect to fluctuations in the power supply voltage. Curve A is also for the circuit of the present invention, and curve A is for the conventional line. Even in this case, the curve A is not affected by power supply fluctuations, whereas the duty of the curve A changes with the power source voltage. As described above, according to the present invention,
Since the output duty of the waveform shaping circuit can always be kept constant, if this is applied to an FSK demodulator that requires precision, there is an advantage that accurate demodulated output can always be obtained.

【図面の簡単な説明】 第1図はFSK復調方式の説明図、第2図a〜dはデュ
ーティ変動による誤動作の説明図、第3図は従来の波形
整形回路の概略ブロック図、第4図は本発明の波形整形
回路の概略ブロック図、第5図は本発明の一実施例を示
す回路図、第6図は本発明の他の実施例を示す要部回路
図、第7図および第8図は入力レベル変動および電源電
圧変動に対する出力デューティの安定性を示す特性図で
ある。 図中、1は波形整形回路、2は波形整形部、4はデュー
ティ検出部、4aは第1の充電部、4bは第2の充電部
、5はデューティ比較部である。
[Brief Description of the Drawings] Fig. 1 is an explanatory diagram of the FSK demodulation method, Fig. 2 a to d is an explanatory diagram of malfunction due to duty fluctuation, Fig. 3 is a schematic block diagram of a conventional waveform shaping circuit, and Fig. 4 5 is a schematic block diagram of a waveform shaping circuit of the present invention, FIG. 5 is a circuit diagram showing one embodiment of the present invention, FIG. 6 is a main part circuit diagram showing another embodiment of the present invention, and FIGS. FIG. 8 is a characteristic diagram showing the stability of the output duty with respect to input level fluctuations and power supply voltage fluctuations. In the figure, 1 is a waveform shaping circuit, 2 is a waveform shaping section, 4 is a duty detection section, 4a is a first charging section, 4b is a second charging section, and 5 is a duty comparison section.

Claims (1)

【特許請求の範囲】 1 非方形波信号を同一周波数の方形波信号に変換する
波形整形部と、該波形整形部の出力の一部を受け、そし
て該方形波信号の1周期のうちハイレベルになる時間の
割合に比例した平均ハイレベル電圧並びに該1周期のう
ちローレベルになる時間の割合に比例した平均ローレベ
ル電圧を出力するデューティ検出部と、該デューティ検
出部からの平均ハイレベル電圧と平均ローレベル電圧を
比較し、両者に差がある場合にその差が減少する方向に
該波形整形部の閾値を制御するデューティ比較部とを備
えたことを特徴とする波形整形回路。 2 デューティ検出部は、波形整形部の出力方形波信号
を反転した信号のハイレベルで充電されて平均ローレベ
ル電圧を出力する第1の充電部と、該反転信号を更に反
転した信号のハイレベルで充電されて平均ハイレベル電
圧を出力する第2の充電部とを備えることを特徴とする
、特許請求の範囲第1項記載の波形整形回路。
[Claims] 1. A waveform shaping section that converts a non-square wave signal into a square wave signal of the same frequency; a duty detection section that outputs an average high-level voltage proportional to the proportion of time when the voltage is low in one cycle and an average low-level voltage proportional to the proportion of the time when it is low level in one cycle; and an average high-level voltage from the duty detection section. and a duty comparison section that compares the average low-level voltage and the average low-level voltage, and if there is a difference between the two, controls the threshold value of the waveform shaping section in a direction that reduces the difference. 2 The duty detection section includes a first charging section that is charged with the high level of a signal obtained by inverting the output square wave signal of the waveform shaping section and outputs an average low level voltage, and a high level of a signal obtained by further inverting the inverted signal. 2. The waveform shaping circuit according to claim 1, further comprising: a second charging section that is charged with a second charging section and outputs an average high-level voltage.
JP5886280A 1980-05-02 1980-05-02 Waveform shaping circuit Expired JPS6051295B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5886280A JPS6051295B2 (en) 1980-05-02 1980-05-02 Waveform shaping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5886280A JPS6051295B2 (en) 1980-05-02 1980-05-02 Waveform shaping circuit

Publications (2)

Publication Number Publication Date
JPS56156053A JPS56156053A (en) 1981-12-02
JPS6051295B2 true JPS6051295B2 (en) 1985-11-13

Family

ID=13096520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5886280A Expired JPS6051295B2 (en) 1980-05-02 1980-05-02 Waveform shaping circuit

Country Status (1)

Country Link
JP (1) JPS6051295B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58143626A (en) * 1982-02-22 1983-08-26 Hitachi Ltd Data discriminating circuit
JPS59257A (en) * 1982-06-25 1984-01-05 Pioneer Electronic Corp Digital modulating signal reader
JPS5952417A (en) * 1982-09-16 1984-03-27 Toshiba Corp Data sampling circuit
JPS59127337U (en) * 1983-02-17 1984-08-27 ソニー株式会社 Waveform shaping circuit
JPS6094527A (en) * 1983-09-30 1985-05-27 テクトロニツクス・インコーポレイテツド Rectangular pulse generator
JPS6135440U (en) * 1984-07-31 1986-03-04 株式会社アドバンテスト clock shaping circuit
JPS6168523U (en) * 1984-10-09 1986-05-10
JPS62111516A (en) * 1985-11-09 1987-05-22 Victor Co Of Japan Ltd Pulse width automatic correction circuit
DE4407054C2 (en) * 1994-03-03 1999-11-18 Philips Patentverwaltung Circuit arrangement for converting sinusoidal signals into rectangular signals

Also Published As

Publication number Publication date
JPS56156053A (en) 1981-12-02

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