JPS6050965A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a Schottky barrier gate type FET adapted for a high frequency operation by forming the regions of gate, source and drain in a self- alignment, thereby ultrafinely forming gaps thereamong, and reducing a series channel resistance. CONSTITUTION:Si<+> ions are implanted to the surface layer of a semi-insulating GaAs substrate 11 to form an operating layer 12', an N type Ge thin layer 18 is covered thereon, an As-doped SiO2 film 19 is covered. Then, a photoresist film 10 having a hole on the overall surface is provided, a hole is opened by reactive photoetching at the film 19, and an overetched hole is then opened by plasma etching using O2 and OF4 at the layer 18. Subsequently, the film 10 is altered to the film 10' to block the hole, etched to remove the exposed portion of the film 19 to expose the layer 18, the film 10' is removed, metal layer 21 of Ti, or W and an aluminum layer 22 are laminated on the overall surface. Thus, a source electrode 16 and a drain electrode 17 and a gate electrode 15 isolated at an interval and made of laminated metal are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to field effect transistors, and specifically relates to 1) a structure of a Schottky barrier gate type field effect transistor suitable for high frequency operation and a method for manufacturing the same.

[Technical background of the invention and its problems]

Gallium arsenide (GaAs) semi-rod elements have superior high-speed performance compared to silicon hand-knitted single-piece elements, so research into them has been conducted in recent years.
Development is progressing rapidly. Special vc()aAsAs Schottky barrier gate field effect transistor (GaA, s
MESFE'I') is being put into practical use as a microwave element, and is also one of the most important elements as a major groove number element in GaAs IC.

Improved GaJrs MESFET CD performance above f, 6
*It is necessary to reduce parasitic resistance and capacitance as much as possible.

In particular, it is important to keep the channel series resistance between the source and gate electrodes low.

However, in the conventional GaAs MESFJuT, for example, the first
As shown in the figure, an n-type semiconductor layer (2) is formed on a semi-insulating OaAs substrate (1) by ion implantation, and then an n+ implanted layer (3) in the source region and an n-type semiconductor layer (3) in the drain region are formed.
+ injection polishing (4) is provided, and the gate electrode (5) is provided on the n-type semi-rod layer (2) sandwiched between both regions.

A source electrode (6) and a drain electrode (
7) is provided. In the diagonal structure, it is necessary to allow for errors in mask alignment in each photoetching process, and due to the limitations of photoetching technology, it is necessary to provide a certain distance between the source and the gate. Therefore, as mentioned above, nm active layer +2) VC
However, the reduction in series resistance is slow, and even if the gate length is made submicron, the performance is not as good as expected.

In addition, the source electrode (6) and drain' were connected once ('7).
Usually, a gold-germanium (Au-Ge) composite thread is used, but an alloy of the electrode metal and GaAs crystal, called an alloy, is required to form the electrode. During this alloying process, the metal often reacts unevenly due to VC, resulting in island-like aggregation (ball-up).
The flat electrodes in Table 1 are it, ill I.
Because of the large size, it became one of the hindrances to forming an integrated circuit (IC) using a number of I'4ESFETs.

[Purpose of the invention]

The present invention obviates the above-mentioned drawbacks and aims to provide a new/Yacht-Kivaliagut-type field effect device and a method for manufacturing the same.

According to this invention, the same metal can be used for the source and drain electrodes by self-alignment, and since they can be formed simultaneously, the manufacturing process can be significantly shortened.

[4 Summary of the Invention] The first field effect transistor of the present invention includes at least one metal layer provided on one main surface of an n-type semiconductor, and the connection with the main surface forms a barrier with this semiconductor. 1. A gate electrode layer, which is a metal layer, is formed, a germanium layer is deposited on the surface of the substrate so as to sandwich the gate electrode; Each of the source and drain consists of at least one layer, with the same metal layer connected to the main surface as the connection layer to the substrate.
A structural feature with an electrode layer is provided. Next, the second invention (f) (the method for manufacturing such a field effect transistor includes the steps of depositing a germanium thin film on the surface of the active layer, and laminating the germanium thin film to a thickness that is thicker and smaller than the electrode metal layer of this element. a step of forming an insulating film consisting of a single layer;
A step of forming a first hole in the insulating film in the area where the gate is to be formed, and then etching the insulating film over a wide area including the hole in the germanium thin film as an etching mask; a step of providing a second aperture in the insulating film facing the first aperture, and a step of depositing and patterning an electrode metal layer to form a gate electrode in the first aperture and forming a second aperture in the first aperture. forming a source electrode and a drain electrode in the opening, respectively. Furthermore, even if the insulating film in contact with the germanium thin film in the manufacturing method of the present invention is doped with an impurity that becomes a donor for germanium,
Alternatively, the atmosphere in the step of heat-treating the semiconductor substrate together with the germanium thin film may be an atmosphere containing arsenic.

[Embodiments of the invention]

Next, one embodiment of the present invention will be explained in detail with reference to the drawings.

First, (J)aAs MESF, IB'J,
' f In Figure 2, (Iυ is semi-insulating GaA
An n-type semiconductor layer (121° (131 is the source region and A4) is formed by ion implantation on the 1st side of the S substrate.
is a drain region, (19 is a lamination of a metal layer (21g) such as Ti or W, 'J, 'a, etc., which is deposited on an example n-type semiconductor layer and forms a 7-layer barrier with this semiconductor, and an aluminum layer (22g). gate electrode layer, Uω, aη
are a source electrode layer and a drain electrode layer, respectively, which are formed simultaneously with a semiconductor layer (a germanium thin layer deposited on the main surface of the semiconductor layer (the gate electrode layer 05) sandwiched therebetween). Therefore, the source electrode layer 06) has a metal layer (21s) such as Ill + or WlTa that forms a barrier with this semiconductor as a lower layer, and an aluminum layer (22S) as an upper layer. The drain electrode layer 07) is made of a metal layer (such as Ti 1 , uW, Ta, etc.) that forms a barrier with the underlying semiconductor.
21d) and the upper layer is an aluminum layer (22d). As shown in FIG. 8, this invention uses, for example, As5G (As d
A spacer layer aω of the opened glass may be left. Note that each of the electrode layers may be only one layer forming a barrier with the semiconductor.

Next, one embodiment of the manufacturing method of this invention is shown in FIGS. 3 to 8.
The 1-song VC process will be explained with reference to the diagram.

Si ions (Si
+) at an acceleration energy of 120 keV and a dose of 3.5
An injection layer (12') is selectively formed in the x 1012 cm two-layer MES 11'ET formation region. Furthermore, a Ge thin film is deposited on the entire upper surface of the substrate including this injection layer to a thickness of about 70 OA, and then an arsenic-doped 7-lion oxide film αω (A,
s S G M ) to a thickness of approximately 7000X. Next, a photoresist film (10) is applied and a hole (10a) with a length of 0.5 μm is formed in the photoresist film by photoetching (FIG. 3).

Next, through the opening A s S G 14α9)tJ
Etching is performed using 12 gas and OF gas, or by active ion etching (1tII!i). As a result, a window with a substantially vertical cross section is formed in the As 8 G membrane σ wing. Next, the Ge thin film was inserted through the opening with 02 and OI.
, etched by plasma etching using +4 gas. As a result, the Ge thin film is over-etched, and the openings in the overlying AsSG film are also widened (FIG. 4).

Next, the photoresist film (10) is removed and annealed at 850°C for 215 minutes in an argon gas atmosphere containing AS to activate the injection layer (12') and activate the active layer (12').
form a force. Note that this annealing also serves as the heat treatment performed after the Ge thin film is formed, and as a result, ()e and GaA
s reacts, and As is also doped into the Ge thin film at a high concentration (FIG. 5). Photoresist film (1o') again
The A s
The SG film is etched to expose the Ge surface (FIG. 6). Next, the photoresist film (1o') is removed (Fig. 7), the titanium layer (2I) of the example is applied to a thickness of about 1000X, and the aluminum layer (2I) is then formed to a thickness of about 4000X to a thickness of about 4000X. The gate electrode (15) is deposited sequentially from
A north electrode (1G) and a drain polarization α7) are formed at the same time (FIG. 8).

In FIG. 8, the metal layer eυ such as Illi, W, IIIa, etc., which forms a barrier with this semiconductor, is formed by the ASSG film (19') as a gate, source,
Gate electrode layer (21g) separated into each drain electrode part
, source electrode layer (21s), drain electrode layer (2td
), and an aluminum layer formed by laminating (7!).
The gate electrode is separated in the same way as above;
, source-electrode layer (22s), drain electrode layer (22d)
) are formed respectively.

Note that the electrode metal layer is an active layer (+21 or a Ge thin film (
18) A metal layer forming a layer directly connected to the semiconductor and the metal layer t, which is not limited to titanium as an example, for example,
It may be a 1-i melting point metal such as W or Ta, and the layer J
The thickness should be determined in balance with the thickness of the As5GJ layer, which is an example of an insulating film for a spacer. However, the insulating film for the spacer is not limited to one layer, but can also be made of two or more layers in order to make it thicker and more reliably separate the unwanted metal and electrode parts. good.

Next, a manufacturing example using an As5G film and a Si3N4 film as the spacer insulating film will be described with reference to FIGS. 9 to 13 to explain the differences from the above-mentioned embodiment. Note that parts that are the same as those in the above-described embodiments are indicated by the same numbers in the drawings, and explanations thereof will be omitted.

First, the field effect transistor formed by the method of this embodiment shown in FIG.
21g) with a minute gap between it and the opposing Ge thin layer (18').

Next, in the formation of a spacer layer in the manufacturing process, a Ge thin film (
18) lcAssG film (19') covered M L, further I
U! Silicon nitride film (Si3N4 film) (20)
This is used as a spacer layer for later lift-off formation of the electrode layer. For this reason, the film thickness of the - example was reduced to approximately 500
0X.

It is formed to about 400 OA (Fig. 10).

Deposit a photoresist film 00), with an example of 0.5μ
A Si3N film (2υ) is plasma etched using, for example, 02 gas and QI+ to form a hole (1 ob) from the aperture (10a) of m (FIG. 11).

Furthermore, K overetching was performed on the As5G film (19') through the opening (1, ob) of the Si3N4 film,
Opening hole (10c) with a larger area than the opening hole (1ob)
is formed on the As5G film. Next, this opening (10c)
Then, the Ge thin film (18) is etched. This ASSG
Etching for IIal/C does not require overetching as in the first embodiment. (12th
figure).

The following steps are almost the same as those explained in Step 8 of the first embodiment with reference to FIGS. 5 and after, and even in the final state shown in FIG. MESFET is formed in the same manner.

When two layers of spacer insulation +y are used in this example, the thickness of the spacer film can be made thicker, and the cross section of the opening can be devised by taking advantage of the etching characteristics of each film, which eliminates the electrode metal deposition process. Short circuits between electrodes can be prevented even when metal is pushed into the side of the opening. Here A s S
Although the case of two layers of G film has been described, the combination is not limited to these. For example, a combination of PSG film and 5i02
A combination of films or the like may be used, or even three layers of insulating films may be provided.

In the case of three layers, the intermediate layer may be formed as an upper layer (Si3N, film) or a lower layer (As80 layer) with respect to both adjacent layers.

In each of the above embodiments, ion implantation was used as a means for forming the active layer 0.2), but other methods, such as vapor phase epitaxy, may be used to form an epitaxial layer. In this case as well, the GeO heat treatment may be performed under the same conditions as in the above two embodiments. Further, even when forming the active layer by ion implantation, the impurity to be implanted is not limited to silicon, and it goes without saying that other impurity ions such as selenium (Se) may be used.

In the above two implementations, an As5G film was used as the insulating film on the C4e thin film, and care was taken to introduce IF As into the Ge thin film during the subsequent heat treatment, but the insulating film on the Ge thin film is not necessarily Gevc. There is no need to include impurities that serve as donors. However, in order to form high-performance transistors with good reproducibility, it is necessary to apply Ge to a bacterial concentration and to lower the contact resistance of the source and drain portions. Therefore, it is preferable to use an insulating film doped with impurities as in the above embodiment.Next, in the 7-barrier cage field effect transistor of the present invention, the effective distance between the source and drain can be significantly shortened, and However, since the electrode metal is left on the spacer insulating film, there is a risk of parasitic interaction with the remaining metal. If capacity is a problem, a step of removing some or all of these may be added. This step-2 can be easily carried out by a combination of ordinary photoetching technology and etching technology.

〔Effect of the invention〕

As described above, according to the present invention, the effective gap between the source and the gate can be determined using the Ge thin spacer described in the first embodiment or the Ge thin spacer described in the second example. Since the film can be overetched by the amount of film overetching, and the gate, source, and drain regions can be formed in self-alignment across this microgap, it is possible to significantly reduce the channel series resistance without impairing the gate breakdown voltage. Become.

Furthermore, ohmic contact electrodes on the source and drain parts,
The Schottky contact electrode in the gate area can be formed from the same metal at the same time, and there is no need for an alloying process to form an ohmic contact, so there is no AuGe ball-up that often occurs in the alloying process, and a smooth electrode can be formed. MES with? 'ET is obtained.

Furthermore, since the mask alignment precision required in the conventional MESFET manufacturing process is not required, the effect of improving productivity is significant.

[Brief explanation of the drawing]

Figure KS1 is a cross-sectional view of a conventional 7-barrier gate field effect transistor, and Figures 2 and 8 are cross-sectional views of a 7-barrier gate field-effect transistor of the l embodiment.
3 to 7 are cross-sectional views showing the manufacturing method of one embodiment in the order of steps, and FIGS. 9 and 12 are cross-sectional views of Schottkino-rear gate field effect transistors of other embodiments. 10 and 11 are sectional views showing the manufacturing method of another embodiment in the order of steps. 11... Semi-insulating GaAs substrate 12...
... Operation (to) (12'... injection layer) 13 (14)
...Source (drain) region n+ injection layer 15...
Gate electrode layer 21 (21g, 21s, 21d)...Nyotoki barrier forming metal J@ (Ti, W, Ta, etc.) 22 (22g, 22s, 22d)...Aluminum layer 1
6...Source electrode layer 17...Drain electrode layer 18 (18')...Germanium layer 19...As5G film 20...S i3N, patent attorney Mr. Inoue 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 9 Figure 10 Figure 11 Figure 12 Procedure amendment (method) Commissioner of the Patent Office Manabu Shiga 1, Indication of the case 1982 Patent Application No. 157784 2 Name of the invention Field-effect transistor and its manufacturing method 3 Relationship with the case of the person making the amendment Patent applicant (307) Toshiba Corporation 4, Agent Kamata, Ota-ku, Tokyo 144 No. 4-41-11 - Tsunoda Building Benjo Patent Office Phone number 736-3558 5. Date of amendment order: July 11, 1980 (Delivery date: July 31, 1980) 6. Subject of amendment Meiwa 1 Column 7 for a brief explanation of the drawings in the book, contents of the amendment (1) I and Figure 8 in page 15, line 17 (line 4 from the last company) of the specification are deleted. (11) Page 15, line 19 of the specification (Sueshayo 1, line 2)
``Figure 7'' of the eye is changed to ``Figure 8'' (Second amendment 1-1).
Delete "Figure 2". Ovl Specification, page 16, line 3, 1- and 11
"Fig. 13" (2 corrections).

Claims (1)

[Scope of Claims] (1) At least one metal layer provided on one main surface of an n-type semiconductor, and a gate electrode whose connection with the p main surface is a metal layer forming a barrier with this semiconductor. a germanium layer deposited on the main surface so as to sandwich the gate electrode, and a metal layer connected to the main surface of the substrate at the gate electrode 4 on the exposed surface of the germanium layer. A field-effect transistor comprising at least one source and drain electrode layer with the same metal layer as a connection layer to the substrate. (2) forming an active layer on the main surface of a high resistivity semiconductor substrate; depositing a germanium thin film on the surface of the active layer; A process of forming an insulating pattern made of at least one layer thicker than the metal layer, and forming a first hole in the insulating film in the region where the gate is to be formed (later this insulating pattern). a step of etching the germanium thin M as an etching mask over a wider area than the opening; a step of providing a second opening in the insulating film opposite to the tenth opening; and a step of depositing an electrode metal layer. Method for manufacturing a field effect transistor (3) germanium thin film, comprising the step of applying patterning to form a gate electrode in a first opening and a source electrode and a drain electrode in a second opening, respectively. Claim 111, characterized in that the insulating end in contact with germanium is doped with an impurity that becomes a donor for germanium.
A method for manufacturing a field-effect transistor according to item 2. (4) The method for manufacturing a field effect transistor according to claim 2, wherein the atmosphere in the step of heat-treating the semiconductor substrate together with the germanium thin film is an atmosphere containing arsenic.