JPS605028B2 - Complex data processing unit/data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a composite data processing unit/data processing device;
Particularly, in a complex data processing unit/data processing device in which a plurality of microprocessors share and execute one overall process, each data processing unit is provided with a distributed schedule table, and at least one
Composite data processing unit data processing in which each healthy data processing unit executes the processing that it should execute based on the contents of the schedule unit when a failure occurs and/or when a failure occurs in one data processing unit. It is related to the device.

As so-called microprocessors have become widely used, composite data processing units and data processing apparatuses, in which a plurality of microprocessors are operated in parallel to execute one overall process, are being considered.

In such a data processing device, for example, one microprocessor #IMPU is used as shown in FIG.
executes processing system A related to data input, another microprocessor #Kitsunaka U executes arithmetic processing system B related to the input data, and yet another microprocessor #milk MPU executes processing system A related to data output. Processing system C is executed for each microf. . Sessa #I
The MPU to #3 MPU are configured to share and execute their respective processing systems. In such a data processing device, for example, if a failure occurs in the microprocessor #IM U that executes the processing system A related to data input, the microprocessor
Processing is performed only by processor #2MyenU and #milk MPU.

In this case, assuming that the microprocessor #IM Koyo Maruyama processing system A plays an important role in executing the overall processing, the entire data processing apparatus may go down depending on the case. For this reason, for example, it is desirable that the processing system A can be executed even if the processing system C, which is being executed by the illustrated microprocessor #Kitsunaka U, is temporarily interrupted.

When attempting to perform such system switching, a system management microprocessor is generally installed to perform the system switching as described above, but if the system management microprocessor has a failure If this occurs, the entire device will go down. The present invention
The purpose is to solve the above point, and the schedule table necessary for the above system switching is distributed and held in each microprocessor #IMPU or #ShoemisakiU (in the case shown in Fig. 1). Then, as shown in FIG. 1C, the processing system A
The purpose is to enable the execution of the following.

For this reason, the composite data processing unit/data processing device of the present invention is configured such that a plurality of data processing units are interconnected, a system file is created corresponding to each data processing unit, and a system file is created corresponding to each data processing unit. A system file corresponding to a processing unit is loaded with a processing system from a file common to the system, and the corresponding data processing unit executes the processing system individually, so that the entire processing including the individual processing systems is performed on the multiple units. The composite data processing unit/data processing device executed by the data processing unit includes a fault monitoring device that monitors the occurrence of individual faults in the data processing unit, and at least one The schedule table is configured to be distributed and maintained in each of the data processing units, which instructs the processing system to be separated and/or the processing system to be recovered at the time of failure recovery when a failure occurs in the data processing unit. , when a failure occurs and/or when a failure occurs in the at least one data processing unit, each healthy data processing unit indexes the contents of the schedule table and executes the processing system that it should execute based on the contents. It is characterized by This will be explained below with reference to the drawings. FIG. 2 is an explanatory diagram illustrating the schedule table used in the present invention, FIG. 3 is an explanatory diagram illustrating countermeasures taken by the data processing apparatus of the present invention when a failure occurs in one data processing unit, and FIG. 4 5 is an explanatory diagram illustrating countermeasures taken by the data processing apparatus of the present invention when one faulty data processing unit is restored, and FIG. 5 shows the configuration of an embodiment of the data processing apparatus of the present invention.

In the present invention, the second schedule table 1 is distributed and held in the microprocessors #IMPU to #KitsunakaU shown in FIG. 1A.

The schedule table 1 includes (i) information 2 that instructs which processing system (processing system C in the illustrated case) is to be disconnected in the event that one microprocessor fails in a normal operating state; (ii) ) Information 2-2 that instructs which processing system (processing system C in the illustrated case) is to be restored when the microprocessor is restored in an operational state where one microprocessor is down; Oii) 1 Information 2-3 and 0 that instructs which processing system (processing system B in the illustrated case) should be disconnected if one more microprocessor fails in an operating state where one microprocessor is down. Information 2-4 that instructs which processing system (processing system C in the illustrated case) is to be disconnected when one microprocessor is restored in an operating state where two microprocessors are down.
It is equipped with... FIG. 3 explains countermeasures when a failure occurs in one data processing unit (in the illustrated case, a microprocessor).

Reference numeral 1-i in the figure is a schedule table that is distributed and provided corresponding to each microprocessor, 3-i is a microprocessor, and 4-i is a fault monitoring device (hereinafter referred to as RACA). 5 represents a system MT file which stores each of the processing systems A, B, and C shown in FIG. Now the first
As explained with reference to Figure A, the microprocessor 3
Suppose that a failure occurs in -1.

The illustrated RACA 4-i is configured to issue a diagnostic signal to the corresponding microprocessor 3-i at, for example, one second intervals, and waits for example, 250 seconds before issuing a diagnostic signal to the corresponding microprocessor 3-i.
If there is no response from the processor 3-i, it is determined that the corresponding microprocessor 3-i is at fault (as shown in the figure).
). If the RACA4-1G detected the failure, the RA
The failure is notified to the CAs 4-2 and 4-3, and an interrupt is applied to each healthy microprocessor 3-2 and 3-3 (indicated by ■ in the figure). As a result, an inquiry about the cause of the failure is made (■ in the figure), and a response regarding the cause of the failure is made (■ in the figure).
However, in general, the response is often no response. The cause of the failure is notified to all microprocessors. (Illustrated ■). Schedule processing is activated in each healthy microprocessor 3-2 and 3-3 (indicated by ■ in the figure). At this time, when the microprocessor 3-3 refers to the schedule table 1-3 that is distributed and held within itself, it learns that the processing system C that it is processing should be separated, and the microprocessor 3-3 disconnects the processing system C. The process is interrupted (■ in the diagram). Microprocessor 3-3
is subsequently processed from system MT file 5 to system A.
is automatically loaded (■ in the figure), and thereafter the microprocessor 3-3 executes the processing system A (■ in the figure). FIG. 4 explains countermeasures to be taken when one faulty data processing unit (in the illustrated case, a microprocessor) is restored.

The symbols in the figure correspond to those in FIG. Assume now that the microprocessor that caused the failure in FIG. 3A has been recovered (indicated by ■' in the figure).

The recovery is notified from RACA 4-1 to each RACA 4-2, 4-3, and each microprocessor 3-2, 3-3
An interrupt is generated (■' in the diagram). As a result, the schedule table 1-1 is set for the microprocessor 3-1 as necessary, and the microprocessor 3-1 is notified that the current state is one microprocessor failure state (No. 2 in the figure). (Illustrated ■'). In this state, the scheduler processing is started in each of the microprocessors 31 which are in a healthy state (indicated by ■' in the figure). micro·
The processor 3-1 knows that the processing system C should be executed based on the contents of the schedule table 1 (■' in the figure), and automatically loads the processing system C from the system MT file 5 (■' in the figure). Thereafter, the microprocessor 3-1 executes the processing system C (
Diagram ■'). Further, if necessary, the other microprocessors 3-2 and 3-3 are notified via the RACAs 4-2 and 4-3 that the processing system C is ready to be executed. FIG. 5 shows the configuration of an embodiment of the data processing device of the present invention.

Reference numerals 1-i, 3-i, 4-i, and 5 in the figure correspond to FIGS. 7-i are system files respectively connected to the data bus 6-i and executed by the microprocessor 3-i. 8A, 8B, 8C, 8D, etc. are shared branch buses where programs are stored, and 9A is a check point bus for processing system A.
A file that stores the progress status as a check point in response to the progress of processing in processing system A;
10A represents a data file for processing system A. Further, 11-IA, 11-IB, . . . 11-30 . . . represent changeover switch means, and 12 represents an RAC sister section. As shown in FIG. 1A, it is assumed that each microprocessor is responsible for executing processing systems A, B, and C, respectively. In this case, the processing system A is loaded into the system file 7-1, the processing system B is loaded into the system file 7-2, and the processing system C is loaded into the system file 7-3 from the system MT file 5. is in a stored state. Further, the changeover switch means 11-1A, 11-2B, and 11-3C are turned on, respectively.
Microprocessor 3-1 is connected to files 9A and 10A via buses 6-1 and 8A, and similarly microprocessor 3-2 is connected to bus 8B and is connected to files 9A and 10A via buses 6-1 and 8A.
Processors 3-3 are connected to bus 8C.
And Mike. - The processor 3-1 proceeds with the processing based on the instructions stored in the system file 7-1, and the data during that time is stored in the data file 10A, and the progress of the processing is checked at a predetermined check point. Each time it arrives, it is saved to file 9A. The same applies to the microprocessors 3-2 and 3-3. Further, each of the RACAs 4-1 and 4-3 sends a diagnostic signal to the microprocessor 3-1 to 3-3 at an interval of, for example, one second to perform diagnosis, and receives at least one signal from the corresponding microprocessor. For example, it is checked whether there is a response within 250 seconds. Of course, the schedule tables 1-1, 1-2, 1-3 are distributed and maintained in the microprocessors 3-1, 3-2, 3-3, respectively (system files 7--, 7-2, 7-3). In this state, the micro
If RACA 4-1 detects a failure in processor 3-1, RACA 4-1 will communicate with other RACs via bus 12.
Notify A4-2 and 4-3.

This causes an interrupt to be applied to the microprocessors 3-2 and 3-3, as explained with reference to FIG.
If one of the microprocessors 3-1, 3-2, and 3-3 is designated as a temporary management processor, and the temporary management processor is the microprocessor 3-3, then The processor 3-3 is R
ACA 4-3 and bus 12 (RAC 4-1) determine the cause of the failure in the faulty microprocessor 3-1. Needless to say, the above temporary management processor is not fixedly assigned to a predetermined microprocessor, for example, 3-3, but is assigned to one of the healthy microprocessors as appropriate. In other words, if microprocessor 3-3 is currently assigned as a temporary management processor, microprocessor 3-3
If harm occurs to the other microprocessor rows, for example 3
It may be considered that the microprocessor 3-1 is in a down state, whereas the temporary management processor 3-3 corrects the cause of the failure. Generally, there will be no response.

The response state that corresponds to the interim cause of such a failure is
The RACA 4-3 also notifies the RACA 4-2 via the bus 12. Assuming that the microprocessor 3-1 is in the down state, based on the above notification, the scheduler processing is activated as described above in each of the microprocessors 3-2 and 3-3 that are in the healthy state.

That is, the microprocessors 3-2 and 3-3 have self-distributed schedule tables 1-2 and 1-3, respectively.
Based on the contents of the above, an operation is performed to deal with the down state of the microprocessor 3-1 running the processing system A. In the setting example, since the schedule table indicates that the processing system C is to be disconnected, the microprocessor 3-3 is disconnected from the processing system C.
Know when to interrupt processing. As a result, the microprocessor 3-3 sets, for example, the processing progress status of the processing system C in a check point file 9C (not shown) (corresponding to 9A shown in the figure), and then turns off the changeover switch means 11-3C. . Then, the changeover switch means 11-3D is turned on, the processing system A is loaded from the system MT file 5 onto the system file 7-3, and the changeover switch means 11-3D is turned off. Next, the microprocessor 3-3 turns off the changeover switch means 11-IA and turns on the changeover switch means 11-3A, for example.

Then, the microprocessor 3-3 takes the contents of the check point file 9A for the processing system A and transfers the processing of the processing system A to the microprocessor 3-3.
Perform recovery processing to return to before the failure occurred in -1,
The processing of processing system A is restarted from that state. The operation when the faulty microprocessor 3-1 is restored is as follows.
The recovered microprocessor 3-1 loads the processing system C onto the system file 7-1 and switches the changeover switch means 11-
Turn on the IC, perform the recovery process for the processing system C that was previously interrupted due to the contents of the check point file 9C (not shown) for the processing system C,
Restart processing system C.

As explained above, according to the present invention, the schedule table 1-i is distributed and held in each microprocessor 3-i. It becomes possible for the microprocessor to independently determine the processing it should perform and to perform the processing in the most preferable manner overall.

In this case, any one microprocessor in a healthy state may act as a temporary management processor, but even if a failure occurs in the microprocessor serving as the temporary management processor, the temporary management processor Management. . The role of setter is delegated to a healthy microprocessor, so there is no problem at all. In the case shown in FIG. 5, each RACA 4-i is configured to perform fault monitoring, but each RACA 4-j is configured by a hardware circuit, and the circuit configuration is simplified as much as possible. Care is taken to ensure that -i itself does not experience any trouble. Furthermore, in the case shown in Figure 5, file 9A
If the IQA is one shared branch data data bus, e.g.
A, but consideration should be given to connecting to two or more shared branch data buses as necessary.
Alternatively, consideration may be given to multiplexing the files 9A and 10A themselves.

[Brief explanation of the drawing]

Figures 1A, B, and C are explanatory diagrams for explaining the prerequisite problems of the present invention, Figure 2 is an explanatory diagram for explaining the schedule table used in the present invention, and Figure 3 is an explanatory diagram for explaining the problem in one data processing unit. FIG. 4 is an explanatory diagram illustrating the countermeasures taken by the data processing device of the present invention in the case where one faulty data processing unit is restored. 1 shows the configuration of an embodiment of a data processing device of the present invention. In the figure, 1 is a schedule table, 3 is a data processing unit, 4 is a fault monitoring device, 5 is a system MT file, 6 is a unit corresponding data bus, 7 is a system file, 8 is a shared branch bus, and 9 is a check・Point file, 10 is a data file, 11 is a changeover switch means, and 12 is a bus. 2 illustrations of spears, 4 illustrations of spears, 5 illustrations

Claims (1)

[Scope of Claims] 1 A plurality of data processing units are interconnected and a system file is created corresponding to each data processing unit, and the system file corresponding to each of the above data processing units is A processing system is loaded from a file common to the system, and the corresponding data processing unit executes the processing system individually, so that the overall processing including the individual processing systems is executed by the plurality of data processing units. The composite data processing unit/data processing apparatus includes a fault monitoring device that monitors the occurrence of individual faults in the data processing units, and also includes a fault monitoring device that monitors the occurrence of faults in at least one data processing unit when performing the above overall processing. , a schedule table indicating a processing system to be separated and/or a processing system to be restored at the time of failure recovery is configured to be held distributed among the data processing units, and the at least one of the above
When a failure occurs and/or when a failure occurs in one data processing unit, each healthy data processing unit indexes the contents of the schedule table and executes the processing system that it should execute based on the contents. Features: Composite data processing unit/data processing device. 2. Each of the data processing units has its own unit-compatible data bus and is switched to one or more shared branch data buses that intersect with each of the plurality of unit-compatible data buses. The healthy data processing unit utilizes the contents of the files connected to the shared branch data bus in executing a new processing system. A composite data processing unit/data processing apparatus according to claim 1, characterized in that: 3 A fault monitoring device is provided corresponding to each of the data processing units, and the fault monitoring device is configured to monitor a fault in the data processing unit corresponding to itself, and the fault monitoring device that has detected the fault is configured to Claim 1, characterized in that the occurrence of a failure is notified to a failure monitoring device of
The composite data processing unit/data processing device according to item 1 or 2.