JPS604998B2 - audio output device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audio output device that utters various messages such as warning messages and hourly messages using sounds such as human voices and melodies, and its first purpose is to The purpose is to provide a highly versatile voice output device that can utter a wide variety of messages and can handle even if the input signal is parallel data or serial data. An object of the present invention is to provide an audio output device with low average power consumption by supplying power as needed.

Examples will be described below using figures. FIG. 1 is a block diagram showing signal processing according to an embodiment of the present invention, where the input signal D for selecting a message is a fire detection signal, a visitor detection signal,
The input signal D is a signal such as an hourly signal of a clock, and the input signal D is a mode switching signal M input via the operation mode switching circuit 30.
is input to the logic unit 32 along with
A sequence program for concatenating message elements that are arithmetic-processed in the logic unit 32 and constitute a message is executed in the logic unit 3.
Output from 2. This sequence program is input to the editing section 33, and message element selection signals (address signals of the parameter memory section 34) are sequentially output based on the sequence program from the editing section 33. This selection signal is input as address data to the parameter memory section 34 which stores the characteristic parameters of the audio waveform of each message element, and the characteristic parameters of the message elements constituting the message are sequentially output from the parameter memory section 34. The feature parameters read from the parameter memory section 34 are input to the speech synthesis section 35, and the message F consisting of a synthesized sound based on the features outside the feature parameters is outputted from the speech synthesis section 35. (Table 1) is an example of mode setting, and seven working modes can be selected by mode switching signals T, , M, , M2.
The code is set accordingly. (Table 1) Figures 2a and 2b are block circuit diagrams showing the configuration of the embodiment. Although the actual circuit has complicated interconnections and cannot be clearly divided into blocks, the schematic configuration is divided into blocks. This is what is shown.

Reference numeral 1 designates a selector circuit controlled by a mode signal m, which inputs input signals D, to D4 (shown as 4 bits in the embodiment, but is not limited to this) and selects the mode output from the mode decoding circuit 2. The signal m is selectively input to the input latch circuit 3 and the pulse conversion circuit 4.

These circuits 1, 3, and 4 constitute an input matching circuit 31, and even if the input signal D is serial data or parallel data, it is converted into a predetermined control signal (a signal that can be logically processed by the logic section 32). It is supposed to be done. An operation mode switching circuit 301 consisting of a mode decoding circuit 2 controls the selector circuit 1 and also controls other circuits according to the operation mode (purpose of use). 9 is a test circuit.

5 is a trigger circuit, which generates a trigger pulse (TRG) when a certain condition determined by the combination and order of the mode switching signal M and the input signal D is satisfied, and starts the voice synthesis operation.

6 is a sequence timing circuit, 7 is a secondary circuit, and 8 is an enable circuit, and the operation control signals (ENABLE) (STOP) ( READY), the logic unit 32 and the voice synthesis unit 35 are connected for handshaking (described later), and power is supplied to the voice synthesis unit 35 using an operation control signal, that is, an enable signal (ENAB).
It is controlled by LE).

10 is a sequence initialization circuit, 11 is an address latch counter, 12 is a sequence ROM, 27 is an end circuit, and these circuits 6, 10, 11, 12,
At step 27, a sequence program is formed that connects the words of the message and the syllables of the melody.

13 is a general-purpose counter that counts serial data.

By the way, the above-mentioned sequence ROM 12 stores sequence programs for editing messages (10 words of melody) according to various uses. A sequence program to be executed is stored. (
Table 2) Reference numeral 14 denotes an editing circuit which outputs a message element selection signal h based on the sequence program outputted from the sequence ROM 12 and the count signal (CO) outputted from the general-purpose counter 13.

15 is a latch circuit, and 16 is an address decode ROM.

18 is a compression parameter ROM that compresses and stores characteristic parameters of the audio waveform of each message element; Compressed characteristic parameters (hereinafter referred to as compression parameters) 1 applied as data and read out from the compression parameter ROM 18 are converted from parallel data to serial data (DAT) by a pulse counter 19 and a parallel-to-serial conversion circuit 2. Ru.

The serial compression parameters (DAT) output as serial data (DAT) from the parameter memory section 34 in this manner are input to the speech synthesis section 35. The speech synthesis unit 35 synthesizes speech based on serial compression parameters (DAT).Synthesizing methods include PARCOR method (described later), LPC method, etc.
A waveform synthesis circuit 24 consisting of M and a waveform synthesis filter, a parameter regeneration circuit 21, a synthesis control circuit 22, a timing clock circuit 23, an increase circuit 25, and a speaker 26.
Power is supplied only when the enable signal (ENABLE) is input from the enable circuit 8, and the circuit becomes operable and outputs the timing signal t of the frame signal. Further, only when a ready signal (READY) is input, a quest signal (REQ) is outputted in order to input a compression parameter. Note that both the serial compression parameter (DAT) and the IJ quest signal (REQ) are 1-bit pulse signal sequences. In the compression parameter ROM 18 of the parameter memory unit 34 described above, compression parameters of message elements (parameter units consisting of compression parameters of a plurality of frames in the embodiment) are stored in respective predetermined parameter storage areas, and the start address of the parameter storage area is address decode ROM1
6, the compression parameters of each message element are read out sequentially as 1-bit serial data (DAT) in response to a request signal (REQ).

Note that the sequence ROM 12 and the address decode ROM 16 for editing are formed of mask ROMs, and by converting the mask, a versatile audio output device that can be used for various purposes can be formed. By the way, in the embodiment, the PARCOR (partial autocorrelation) method is used for speech synthesis, and the PARCOR method will be explained below.

This method divides the audio waveform into frames of 5 to 20 mSeC on the time axis, treats each frame as a stochastic stationary process, and extracts it using a partial autocorrelation coefficient, that is, a lattice-type multistage filter. The number of K-parameters equal to the number of filter stages obtained by
N, P), find the sound source power (PWR), store or transmit the K parameter and the sound source parameter as voice feature parameters ~ Synthesize the voice by filling in the feature parameters in the reverse process of the above-mentioned feature parameter extraction process. Simple melodies can be synthesized. In addition to these characteristic parameters, bit compression is performed by taking into consideration the quantization method and line return in each frame. In the PARCOR method, audio is recorded for 5 to 20 seconds.
The compression parameters are determined for each frame.The shorter the frame, the better the sound quality, but at the cost of an increase in the number of bits. In the embodiment, a frame signal (FRL) is included in the signal x inputted from the address decode ROM 16 to the synthesis control circuit 22 so that the compression parameters of the fractional frames constituting a word or syllable, that is, the frame can be changed for each parameter unit. Includes. In addition, a sound source switching signal (M
/F) was included in the above signal ×. In the case of a melody, the melody signal (MS) may be similarly included in the signal x and the sound source ROM may be switched to the melody, but a female sound source may also be used instead. In the embodiment, the timing signal t in FIG. 2 is composed of a frame signal (FRM), which is a pulse having the frame period, and a subframe signal (ST), which does not change depending on the frame period.

The period of the frame signal (FRM) is 10 seconds or 20 seconds, and the period of the subframe signal (ST) is 2 seconds.
．． 5 seconds. The above-mentioned speech synthesis section 36 interpolates K-parameters in subframe signal (ST) units to smoothly synthesize speech, resulting in good sound quality.

The operation of the embodiment will be specifically explained below.

The operation mode is set by the mode switching signal T,,M,,,, and the mode signal m consists of seven signal sources in the case of (Table 1), and in the case of chime, CH=day. . By selecting the mode signal m, the logic gates of each circuit are selected, and a circuit network is constructed that performs a logic operation suitable for the mode. The sequence ROM 12, the address decode ROM 16, the compression parameter ROM 18, and the sound source ROMs (multiple) built into the waveform synthesis circuit 24 are composed of mask ROMs, in which contents suitable for the purpose of use (operation mode) are written, and as necessary. Specifications can be easily changed as required. Figures 3 and 4 show the flow of operations suitable for each normal mode with T, =L, and when input signals D, ~D4 are input, the order and combination of input signals D, When the conditions for outputting audio are established, a trigger pulse (TRG) is output from the trigger circuit 5 and an enable signal (ENABLE) is output from the enable circuit 8.
) is output to the voice synthesis section 35 (becomes an inactive bell), and in response, the timing signal t is output from the voice synthesis section 35, the sequence timing circuit 6 operates, and the sequence initialization circuit 10 is working (
Data is output to the address counter 11 so that the editing sequence starts from the initial of the route according to the input as shown in Table 2), and the process proceeds to loading the address counter 11 and accessing the sequence ROM 12.
If the contents of 2 do not indicate "END", the editing circuit 14
At , the output C of the input latch 3, the output (CO) of the general-purpose counter 3, and the edit address data of the sequence ROM 12 are selected or edited by the edit control data of the sequence ROM 12.

This editing output is latch 15, address decode ROM 1
6 to the start address (referred to as a unit address) of the parameter unit of the compression parameter ROM 18 in which the audio compression parameters are stored, and preset it in the address latch counter 17. This unit address is decoded by the address decode ROM 16 to the length of the address in the compression parameter ROM 18 in bits. This work is performed at sequence timing TM2.
The latch 15 latches the output of the editing circuit 14 and accesses the address decode ROM 16. At sequence timing TM3, the pulse counter 19 is cleared and the address latch counter 17 is preset, and the compression parameter ROM 18 is set to the above-mentioned start address. When prepared to be read from (unit address),
A ready signal (READY) is output (turned on) from the ready circuit 7. The voice synthesis unit 35 outputs a request pulse (REQ) and performs a shift operation between two parallel-to-serial conversion circuits, and the pulse counter 19 outputs a pulse that counts up the address latch counter 17 and loads the parallel-to-serial conversion circuit 20. (CP).

In this way, the compression parameters are read out sequentially starting from the unit address. The compression parameter (DAT) output in 1-bit serial form from the parallel-to-serial conversion circuit 20 is reproduced by the parameter reproduction circuit 21 and converted into data with a bit length before compression. The K-parameters and other sound source parameters obtained by processing this data are sent to the waveform synthesis circuit 24, and the built-in sound source ROM of the waveform synthesis circuit 24 is accessed to generate a sound source waveform to be input to the filter. The waveform synthesis circuit 24 synthesizes an audio waveform by passing the sound source waveform through a dynamic filter controlled by the K-parameter, and outputs it through the amplifier circuit 25 and the speaker 26.
When audio is synthesized by reading parameter units one after another, the end operation of the audio parameter unit to be synthesized in one sequence step is to send the stop code of the compression parameter (DAT) to the parameter reproduction circuit 21.
The synthesis control circuit 22 generates a stop pulse (ST
The ready circuit 7 outputs the ready signal (REA).
This is completed by turning off DY). The stop pulse (STOP) is generated by the sequence timing circuit 6, which outputs an increment signal (WC) to increment the count of the address latch counter 11 in the case of the once-voice mode, thereby advancing the sequence.

A silent section signal (
After a pause time (mT), a ready signal (READY) is output from the ready circuit 7, and the above synthesis process is repeated.

On the other hand, the sequence initialization circuit 10 has two modes: a one-shot mode such as "melody + word" in which synthesis is performed once at each sequence step after an input signal is input, and a one-shot mode in which synthesis is performed once at each sequence step, and a repeat synthesis mode that remains in one sequence step. Input signals D, ~D in a continuous voice mode (continues until the input is cut off) such as ``melody + word repetition 1''
There is a function to select and set according to 4 bit patterns.
The voicing mode signal (SC) is sent to the sequence timing circuit 6.
send to

In the latter case, this is realized by controlling the count-up operation of the address latch counter 11 according to the bit pattern of the input signal so that when the stop pulse (STOP) is repeatedly input, a sequence like ``word repetition 1'' is performed. After execution in the single voice mode or continuous voice mode, the end code is output from the sequence ROM 12 and the sequence timing TM2 is terminated.
When the end signal (END) is output from the end circuit 27,
is output to the enable circuit 8 as an enable signal (EN
ABLE) is turned off.

In the continuous voice mode, the sequence timing circuit 6 does not output an increment signal (river C) even if a stop signal (STOP) is input.

As described above, the control section consisting of the logic section 32 and the editing section 33 and the speech synthesis section 35 receive the enable signal (ENABLE),
Handshaking is performed using the timing signal t, ready signal (READY), and stop signal (STOP), and the control section edits message elements and controls the sequence in response to input signals D, ~D4, and performs voice synthesis. The unit 35 is arranged to synthesize speech based on the feature parameters of the message elements read out from the parameter memory 34.

Further, the sequence initialization circuit 10, general-purpose counter 3, editing circuit 14, and sequence ROM 12 provide diversity in editing of combinations and connections of message elements such as syllables and words. Parameter memory section 3
4, the pulse counter 19 and the parallel-to-serial conversion circuit 20 convert the compression parameter (DAT) into 1-bit serial data.
The compression parameter ROM 18 is accessed by a 1-bit request signal (REQ), and a normal 8-bit word length ROM can be used as the compression parameter ROM 18. Note that the configuration of the speech synthesis unit 35 may be various depending on the speech synthesis method such as the PARCOR method or the LPC method or the parameter compression method, but this application is not limited to these methods, and the speech synthesis method may be any method. However, if the above-mentioned handshake operation can be performed, that is, if it is unified, the control section, parameter memory section 34, and speech synthesis section 35 are configured with two or three independent chips, and the enapple signal (
ENABLE) is off, power to the parameter memory section 34 and speech synthesis section 35 can be turned off to save power consumption, and furthermore, compatibility with speech synthesis LSI chips with different speech synthesis methods can be obtained. .

Furthermore, if the synthesis control method (male, female, child, frame period, etc.) is different for each parameter unit,
These control signals X can be outputted from the address decode ROM 16 and transmitted to the synthesis control circuit 22 via the editing circuit 4. On the other hand, the input signal D may be either serial input (pulse signal) or parallel input (digital signal), and has an operation mode compatible with both signals.

That is, when the serial input mode is used in a clock as shown in Table 1, the input pulses are counted by the general-purpose counter 3 and synthesized according to the number of pulses. In parallel input mode, synthesis is performed according to the bit pattern of the input signal, like a chime. Application examples of the audio output device according to the present invention will be described below.

Note that the detailed operation of the audio output device has been described above, so a detailed explanation thereof will be omitted. FIG. 5 shows a connection example when implementing a clock striking device, where the input signal D is the timing signal for issuing the time signal, that is, the hour signal, and the input signal D2 is the notification time and the general-purpose counter 13. This is a time adjustment signal that matches the count number, SW, , SW2 are switches, and 36 is an oscillator.

When the time setting signal is input, the general-purpose counter 13 starts from zero and counts up while synthesizing the sound of "beep" every second.For example, if it is now 5:15, it will say "beep" five times. If the time setting is aborted at that time, the 6 o'clock time signal will be made the next time the hour signal is obtained, allowing the time setting of the time setting device. The time signal includes melodies (ping pong, etc.) and words (from now to 00 o'clock...
etc.) has been edited.

Fig. 6 shows an example of application to a self-aware clock, in which the input signal D2 input to the audio output device (SY) is a self-aware set signal for reserving a self-aware operation, and when set, it says "W good night," It responds by saying, notifying you that the set is complete.

Next, it becomes aware of the input signal D, and when the ON signal is input, it becomes aware and starts the operation, and continuously utters "Good morning, good morning".Here, if the snooze signal is input as the input signal D3, the snooze signal is input. It stops speaking while the signal is being input (about 5 minutes), and responds by continuously saying, "It's time for a longer time than when the snooze signal was turned off." Furthermore, a snooze signal is input, and after a pause period, the snooze signal is cut off, and the robot continuously utters "I'm sorry.".The awareness movement is stopped when the awareness set signal is cut off, and the sequence of the awareness movement is reset. SW3 is a snooze switch, and SW4 is a switch for switching between adult and child messages.
"I'll be late" message can be changed sequentially by writing the sequence of each message in the step of the sequence ROM 12, counting up the general-purpose counter 13, and transferring this count result to the address decode ROM.
There is a method of outputting to 16. FIG. 7 shows an example of application to an alarm chime, in which digital signals D, -D4 corresponding to the signal with the highest priority are output to the output of the alarm encoder 37 among alarm inputs A, ~A, and 5. At the same time, a pulse (RO) indicating a change in the input is output.

For example, if only input A7 is input, the response will continue until the input is cut off, such as "Pororon" ke rain desu "ke rain desu" (continuous vocalization), but before input A7 is cut off, the input with a higher priority will be input. When A3 is input, alarm reset pulse (AR)
The above pulse (RO) is input as above, resets the sequence, and "bleep" Gas leakage Gas leakage...
・Perform the following actions (continuous vocalization). Figure 8 shows an example of an application that performs a complex mode operation such as a chime, a clock, and an awareness.Inputs generated from the clock 38 such as a clock, an awareness time, an hour signal, an awareness on signal, etc., and a time adjustment. , inputs from switch 39 such as self-aware set and snooze, and rain,
Inputs from sensor inputs 40 such as gas leaks and input devices 41 such as interphones are input via an input/output boat 42.
When input to the microcomputer 43, the software (program) of the microcomputer 43 outputs mode inputs M, , M2, T, and data inputs D, , D2, D3, of the audio output device (SY) via the output port 44. D4
, (AR) to obtain the desired audio response according to the input and priority. Types of input information include alarm, awareness,
A chime (interphone), a striking clock, and the following:
The editing work for each input will be explained.

First, if the input information is alarm data, the sensor 40→
Input/output port 42 → Microcomputer 43 → Output port 44 (mode "input data setting") → Sequence initial 1 → Sequence 1 (at normal speaking speed,
Output the edit address, that is, the output data of the sequence ROM to the address decode ROM 16) → "People"
Synthesis of r → Sequence increment (increase the value of address latch counter 11 by 11) → Sequence 2 (Edit address at fast speed Address decode ROM
161 outputs) -> Response to "busy foliage information"-> Sequence increment -> Sequence 3 (outputs the input port output and edited data to the address decode ROM 16 at fast speed) -> Response to "Gas leak" (input utter the words in succession or once) → Sensor 4
0 input release → sequence increment → sequence 4
(Address decode ROM1 for editing address in normal mode)
Editing is performed in the order of ``output to 6) → response of ``released'' → sequence increment → end code output.Next, if the input information is recognized and is data, it is recognized and input 38 → input/output boat 42 → Microcomputer 43 → Output board 44 (mode, input data setting) → Sequence initial 2 → Sequence 1 (address decode RO for editing address at normal speaking speed)
Output to M16)→Response of "picopico"→Sequence increment→Sequence 2 (Normal, aware of general-purpose counter 13 and address decodes the contents of the counter R
The editing work is performed in the following order: Output to OM16)→Response such as "It's time"→Recognize and turn off input→Sequence increment→Sequence 3→End code output.

Note that in sequence 2, the next response changes depending on the editing content. Next, if the input information is visitor detection data such as a chime or an intercom, the switch 39 or sensor 40, input device 41 → input/output board 42 → microcomputer 43 → output board 44 (mode, input setting) → sequence Initial 3 → Sequence 1 → Response of “I Ping Pong” → Sequence 2 (slow vocal speed,
Address decodes input boat contents and edited data RO
Editing work is performed in the order of output to M16) → response of "I'm sorry, please wait for a while" → sequence 3 (end code output), and for other inputs, the sequence is Thank you very much for your reply after 2.
,,Please respond to the customer.

Next, when the input information is the hour data of the hourly clock, the clock 38, switch 39, sensor (illuminance, etc.) 40 → input/output boat 42 → microcomputer 43 → output boat 4
4 (Mode, input settings) → Sequence initial 4 →
Sequence 1→Response of ``Pyo Pyo''→Sequence 2→Response of ``The next time signal is''→Sequence 3 (Normal and address decode ROM1 according to the contents of the clock counter of the general-purpose counter and the contents of the sequence data of the sequence ROM.
The editing work is performed in the following order: Access 6) ->It's 3 o'clock" response -> Sequence 4 ->"Ping Pong Burn" response (notify the hour with a burn) -> Sequence 5 (end code output). In the composite mode, the general-purpose counter 13 incorporates a counter for clock use and a counter for awareness, and the mode signal m is configured to switch the count up signal (CUP) or reset signal between clock use and awareness use. It can be used for various purposes.

Edit circuit 14 output to address decode ROM 16
Since the number of address bits in the address decode ROM 16 corresponds to the number of parameter units, the output is a combination of the output data (edit control, edit address) of the sequence ROM 12, the general-purpose counter 13, and the output of the input board 42. Even in short sequences, there are many types (
parameter unit) voice response is obtained.

The present invention is configured as described above, and a sequence program for connecting message elements is formed by a combination of an input signal for selecting a message and a mode switching signal, so that a variety of messages can be uttered, and the mode switching signal Since it is equipped with an input matching section that converts input signals into predetermined control signals, even if the input signal is parallel data or serial data, it can be handled without using an interface circuit, and can be used in alarm mode, hourly mode, etc. It has the advantage of being able to provide a highly versatile audio output device that operates in multiple modes.
Furthermore, the power supply to the speech synthesis section is controlled by the operation control signal of the speech synthesis section output from the logic section, and the sequence program is output, so that the speech synthesis section can synthesize speech only when it is necessary to operate. Since power is supplied to all parts, it has the advantage of reducing average power consumption.

In addition, since the PACOR method is used as the speech synthesis method in this embodiment, the number of bits for the feature parameters of the audio waveform of each message element can be reduced, and the number of message elements that can be stored in the parameter memory section can be increased. This allows a wider variety of messages to be uttered.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing signal processing according to an embodiment of the present invention;
Figure 2a is a block circuit diagram of the same as above, Figure 2b is a main block circuit diagram of the same as above, Figure 3 is a flow chart of same as above, Figure 4 is a time chart of same as above, Figures 5 to 8 are respectively FIG. 9 is a block circuit diagram illustrating an application example similar to the above. FIG. 9 is a diagram showing a memory example of a sequence ROM and peripheral circuits of the application example shown in FIG. 8. 31 is an input matching circuit, 32 is a logic section, 33 is an editing section, 3
4 is a parameter memory section, and 35 is a speech synthesis section. Figure 1 Figure 2 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1. An input signal for selecting a message and an alarm mode;
A mode selection signal for switching an operation mode such as a time mode is input, and outputs from a logic section that forms a sequence program for concatenating message elements such as words and syllables of a melody based on the input signal and the mode selection signal. an editing section that sequentially outputs selection signals of message elements according to a sequence program to be executed; a parameter memory section that stores characteristic parameters of the audio waveform of each message element; and a characteristic parameter that is read out from the parameter memory in response to the selection signal. A voice output device comprising a voice synthesis section for uttering a message that synthesizes voice based on. 2. The audio output device according to claim 1, further comprising an input matching section that converts an input signal into a predetermined control signal using a mode switching signal. 3. A patent claim characterized in that power supply to the speech synthesis section is controlled by the operation control signal of the speech synthesis section output from the logic section, and power is supplied to the speech synthesis section only when a sequence program is output. The audio output device according to item 1.