JPS6047611B2 - Microprogram control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called dynamic microprogram control system that enables microprograms to be dynamically opened to users online in a data processing apparatus that performs microprogram control.

Conventionally, control memories used in data processing devices for on-line systems, especially highly online systems such as electronic exchanges, have mostly been read-only control memories.

(1) dynamic microprograms; (2) subroutines of microprograms with parameters; (3)
Functions such as complete microprogramming of diagnosis, (4) efficient firmware implementation, and (5) economical debugging (error removal) of microprograms become impossible. The main reason why writable control memory is not used as control memory in an online system is that as a result of opening the microprogram to users in (1) to (4) above, if there is a bug (error) in the microprogram, the system This is because there is a high possibility that the device will go down, that is, the entire device function will be destroyed. In the case of a read-only control memory, when debugging a microprogram (error removal), it is necessary to separately prepare a writable control memory and storage therein.

The purpose of this invention is to provide a microprogram control method that monitors control by a microprogram stored in a writable control memory and forcibly returns to microprogram control by a read-only control memory in the event of an abnormality, thereby preventing a system down. It is about providing.

Another object of the present invention is to provide a microprogram control system that can perform more reliable control using both a read-only control memory microprogram and a writable control memory microprogram.

Still another object of the present invention is to provide a microprogram control system that enables subroutines with parameters and efficient firmware creation by dynamically writing data into a writable control memory. Still another object of the present invention is to provide a microprogram control system that allows diagnosis to be performed entirely by microprograms by overwriting a large amount of diagnostic programs and their data from main memory to writable control memory. It's about doing.

Yet another object of this invention is a writable control record! To provide a microprogram control system which has a built-in microprogram and can debug the microprogram without using another tester by forcibly changing the address register of the microprogram.

5. A read-only control memory that stores microprograms in a data processing device that performs microprogram control, a writable control memory that can be written from a buffer register that stores data from the main memory, and a control that controls the writing. By having the circuit 4, it is possible to freely write data from the main memory to any address in the writable control memory. It has a selection circuit that inputs either the microprogram read from the read-only control memory or the writable control memory into the microprogram instruction register, and further inputs the microprogram from the read-only control memory to the writable control memory and vice versa. The control circuit that transfers control of the program allows both control memories to be used freely. In this invention, counting can be started and reset can be specified only from a microprogram in a read-only control memory, and a counting circuit is provided that performs a counting operation while performing remicroprogram control using a writable control memory. Writing is possible by having a control circuit that forcibly returns control from the writable control memory to the microprogram at a specific address in the read-only control memory when the counting circuit overflows, and a circuit that notifies the program of an abnormality. Even if the microprogram in the control memory goes out of control, it will always be possible to return to normal.

Furthermore, by having a circuit that externally forcibly sets the most significant bit of the microprogram address register that is common to both read-only control memory and writable control memory, all can be written when debugging the microprogram. It is now possible to move all microprograms to a separate control memory for debugging. Next, an embodiment of the microprogram control system according to the present invention will be described with reference to the drawings.

Before going into detailed explanation, the order of explanation is as follows. (1) Detailed explanation of the invention (2) Control memory writable from the main memory (hereinafter referred to as WC)
Explanation of writing control to (denoted as M).

(3) Explanation of control when passing control from a microprogram in a read-only control memory ROM to a microprogram in a writable control memory. (4) Description of control when passing control from a microprogram with writable control memory to a microprogram with read-only control memory.

(5) Explanation of the WCM microprogram monitoring mechanism when control is passed from the ROM microprogram to the WCM microprogram.

(6) Finally, explanation of a method for debugging a ROM microprogram using a WCM The following will be assumed in the detailed explanation of the invention, but the generality is not lost thereby.

One processing device is a 16-bit word machine.

2 The microprogram width is 32 bits.

The capacity of 3R0M is 1KW, and the capacity of WCM is also 1KW.

(1) Overall configuration of this invention As shown in FIG. 1, data read from main memory 1 is 1
The buffer register 2 is connected to the buffer register 2 through the six data lines 1a.
The instructions stored in and read out are stored in the instruction register 3 through 16 data lines 1b.

Constant register 4 contains a constant.
The instruction register 3 and the constant register 4 are connected to an address determining circuit 6 through one data line 3a and 4a, respectively, and this address determining circuit 6 is connected to the ROM and W.
An address is given to the control memory 7 composed of both CMs through the data line 6a. The buffer register 2 is also connected to the control memory 7 through 16 data lines that provide write data. The address determining circuit 6 is a ROM, W
It is connected to a control memory 7 through a signal line 6b for controlling CM switching. Microprogram instructions read from control memory 7 are supplied to microcontrol circuit 8 through three data lines 7a.

The micro control circuit 8 and the address determining circuit 6 are connected by one data line 8a for giving the next micro program address or WCM write address, its selection signal line 8d, and an address+1 designation signal line 8e. WCM
A monitoring circuit 5 including a counting circuit for monitoring the operation of the microprogram of the WCM is provided.
It is connected to the micro control circuit 8 by a counting start signal line 8c and a reset signal line 8b of a counting circuit for microprogram monitoring. An external operation key 9 is connected to the address determination circuit 6 through a signal line 9a that determines the most significant bit of the address. (2) WCM from main memory
As shown in FIG. 2, the address determining circuit 6 includes a control storage address register selector 61 and an address register 6.
2, +1 circuit 66, WCM address register 6, selector 63 of address register 64, and +1 circuit 67.

Selector 61 and address register 62 are connected to address line 6
1a and is connected through an address line 66a to which the contents of the address register 62 are given an address incremented by +1 by a +1 circuit 66. The selector 63 and the address register 64 are connected to each other through an address line 63a for writing data in the WCM.
They are connected through address lines 67a to which an address incremented by 1 by an 11 circuit 67 is given to the contents of 4. The inside of the control memory 7 is ROM72, WCM73, ROM
72 and a selection circuit 74 of WCM 73.

The address register 62 and the ROM 72 are connected by the CM address line 6a, and the ROM 72 and the selection circuit 74 are connected to the ROM
are connected by a microprogram data line 72a. The address register 64 and the WCM 73 are connected through an address line 64a for writing data to the WCM. The inside of the micro control circuit 8 is composed of a micro program instruction register 81, which is connected to the address register 61 by a +1 designation line 8d, and connected to the address register 63 by a WCM write address line 8a and a +1 designation line 81.
a, respectively.

Furthermore, the microprogram instruction register 81 and WCM7
3 are connected by a WCM write designation line 82b. Normally, when data is written from the main memory 1 to the WCM 73, an instruction consisting of an instruction code f1 for specifying WCM writing and an address D2 of the WCM to which data is to be written is entered into the instruction register 3, as shown in FIG. , its instruction code f
The 4 bits of 1 are decoded, become 12 bits, and enter the address register 62 through the address line 3a.

At this time, the most significant bit of the anode address register 62 is naturally 0.
ROM72 is selected. The microprogram at the designated address in the ROM 72 is read out to the microprogram instruction register 81 through the selection circuit 74.
First of all, the WC indicated by RO (not shown in the figure)
Assume that the address of main memory 1 to be written to M73 has already been read to buffer register 2. The microprogram after that operation is stored at 30 in the microinstruction register 81.
The bit is set to 1, and the next ROM address is the address of the current microprogram plus 1, which is selected by the selector 61 and entered into the address register 62 by the +1 designation line 8d. Also, 1 is set in the 12th bit, and the lower 2 bits D2 of the instruction register 3 are +1 designation line 81.
a is selected by the selector 63 and the address register 6
It is stored in 4. Furthermore, main memory 1 that has already been read at this time
In order to write the contents from the buffer register 2 to the WCM 73, 1 is set to the 13th bit of the microinstruction register 81, and writing is designated to the WCM 73 by the transfer designation line 82b. These 12th, 13th .
When all the 30th bits are complete, the 16 bits of data read from the main memory 1 are written into the left half word of the 32 bits of the designated address portion of the WCM 73. Similarly, the contents of the main memory 1 are then read out to the buffer register 2 and written into the 32-bit right half word of the WCM 73.

At this time, the 12th bit of the microprogram instruction in the register 81 is set to 1 to select the WCM address mountain in the instruction register 3. That is, select the same WCM address as the previous one. This control of writing in the left half word and the right half word is possible using the conventional method. Next, subtract 1 from the number of words R1 to be written to the WCM73, and then transfer the data read from the main memory 1 to the next WCM73 address in the buffer register 2.
Write to the left half word of WCM73. The microprogram specification at this time is 0 for the 12th bit and 1 for the 13th bit.
When set to , the address of WCM73 plus 1 is entered into address register 64 by selector 63,
Write the contents of buffer register 2 to WCM73. 13
When the bit is O, writing to the WCM73 is not possible. Thereafter, the contents of the main memory 1 are sequentially written into the WCM 73 under the control of the ROM microprogram in the same manner.
(3) Jump RO from ROM control to WCM control
FIG. 4 shows the control configuration when passing control from the M72 microprogram to the WCM73 microprogram.

In FIG. 4, a 12-bit ROM address line 4a from the constant register 4 connected to the selector 61 in the address determination circuit 6 is newly added to the one shown in FIG. A NAND circuit 71 is added to the control memory 7, AND circuits 82 and 83 are added to the microcontrol circuit 8, and a monitoring circuit 5 is added. Monitoring time 4
The path 5 includes a holding type flip-flop 51, an AND 52, a counting circuit 53, an AND 54, and a holding type flip-flop 5.
It consists of 5. The inputs of the holding type flip-flop 51 are a set input on line 8b and a reset input on line 8c. The input of the AND 52 is a holding type flip-flop 5.
1 and the clock signal 51b, and the inputs of the counting circuit 53 are the reset input of the line 8c and the output of the AND 52. The inputs of the AND 54 are all the outputs 53a to 53b of the counting circuit 53. Holding type flip-flop 5
The input conditions of 5 are the set input of the output signal 54a of the AND 54 and the reset instruction 55a by the microprogram instruction.
This is the reset input. The ROM and WCM switching signal 6b being output from the address register 62 is inverted by the NAND circuit 71, and the ROM 72 is selected by the signal line 71a. Furthermore, the output signal line 71b of the NAND circuit 71 is connected to the counter circuit register 71 at the 28th bit of the microinstruction register 81.
The set designation line 81a is ANDed by the AND circuit 82 to generate a signal on the signal line 8c that resets the holding flip-flop 51 and the counting circuit 53. Also, NAND circuit 7
1 output signal line 71c is the 2nd output signal line 71c of the microinstruction register 81.
9th bit count start designation signal line 81b and AND circuit 8
3, and the holding type flip-flop 51 is set. The ROM and WCM switching signal 6b being output from the address register 62 directly selects the WCM 73 through the signal line 62d, and further causes the selection circuit 74 to select the microprogram from the WCM 73 through the signal line 62e. When passing control from the ROM 72 to the WCM 73, as shown in FIG. 5, an instruction code F, 2. An instruction consisting of a stack of addresses in the ROM or WCM is set in the instruction register 3, and the corresponding address in the ROM is selected for F2 in the same manner as in (2) described above.

The first microinstruction controls the D2 part of the instruction register 3 to be set in the address determination circuit 6.

At this time, since it is a jump from ROM to WCM, D2
Since the most significant bit of is set to 1, the most significant output signal line 6b of the address determining circuit 6 becomes 1, and the signal line 71a
becomes O, ROM 72 is not selected, and conversely, the signal line 62
d becomes 1, WCM73 is selected, and signal line 62
When e becomes 1, the microprogram read from the WCM 73 is selected by the selection circuit 74 through the data line 73a and enters the microinstruction register 81. That is, the microprogram from the WCM 73 is entered into the microinstruction register 81, and control is transferred from the microprogram in the ROM 72 to the microprogram in the WCM 73. (4) Jump WCM from WCM to ROM
When you want to execute a certain function on the ROM 73 side and return to the instruction next to the instruction in the instruction register 3 shown in FIG.
It is necessary to return to the instruction fetch routine prepared in .

This instruction fetch routine is located in ROM 72 at a fixed address. The last microprogram of WCM73 sets the next microprogram address, and of course the address line 8
The most significant bit of the 12 bits of a is set to O. When we set 1 to the 31st bit of the microinstruction register 81,
The CM address on the address line 8a is selected by the selector 61 via the signal line 8e and entered into the address register 62. Then, since the most significant bit of the address register 62 is O, the signal line 6b becomes 0, and the WCM selection signal line 62
d and the signal line 62e for selecting the microprogram of the WCM 73 are also set to O, and the microprogram on the WCM 73 side is not read out. On the other hand, the signal line 71a becomes 1 by the NAND circuit 71, the ROM 72 is selected, and the microprogram in the ROM 72 is set in the microinstruction register 81. This means that control is transferred from the microprogram in the WCM 73 to the microprogram in the ROM 72, in this case the instruction fetch routine. (5) W.C.
Monitoring of the microprogram of M In order to monitor the microprogram of the WCM 73 to prevent it from running out of control, the present invention provides the following functions.

That is, from the program of ROM 72 mentioned in (3) above, W
When transferring control to the CM73 program, set 1 to the 29th bit of the microprogram instruction for the jump. Then, since the ROM 72 side is naturally selected at this time, the AND circuit 83 calculates the logical product, the signal line 8b becomes 1, and the holding type flip-flop 51 of the counting circuit 53 for instructing the start of counting is set to 1. Then, the output line 51a of the flip-flop 51 becomes 1 in the AND circuit 52, and the clock signal line 51b receives output pulses at regular time intervals, so the counting circuit 53 starts counting. Counting circuit 53
is set to overflow at a certain constant value, that is, a value that satisfies the time during which the microprogram can perform sufficient work on the WCM 73 side. When the microprogram on the WCM73 side is operating normally, the instruction in the instruction register 3 is executed, the instruction jumps to the instruction fetch routine on the ROM72 side according to the procedure (4) above, and the contents in the instruction register 3 are transferred from the ROM72 to the WCM73. Control then shifts to bringing the next instruction into the instruction register 3. At this time, if the 28th bit of the microprogram instruction of the instruction fetch routine read from the ROM 72 and stored in the microinstruction register 81 is set to 1, the AND circuit 82 performs the AND operation (at this time, the RO
Since the M72 side is selected, the signal line 71b is set to 1. ) The reset signal line 8c becomes 1, and the holding flip-flop 51 and counting circuit 53 are all reset. When the holding type flip-flop 51 is reset, the AND circuit 52 cannot perform the AND operation, so the counting circuit 53 does not count at all. Therefore, the counting circuit 53 does not operate until control is next transferred to the microprogram of the WCM 73. However, when a bug occurs in the microprogram on the WCM 73 side, control is not transferred to the microprogram that executes step (4), so the counting circuit 53 continues counting and eventually overflows.

When overflow occurs, the holding type flip-flop 55 is set to 1.
At the same time, the cons.
The contents of tanto register 4 are placed in address register 62. The contents of the constant register 4 are always set to the address of the next instruction fetch routine microprogram. Therefore, when the microprogram on the WCM73 side goes out of control, the counter circuit 53 overflows, and the recovery control means forcibly writes the ROM.
Control is then returned to the instruction fetch routine on the 72 side. Also, since the state of the holding type flip-flop 55 can be read by a command, the state of this holding type flip-flop 55 must be read in the next instruction after the instruction to transfer control from the ROM 72 to the WCM 73, and if this flip-flop 55 is 1 It turns out that there is a bug in the microprogram of Tsutara WCM73. Note that this flip-flop 55 can be reset by a command. O Also, as is clear from the explanation so far, starting the counting circuit 53 or resetting the counting circuit 53 can only be done by the microprogram on the ROM 72 side, so the microprogram on the WCM 73 side may run out of control and cause the counting circuit 53 to be reset. It is not impossible to reset and return to the normal route on the ROM72 side. According to the above procedure, the present invention makes it possible to monitor the operation of the microprogram on the WCM 73 side under time constraints. (6) How to debug ROM72 microprogram using WCM73ROM
W the microprogram with the address for the 72 side.
FIG. 6 shows a method of debugging on the CM73 side.

What is newly added in Figure 6 is the address determination circuit 6.
is the OR circuit 65. In the present invention, means for externally controlling specific bits of the address register 62 is provided. In the OR circuit 65, the signal line 9aI: d. The signal line 61b indicating the 11th bit of the CM address is ORed and set in the address register 62 through the signal line 65a. As is clear from FIGS. 1 and 6, when the external operation key 9 is set to 0FF (0 state), the signal line 9a becomes O, and the 11th bit of the CM address is transferred directly to the address register 62 by the OR circuit 65. is set to

However, when the external operation key 9 is set to 0N (1 state), the signal line 9a becomes 1, and the CM address 1 is set by the OR circuit 65.
The first bit always becomes 1 and is set in the address register 62. That is, when you want to debug a microprogram addressed for the ROM 72 side on the WCM 73 side, if you set the external operation key 9 to 0N, the 11th bit of the address register 62 will always be 1, and the signal line 6b will be 1.
Therefore, the WCM73 side is selected, and it is exactly the same as the microprogram for the ROM side! If you put this into the WCM73 side, the microprogram on the WCM73 side will be executed, and you can debug the microprogram on the WCM73 side while correcting the microprogram so that it is executed correctly. By the above procedure, ROM7
WC the microprogram addressed for the 2nd side.
It becomes possible to debug by inserting it into the M73 side. As explained above, this invention provides a monitoring mechanism for monitoring the operation of the microprogram in the writable control memory WCM73, so that even if the microprogram goes out of control, the ROM
Because the program always moves to a program that can capture the next instruction, even in systems with strict online requirements, there is no online command in WCM).
It is possible to specify subroutine parameters by writing data to the input, efficiently create firmware, and write the diagnostic program from main memory to the WCM to enable complete microprogramming of diagnosis.Additionally, if necessary, control memory address register By making the most significant bit of the ROM externally operable, economical and efficient ROM microprograms can be expected.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram showing an example of the microprogram control method according to the present invention, and FIG. 2 shows the contents of the main memory in the WC.
Figure 3 is a diagram showing the command format of the command to write the contents of main memory to WCM. Figure 4 is a diagram showing the configuration of the WCM microprogram monitoring function. Figure 5 is a diagram showing the instruction format of an instruction to jump between ROM and WCM, and Figure 6 is a diagram showing the instruction format for jumping between ROM and WCM.
1 is a block diagram showing a method for debugging a ROM microprogram using the ROM microprogram. 1: Main memory, 2: Buffer register, 3: Instruction register, 4: Constant register, 5: Monitoring circuit, 6: Address determination circuit, 7: Control memory, 8: Micro control circuit,
53: Counting circuit, 72: ROM173: WCM, 74:
Selection circuit, 81: Microprogram instruction register.

Claims (1)

[Claims] 1. In a data processing device that performs microprogram control, there is a read-only control memory that stores the microprogram, a buffer register that stores data from the main memory, and a writable control that stores data from the buffer register. a memory; a microprogram instruction register; an address register for setting an address for at least one of the read-only control memory and the writable control memory; and the read-only control memory controlled by a specific bit of the address register. a selection circuit for inputting a microprogram read from the microprogram or the writable control memory into the microprogram instruction register; and a selection circuit connected to a specific bit of the microprogram instruction register;
write control means for writing from the buffer register to the writable control memory; and a write control means connected to a specific bit of the address register to write from the read-only control memory to the writable control memory and vice versa. a control means for passing control of a microprogram from said writable control memory to said read-only control memory; and a control means connected to a specific bit of said microinstruction register to initiate counting only from the microprogram of said read-only control memory. and a counting circuit that can be reset and performs a counting operation when the microprogram in the writable control memory is operating, and when the counting circuit overflows, the control memory is transferred from the writable control memory to the read-only control memory. a return control means that returns control to the microprogram at a specific address; a holding flip-flop that is controlled by an overflow of the counting circuit to hold an overflow state and can read and reset this held state by the microprogram; and the address; 1. A microprogram control system comprising means for externally controlling specific bits of a register.