JPS6047566A - Variable power device for video plate making - Google Patents

Abstract

PURPOSE:To supply an image signal to an exposure drum with a summerized interpolation output and output an image of optional variable power magnifications set at a setting part through simple constitution by separating image data from a frame memory horizontally and vertically, and performing interpolation. CONSTITUTION:A variable power device for video plate making is provided with horizontal and vertical variable power circuits, and the video signal of every horizontal line stored in the frame memory 2 of the horizontal variable power circuit is converted by a D/A converter 3 into an analog signal, which is interpolated by an interpolating circuit 4. This operation is performed synchronizing with pulses of a sample pulse generating circuit 11 and digital data of every scanning line from an A/D converter 5 are written in vertical line memories 15 and 16 of the vertical variable power circuit. Data read out of those memories 15 and 16 are converted by a D/A converter 19 into analog data, which are interpolated by an interpolating circuit 22. Then the image signal is applied to the exposure drum 30 with the summerized interpolation output to output an image of optional variable power magnifications set in horizontal and vertical variable power magnification setting parts 9 and 25.

Description

[Detailed description of the invention] The present invention relates to a variable magnification device in a video plate making device.

Due to the recent remarkable development and spread of video technology and changes in publishing trends due to the increased use of printed materials, it is now possible to use desired screens in continuous video information recorded on video tapes, etc. for photographs, printed manuscripts, etc. If so, you will get many benefits. Compared to the traditional method in which photographers use still cameras to shoot film, this method offers improved speed, photo opportunities, shutter sounds, flashlights,
This is because it is free from constraints such as low brightness, and at the same time, various needs can be expected to develop. For example, a photograph or printing plate can be created directly from video information recorded on a videotape, or a TV composite video signal such as R (red), G (green), B (
It is now possible to create a blue signal and then directly create a printing plate, making it possible to publish at a lower cost and faster than conventional methods.

However, when using movie information recorded on a conventional videotape as a printing manuscript, the videotape is first set in a playback device and continuous images are displayed on a CRT (cathode ray tube) using slow or stop playback. After creating a film I11 draft by photographing a desired image with a still camera while observing the screen, color separation plates are created from the film I1 draft using a plate-making device such as a color scanner. Therefore, the quality of the printed document depends on the resolution of the television image. However, color television broadcasting in Japan uses the NTSC system, and one image (one frame) is formed using 525 scanning lines, regardless of the size of the television image. Therefore, (1) frame image quality, resolution, etc. are extremely poor compared to general color films. In addition, in the method of selecting a desired screen from continuous video footage and photographing it with a still camera,
In order to improve image quality, a special color is applied to the front of the camera due to the mismatch between the color temperature of CRT, the coloring characteristics and brightness range of RGB phosphors, and the color temperature and coloring material characteristics and density range of color film. There are problems in that it is necessary to insert a temperature conversion filter and to adjust the hue, contrast, etc. of the color monitor. Furthermore, it is not always possible to obtain a satisfactory color tone with these corrections alone.

Furthermore, the number of scanning lines on a TV greatly affects the quality of resolution. When the image projected on a CRT is accurately focused and photographed with a camera, these scanning lines become noticeable as horizontal stripes on the film. will be recorded. Since the scanning lines recorded on this film cause moiré fringes during the plate-making process, a photographing technique is required to erase the scanning lines. For example, to obtain a desired image from a continuous image with little movement, the effects of scanning lines are usually erased by exposing several frames onto a single sheet of film while playing back or slowing down. Since it cannot be completely erased, I try to shift the focus of the photograph slightly.

However, this method has the disadvantage that it is difficult to accurately photograph a desired screen and that the screen may be blurred. Therefore, in order to obtain a desired image from continuous video with large movements, it is necessary to perform stop playback. Normally, with a 374-inch VTR, in the case of stop playback, only one field of video signals is reproduced, and the vertical resolution of the image projected on the CRT is halved, making scanning line erasure a more difficult photographic technique than in the former case. is required. In such cases, since the resolving power of color film is generally around 50 mm/mm, a photographing method is used that takes advantage of the limit of the resolving power of color film. That is, CRT J-
The scanning lines are erased by photographing the desired image of , in such a reduced size that the scanning lines cannot be distinguished. Therefore, since the video image, which is inherently poor in image quality, is printed on the color film in a very small size, the final print size is limited to 100 to 1000 A7, and any size beyond that has no commercial value. becomes. Furthermore, there is also the drawback that workability is significantly degraded due to page layout and enlarged plate making of small-sized color images.

A television image plate-making device to solve the problems of ``2 series'' reads out a video signal corresponding to one desired frame from a video tape recorder that records a television video signal, and converts this video signal into three primary colors. There is a device that converts the three primary color signals into a printing image signal, and then supplies this printing image signal to a platemaking scanner to produce a printing plate. Patent application No. 57-188745
There are inventions such as No. 188749. However, since none of these video engraving apparatuses has a variable magnification device that changes the size of the output image, they have the disadvantage that they cannot output an image of an arbitrary size.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a variable-magnification device for a video plate making apparatus as described above, which allows an image of any size to be output to the output section of a scanner by operating the variable-magnification device.

This invention will be explained below.

This invention relates to a variable magnification device for video plate making, and
As shown in the figure, there is a frame memory 2 which stores the video signal vS digitized by the An converter l in the middle of the frame, and a digital video signal read out from the frame memory 2 for each line (horizontal direction). An interpolation circuit 4 which performs analog conversion and interpolation using the A converter 3; and an An converter 5 which digitizes the output ATS of the interpolation circuit 4 in synchronization with the strobe signal ST from the sample pulse generation circuit 11.
and frame memory 2. A horizontal direction control circuit that controls the operations of the interpolation circuit 4 and the sample pulse generation circuit 11;
I) Line memories 15 and 1G that store the output data of the converter 5 via pass buffers 13 and 14 for each vertical scanning line, and writing to these line memories 15 and 1B is controlled based on the strobe signal S. At the same time, a memory controller 20 that controls data readout, and a line memory 1 via this memory controller 2o.
An interpolation circuit 22 converts the digital data read out from the scanners 5 and 16 into analog data and interpolates it in the OA converter 19 via the path buffers 17 and 18, and provides the interpolated output AMS to the exposure drum 30 of the scanner. A vertical direction control circuit for controlling the operation of a memory controller 20 and an interpolation circuit 22 according to the position is provided.

Here, the horizontal direction control circuit controls the synchronization signal (horizontal) of the video signal vS.

vertical) SY and color subcarrier frequency 'SC (for example, in the case of an NTSC: system television signal: fso=3.
a synchronizing signal generating section 8 that generates a synchronizing signal C86 (57 fl 145 MHz); and a read pulse generating circuit 7 that receives the synchronizing signal C86 and outputs read pulses C98 and C59.
, a memory controller 6 which controls writing and reading of the frame memory 2 by inputting a read pulse C98, a horizontal magnification setting unit 9 which sets a magnification in the horizontal direction (H), and a horizontal magnification rate. It is composed of a frequency multiplier circuit 10 that frequency-multiplies the synchronizing signal C98 according to the scaling factor V set in the setting section 9, and a vertical direction control circuit that multiplies the frequency of the synchronizing signal C98 according to the scaling factor V set in the setting section 9. The magnification ratio setting unit 25 inputs the position signal PS from the rotary encoder 32 connected to the exposure drum 30 of the scanner, and the magnification ratio VM3 set by the vertical magnification ratio setting unit 25 is input.
Frequency multiplier circuit 2 that multiplies the frequency with and VH2, respectively.
3 and 24 and the frequency signal C92 output from the frequency multiplier circuit 24, the memory controller 20 and O
The read pulse generation circuit 21 controls the timing of the A converter 19. Further, a start point pulse generation circuit 31 that outputs one start point pulse C53 for one rotation of the exposure drum 30 is connected to the exposure drum 3o, and the start point pulse C93 is input to the memory controllers 6 and 20, respectively. It has become so.

In such a configuration, when an NTSC television signal is input as a video signal vS, the AD converter l converts this video signal vS into a digital quantity and stores it in the frame memory 2. Assuming that the signal is sampled at four times the subcarrier frequency 'SC, that is, 4f8o, the amount of image data in the frame memory 2 is 755 pixels (horizontal direction) as shown in Figure 2.
This results in 483 lines (vertical direction). In this case, the video signal vS is shown in FIG. 3(A).

As shown in (B), each line (HL) is converted into a digital signal and sequentially stored in the frame memory 2, but the video signal of each line is is output, and the interval l between the sampling points P + + P i + 1 indicates the sampling rate, and the data at each sampling point PL sampled at this rate is digitized by the AD converter l and converted into a frame. Stored in memory 2. In addition, Bt in Figure 3
indicates the horizontal blanking time of the frame.

In this way, when the image data for one frame of the video signal vS is stored in the frame memory 2, the image data stored in the frame memory 2 is transferred to the memory controller 7.
(timing C5a), and the OA converter 3
At timing GS9, the signal is converted into an analog signal S and inputted to the interpolation circuit 4, and the interpolated output AIS interpolated by the interpolation circuit 4 is inputted to the AD converter 5. Here, the operation of the interpolation circuit 4 is explained in FIGS.
E), FIG. 4(C) shows the video signal V
The synchronizing signal generating section 8 outputs a lock pulse C86 as shown in FIG. In accordance with the magnification ratio V set by the horizontal magnification ratio setting section 9, the lock pulse C37 is frequency multiplied as shown in FIG. Timing control C from frame memory 2 to memory controller 6
The image data read out at 38 is converted into analog +113 by the OA converter 3 according to the timing signal CS9 from the read pulse generation circuit 7, so the timing signal C3
9 is synchronized with the clock pulse CS6, the analog signal IS becomes as shown in FIG. 4 (El), and this analog signal IS is input to the interpolation circuit 4. and,
A pulse signal C37 as shown in FIG. 4(B) whose frequency has been multiplied by the frequency multiplier circuit 10 is inputted to the interpolation circuit 4, and the adjacent data of the analog signal S is interpolated as shown in FIG. 4(E). to obtain the interpolated signal AIS. In this case, the pulse signal C3? has a frequency three times that of the clock signal C86, so the interval of the analog signal S is interpolated three times as much. In addition, clock signal C86 and pulse signal C3
The ratio with 7 can be not only an integer ratio but also an arbitrary ratio. Note that details of the interpolation circuit 4 will be described later.

The horizontal video signal AIS interpolated by the interpolation circuit 4 in this way is converted into a digital quantity again by the An converter 5 at the timing of the strobe signal ST from the sample pulse generation circuit 11, and then converted into a digital quantity by the vertical magnification circuit. The data is passed through pass buffers 13 and 14 and stored in line memories 15 and 16 that store data for one scanning line in the vertical direction. In this case, the line memories 15 and 16 are controlled by the memory controller 20, so that the line memory 15 stores the data of the scanning line Pi shown in FIG. 2, and the line memory 16 stores the data of the scanning line P++1 shown in FIG. Since the line memories 15 and 16 are designed to store data, the line memories 15 and 16 store image data of two scanning lines in the vertical direction V out of the image data stored in the frame memory 2. In this case, the line memories 15 and 16 repeatedly perform writing and reading, so when the data of the scanning line Pi is being read in the line memory 15, the data of the scanning line P++1 is written in the line memory 1B. It will be. In this way, line memory I5
The data of the scanning lines Pi stored in 16 and 16 are processed in a configuration as shown in FIG. That is, the switch circuit 191 is switched by the read pulse C94 from the read pulse generating circuit 21, and the data of the line memory 15. The stored data scaled in the direction is converted into an analog signal MS and sent to the interpolation circuit 2.
2 is input. Therefore, as shown in FIG. 6, in the analog signal MS output from the An converter 19, the data of the first scanning line (Pl) is output as an analog signal, and then the data of the second scanning line (P2) is output as an analog signal. It is output as a signal and is sequentially stored in the line memory 15. By switching the output of IEi with the switch circuit 191, vertical image data (for example, Pi in FIG. 2) up to the scanning line that has been scaled by the horizontal scaling circuit is converted into an analog signal M.
S, and these are sequentially input to the interpolation circuit 22. The interpolation circuit 22 operates in the same manner as the interpolation circuit 4 described above, and interpolates between data according to the pulse signal GSI from the frequency multiplier circuit 23, and applies MS to the interpolation signal onto a film or the like mounted on the exposure drum 30. Outputs exposure. Incidentally, the time required to store the image data of each scanning line in the line memory 15 or 16 is equal to the time for one television frame. Therefore, in the case of the NTSC system, it is approximately 93.3 milliseconds (1/30 second). In contrast, the conversion time for output to a scanner is typically 50
Since the scanning time is as slow as ~60 milliseconds or more, the two line memories 15 and 1B can be used to alternately write and read scanning line data as described above.

Note that the rotational position of the exposure drum 30 is detected by a rotary encoder 32, and its position signal PS
is input to the frequency multiplication circuits 23 and 24, so that the data interpolated by the interpolation circuit 22 does not deviate from the synchronization of the rotation of the exposure drum 30. Further, since the starting point pulse generating circuit 31 is connected to the exposure drum 30, the starting point pulse C93 from the starting point pulse generating circuit 31 is inputted to the memory controllers 6 and 20, and the starting point pulse C93 is inputted in the horizontal and vertical directions. This prevents synchronization errors. If the scaling factor V of the horizontal scaling factor setting section 9 is changed to 1, the frequency of the frequency signal GS7 output from the frequency multiplier 10 will be converted, so the number of interpolated data in the interpolating circuit 4 (interpolation scaling factor) changes.

Similarly, by changing the vertical scaling factors VM2 and VH2 set by the vertical scaling factor setting section 25, the interpolation circuit 2
Since the number of interpolation data (interpolation magnification) to be interpolated in step 2 changes, by arbitrarily changing the magnification of the horizontal magnification setting section 9 and the vertical magnification setting section 25, it is possible to output an image at any magnification. can be obtained.

Next, an example in which a switched capacitor filter circuit is used as the interpolation circuit 4 or 22 will be explained with reference to FIG.
It has an analog switch consisting of 1 to QIO, and capacitors c2 and 0 connected to operational amplifiers 41 and 42.
4. C5 and C6 are charged and discharged by clock pulse φ1. On/off control is performed by φ2, and when the speed of these clock pulses φ1 and φ2 is changed, the signal input from the Kugata terminal IT changes in accordance with the frequency of the clock pulse, causing a stepwise change. The interpolated signal, which is this change signal, is output from the output terminal OT. Therefore, the lock pulses φ1 and φ2 as shown in FIG. 8(A) and (B) are inputted to the interpolation circuit 4 (or 22) from the lock 037 (or C3l) as shown in FIG. 8(C). When formed and input to a switched capacitor filter circuit, it is possible to interpolate between two signals with a division number depending on the frequency of clock C57 (or C9I). In addition, the number of data to be interpolated is as follows, assuming that the frame memory is loaded at 4·'sC (the number of pixels in the horizontal direction at this time is approximately 755 pixels) and the scanner output line is 200 mm/mm. By setting the number of interpolations to about 3 kels and 5 digits, a natural tone (not a mosaic style) can be obtained. Further, if the data is taken into the frame memory at 6φ'SC, the number of interpolated data may be 1 to 2.

As described below, according to the scaling device of the present invention, scaling in the horizontal direction and scaling in the vertical direction are separated, and in the horizontal direction, image data from the frame memory is converted into two pieces of data in the horizontal direction. In the vertical direction, the data output from the two line memories are interpolated in the vertical direction, and the combined interpolation output is used to give an image signal to the exposure drum. It is possible to output images with variable magnification. Further, by using a switched capacitor filter circuit that can interpolate between two data using a frequency signal for horizontal and vertical interpolation, there is an advantage that interpolation can be easily performed with an extremely simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the structure of a frame memory, and FIG. 3 (A)
, (B) is a diagram for explaining the state of sampling in the horizontal direction, Figures 4 (A) to (E) are timing charts for explaining the interpolation operation according to the present invention, and Figure 5 is a diagram for explaining the operation of interpolation according to the present invention. FIG. 6 is a waveform diagram showing an example of data output in the vertical direction according to the present invention; FIG. 7 is a circuit connection diagram showing an example of the interpolation circuit used in the present invention; FIG. (A) to (c) are timing charts showing examples of the operation. 1.5...AD converter, 3...DA converter, 2...
・Frame memory, 4, 22...Interpolation circuit, 6, 2o
. . . Memory controller, 7, 21 . . . Read pulse generation circuit, 8 . ...Sample pulse generation circuit, 15.16...
・Line memory, 25...Vertical magnification setting section, 3
0...Exposure drum. Applicant's agent Yu Yasugata 3-1+-+

Claims (1)

Claims: A frame memory that stores a digitized video signal at frame '14, and a first interpolation circuit that converts and interpolates the digital video signal for each line read from the frame memory into an analog format. an AD converter that digitizes the output of the interpolation circuit in synchronization with a strobe signal from the sample pulse generation circuit, and a horizontal direction control that controls the operations of the frame memory, the first interpolation circuit, and the sample pulse generation circuit. a circuit, first and second line memories that store output data of the AD converter for each vertical scanning line, and a memory controller that controls writing and reading of these first and second line memories; a second interpolation circuit that converts and interpolates the digital data read from the first and second line memories through the memory controller and provides the interpolation output to the exposure section of the scanner; 1. A variable magnification device for video plate making, comprising: a vertical direction control circuit that controls operations of the memory controller and the second interpolation circuit according to the above.