JPS6046731B2 - input device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input device suitable for electronic devices such as calculators.

Conventionally, electronic devices such as calculators have had electronic circuits composed of transistors, small-scale integrated circuits, etc., but with the application of large-scale integrated circuits, improvements have been made to input devices for inputting data into electronic devices. .

FIG. 1 is a block diagram showing the configuration of a conventional input device.
IK, 2...9, OK is 0-9 for electronic devices
This is a key switch for inputting numerical data.

Such switches have one end connected in common and a power supply +5
Connected to V. The other ends of the switches are connected to encoder circuits E separately. As shown in the figure, the encoder circuit E has diodes D- appropriately connected to the intersections of the row lines and column lines constituting the matrix, and the row lines are connected to the switches IK, 2, . . . 9, and 0, as described above. is connected to the other end as shown. One end of the column line is grounded via resistors R, ~R, and the other end is connected to the single power ends of AND gates AG1-AG4. Other input terminals of AND gates AG1 to AG4 are signals Tl, T2, and T3 for opening and closing the gates.
, T, are input in a time-divisional manner, and the signals T, ~T.

is applied to each of the AND gates AG1 to AG4, the output of the encoder circuit E is applied to the OR gate OG in series.
Output via . The input device having the circuit configuration described above increases the number of row lines of the encoder circuit E according to the number of key switches, and when the encoder circuit E is incorporated into a large-scale integrated circuit, the number of input terminals of the large-scale integrated circuit increases. cause it to happen.

In view of the above points, the present invention provides an input device that eliminates the above points.

Other objects will become clear from the following description of the embodiments given in conjunction with the drawings.

FIG. 2 shows an embodiment of the input device according to the present invention.

In the figure, KB is a key switch circuit whose switches open and close by operating the keys arranged on the keyboard, and the switches that respond to the keys are row lines L1 to L4 and column lines C0 to C0, which make up a matrix. Each terminal of the switch is connected to C7, for example, 1 to 3 as shown in the diagram.
A switch indicated by 2 is placed. TC is a signal generation circuit, and in order to output signals with different phases, a plurality of D-type flip-flops FF1 to FF7 are connected in series as shown in the figure, and the output of only one flip-flop is 1. be done.

The respective outputs of the flip-flops FF1 to FF7 described above are connected to the column lines C1 to C7 of the key switch circuit KB.

One end of the row lines L1 to L4 of the key switch circuit KB is connected to the OR gate 0G1, and the row lines L2 and L4 are connected to the OR gate 0G2, and the row lines L3 and L4 are connected to the OR gate 0G3. The output of flip-flop FF8 and OR gate 0G3 is applied to the input of OR gate 0G1 via flip-flop FF9 and FFlo.

The operation of the embodiment constructed as described above will be explained with reference to the timing chart shown in FIG. The signal generation circuit TC generates flip-flops FFl to FF8 by the signal TO and clock pulse CP applied to its input terminal at predetermined time intervals.
Signals T1 to T as shown in FIG.
Outputs 7.

Signals TO to T7 are sequentially applied to column lines CO to C7 of the switch circuit. In this state, when a key switch (not shown) on the keyboard is operated, the corresponding switch K7, for example, becomes 0N, and the row line L1 and column line C3
and are shorted. Next, in order to know that the switch K4 is turned on, the signal TO applied to the signal generation circuit TC at a predetermined time is sequentially transmitted to the flip-flops by a clock pulse, and the output of the flip-flop FF3 is brought to an H level. When a signal T3 is applied to the column line, this signal is transmitted to the row line D1 via the switch K4 and output via the OR gate 0G1.

The signal TO of the output of this OR gate (assuming the time during which the signal TO is kept at H level is 11)Ittime)
The state from 1 to 10 bit times is input to the computer as a 10-bit serial code signal representing switch K4. Next, the key to turn on switch Kl3 is operated. Then, as described above, the flip-flop transmits the H level signal of the signal TO in accordance with the arrival of the clock pulse,
A signal is applied to the OR gate 0G1 via the switch Kl4 that shorts the column line C5 and the row line L2, and a signal delayed by one bit time by the flip-flop FF8 is applied to the OR gate 0G1 as a serial code signal of 000011000. It is derived from 0G1.

Similarly to the above, when switch K22 is turned on, signal T5
appears in the row "L3" and is applied in series to the OR gate 0G1, and 2 when applied through the OR gate 0G3.
A bit-delayed signal is applied, and eventually 00000101
It is derived from the OR gate 0G1 as a signal of 00. When the switch K3l is pressed, a signal of 0000001110 is obtained as the output of the OR gate 0G1.

The signal generating circuit TC described above applies signals TO to T7 to the key switch circuit B while the switches K1 to K32 are on.

As described above, the present invention arranges key switches at the intersections of the matrix, and at one end of the matrix (for example, a column line).
When the key switch is turned on, a signal applied from the key switch is derived from the other end (column line or row line), and this derived signal is obtained via a delay means to obtain a coded signal corresponding to the key operation and input to the input device. It's meant to be simple.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional input device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram explaining the operation of the block diagram shown in FIG. be. KB...Key switch circuit, FFl~FFlO
·····flip flop.

Claims (1)

[Claims] 1. A signal generating means for generating a signal, a plurality of key switches to which the signal of the signal generating means is applied, a delay means for delaying a signal obtained by the operation of the key switch, and a signal generating means for generating a signal by the operation of the key switch. It has an output means for outputting the obtained signal and the signal from the delay means as a serial data string, and when the key switch is operated, the key switch is determined from the serial data string from the output means. input device.