JPS6043708B2 - Automatic control method of frame synchronizer - Google Patents

Automatic control method of frame synchronizer

Info

Publication number
JPS6043708B2
JPS6043708B2 JP53044044A JP4404478A JPS6043708B2 JP S6043708 B2 JPS6043708 B2 JP S6043708B2 JP 53044044 A JP53044044 A JP 53044044A JP 4404478 A JP4404478 A JP 4404478A JP S6043708 B2 JPS6043708 B2 JP S6043708B2
Authority
JP
Japan
Prior art keywords
signal
input
frame synchronizer
output
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53044044A
Other languages
Japanese (ja)
Other versions
JPS54136122A (en
Inventor
幹夫 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP53044044A priority Critical patent/JPS6043708B2/en
Publication of JPS54136122A publication Critical patent/JPS54136122A/en
Publication of JPS6043708B2 publication Critical patent/JPS6043708B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は、テレビジョン放送に使用されるフレームシン
クロナイザー(Fs)の入力信号によるモードの切替の
制御方式に関し、特にタイムベースコレクタ(TBC)
の機能を合せもつているフレームシンクロナイザーの自
動制御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mode switching control method based on an input signal of a frame synchronizer (Fs) used in television broadcasting, and in particular to a method for controlling mode switching using an input signal of a frame synchronizer (Fs) used in television broadcasting.
This invention relates to an automatic control system for a frame synchronizer that has the following functions.

従来フレームシンクロナイザーを単なる映像信号位相変
換装置としてではなく、その内蔵するメモリーを応用し
て、タイムベースエラーの大きなVTR信号の時間軸安
定化装置として使用することが行なわれてきた。
Conventionally, a frame synchronizer has been used not only as a simple video signal phase converter, but also as a time base stabilizing device for VTR signals with large time base errors by applying its built-in memory.

この安定化装置として使用する時にはVTR出力信号の
持つ性質、即ち、タイムベースエラーの大きなこと、或
いはドロップアウト等のノイズを含む事等により、フレ
ームシンクロナイザーのメモリーヘの入力信号書き込み
動作が入力信号に正しく対応しない危険性がある為に、
FsにTBCアダプターを付加し、TBCアダプター内
に具備された入力映像信号に位相結合する同期信号再生
回路の出力パルスに依つて、Fsへの書き込み制御パル
スや、書き込みアドレスが制御される様にFsの動作状
態を切替えて使用する事により所期の目的を達していた
。しかしながらこの方式ではモード(VTR出力と、カ
メラ出力などの時間軸の安定した信号とを入力するモー
ド)に応じてTBC機能を入切しなければならず、モー
ド切替時に必ず出力画面ショックを併つていた。
When used as a stabilizing device, due to the characteristics of the VTR output signal, such as large time base errors or noise such as dropouts, the input signal writing operation to the frame synchronizer memory may not match the input signal. Due to the risk of not responding correctly,
A TBC adapter is added to the Fs, and the Fs is configured so that the write control pulse to the Fs and the write address are controlled by the output pulse of a synchronization signal regeneration circuit that is phase-coupled with the input video signal provided in the TBC adapter. The intended purpose was achieved by switching the operating state of the device. However, with this method, the TBC function must be turned on and off depending on the mode (a mode in which VTR output and a stable time-axis signal such as camera output are input), and there is always an output screen shock when switching modes. was.

このη℃アダプターを常時接続しておく方法も可能であ
るが、この場合TBCアダプターに依る特性劣化を避け
られない事、及びFsへの書き込み制御ルスが、TBC
アダプター内の同期信号再生回路から供給される為にこ
の再生部のN℃ループによる位相結合動作の・慣性に依
つて、入力信号が瞬時切替された時にその信号間の位相
変化に追随できない現象が発生する。この時書き込みア
ドレスが入力画像と対応しない為にメモリー出力に現わ
れる絵は入力画像の正しい配列を再現できない。以上の
点からFsは入力信号に応じてモードを手動で切替ねば
ならず、又その出力画像に何等かのショックを必ず併う
という欠点があつた。
It is also possible to keep this η℃ adapter connected all the time, but in this case, characteristic deterioration due to the TBC adapter cannot be avoided, and the write control pulse to Fs is
Since the synchronization signal is supplied from the synchronization signal regeneration circuit inside the adapter, due to the inertia of the phase coupling operation by the N°C loop of this regeneration section, there is a phenomenon in which it is not possible to follow the phase change between the input signals when the input signal is instantaneously switched. Occur. At this time, since the write address does not correspond to the input image, the picture appearing in the memory output cannot reproduce the correct arrangement of the input image. From the above points, the Fs has the disadvantage that the mode must be manually switched according to the input signal, and that the output image always contains some kind of shock.

したがつて、本発明の目的は従来の欠点を除いて、Fs
に入つてくる信号が瞬時に切替つても、切替つた信号に
応じてFsの動作モードが自動的に切替わり、しかもF
s出力に切替えによる画面ショックが何ら現われないフ
レームシンクロナイザーの自動制御方式が得られる。本
発明によれば、VTR出力にVTR出力であることを示
すパイロット信号を付加し、Fs内ではこのパイロット
信号の有無の変化を検知して書き込み禁止制御回路を直
ぐに働かせるとともに、入力ビデオ信号の径路、メモリ
への書き込みクロック、及びアドレスクリアパルス9切
替などのモード切替えをメモリー書き込み動作シーケン
スの区切で行うように制御するフレームシンクロナイザ
の自動制御方式が得られる。
Therefore, the object of the present invention is to eliminate the conventional drawbacks and to improve Fs
Even if the signal input to the Fs changes instantaneously, the operating mode of the Fs will automatically change according to the changed signal.
An automatic control system for the frame synchronizer is obtained in which no screen shock occurs due to switching to the s output. According to the present invention, a pilot signal indicating that it is a VTR output is added to the VTR output, a change in the presence or absence of this pilot signal is detected within Fs, and the write inhibit control circuit is activated immediately, and the path of the input video signal is , an automatic control system for a frame synchronizer is obtained which controls mode switching such as switching of the write clock to the memory and the address clear pulse 9 at the break of the memory write operation sequence.

次に本発明の一実施例を示した図面を参照して本発明の
詳細な説明する。
Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

第1図は本発明に係わるシステムの一例を示す図であり
、■TRlからの信号は帯域除外フィルター2でパイロ
ット信号に対応する帯域が除かれる。パイロット信号発
生器3では例えば4.5MHzの固定周波数を発生し混
合器4でVTR出力と混合させる。パイロット信号の周
波数はVTRの出力の映像情報に影響がない周波数に選
ばれる。混合器4の出力は切替器5に供給されている。
切替器5には■TR出力とは違つて時間軸が安定な信号
、例えばカメラ6の出力も同時に供給されており、結局
、切替器5の出力には時間軸の安定した信号と不安定な
信号とが切替つて出力されることになる。この信号は例
えば、マイクロ波中継装置7を経て、基地局8に伝送さ
れる。一般にこのようなシステムでは基地局.8は野外
に設置されることが多い。基地局8内において、マイク
ロ波中継装置7からの信号はTBCアダプター9及びパ
イロット信号受信器10に供給される。
FIG. 1 is a diagram showing an example of a system according to the present invention, in which the band corresponding to the pilot signal is removed from the signal from TRl by a band exclusion filter 2. The pilot signal generator 3 generates a fixed frequency of, for example, 4.5 MHz, and the mixer 4 mixes it with the VTR output. The frequency of the pilot signal is selected to have no effect on the video information output from the VTR. The output of mixer 4 is supplied to switch 5.
Unlike the TR output, a signal with a stable time axis, such as the output of the camera 6, is also supplied to the switch 5 at the same time.In the end, the output of the switch 5 has both a signal with a stable time axis and an unstable signal. The signal will be switched and output. This signal is transmitted to the base station 8 via the microwave repeater 7, for example. Generally, in such systems, the base station. 8 is often installed outdoors. Within the base station 8, the signal from the microwave repeater 7 is supplied to a TBC adapter 9 and a pilot signal receiver 10.

刊℃アダプター9及びパイロット信号受信器10の出力
は、フレー!ムシンクロナイザー(Fs)11に送られ
る。パイロット信号受信器10はパイロット信号の有無
を検知して、その結果モード切替信号と書き込み禁止制
御信号をFSllに送る。TBCアダプタ9は、■TR
信号が入つているとき同期信号、映像1信号、及びクロ
ックパルスをFSllにおくる。第2図はパイロット信
号によるモードの切替えや、書き込み禁止制御のタイミ
ング示す図である。第2図を参照して動作を更に詳細に
説明する。■TR装置出力信号は一旦帯域除外フィルタ
ー2に供給され、該フィルタにてパイロット信号と同一
の周波数成分が除去され、しかる後、混合器4にてパイ
ロット信号がVTR信号に重畳されている。この重畳は
VTR信号の波形との同期をとることなく連続で一様に
行なわれている。第2図の時刻ちではFs入力信号が時
間軸の安定な信号A(カメラ信号)1から時間軸の不安
定な信号B(■TR信号)2に瞬時切替が行なわれる。
その結フ果受信側に設置されたパイロット信号受信器は
時刻t1から連続してパイロット信号の検出を行なう。
3にこの様子を示す。
The output of the adapter 9 and the pilot signal receiver 10 is FR! It is sent to Musynchronizer (Fs) 11. The pilot signal receiver 10 detects the presence or absence of a pilot signal and, as a result, sends a mode switching signal and a write inhibit control signal to the FSll. TBC adapter 9 is ■TR
When a signal is input, a synchronization signal, video 1 signal, and clock pulse are sent to FSll. FIG. 2 is a diagram showing the timing of mode switching and write prohibition control using pilot signals. The operation will be explained in more detail with reference to FIG. (2) The output signal of the TR device is once supplied to a band exclusion filter 2, where the same frequency components as the pilot signal are removed, and then the pilot signal is superimposed on the VTR signal by a mixer 4. This superimposition is performed continuously and uniformly without synchronization with the waveform of the VTR signal. At time 1 in FIG. 2, the Fs input signal is instantaneously switched from the signal A (camera signal) 1, which is stable on the time axis, to the signal B (■TR signal) 2, which is unstable on the time axis.
As a result, the pilot signal receiver installed on the receiving side detects pilot signals continuously from time t1.
Figure 3 shows this situation.

該パイロット信号がt1の時刻で検出されると直ちに書
き込み禁止制御回路が動作し4に示す様にt1から成る
時間巾だけ書・き込み禁止を行う。この制御に依り、F
sの内蔵メモリーへの書き込みが禁止されるので5に示
す如く、切替以前の信号がFs出力側に現われ、書き込
み禁止解除まで継続される。従つて、入力信号の切替が
行なわれた時点でのショックを併う画“像はFs出力に
は現われない。方、Fsの動作モードの切替は6で示す
ように時刻t1以降に現われる最初の入力信号の垂直パ
ルスタイミングに依り行う。(フィールドタイプのFs
の場合)従つて、モード切替に併うショックも書き込み
禁止期間中に行なわれるのでFs出力画像にはまつたく
現われない。又、第2図では該禁止期間を4フィールド
巾に設定しているが、これは丁℃アダプター内の同期信
号再生回路の位相結合完了時間を考慮した為であり、結
合時間の速い同期信号再生回路を用いれば、更に短くす
ることも可能である。次に時刻■にて再び入力信号の切
替えが行なわれると前述と同様にT3からT4まで書き
込み禁止が行なわれ、その間に現われる最初の垂直パル
スタイミングに依り、モード切替えが行なわれる。又、
切替えられた信号は時刻ζでFs出力側に現われるので
、何等ショックを併なわない信号が得られる。4に示す
ような書き込み禁止制御を行うにはパイロット信号の有
無によつて状態が変化してゆく論理回路を形成すれば容
易に得られる。
Immediately when the pilot signal is detected at time t1, the write inhibit control circuit operates and inhibits writing for a time span of t1 as shown in 4. With this control, F
Since writing to the built-in memory of s is prohibited, as shown in 5, the signal before switching appears on the Fs output side and continues until the write prohibition is released. Therefore, the image with a shock at the time when the input signal is switched does not appear in the Fs output.On the other hand, the switching of the Fs operation mode is caused by the first image that appears after time t1 as shown in 6. This is done depending on the vertical pulse timing of the input signal. (Field type Fs
) Therefore, the shock associated with mode switching is also performed during the write-inhibited period, so it does not appear in the Fs output image at all. In addition, in Fig. 2, the prohibition period is set to 4 fields, but this is to take into account the phase coupling completion time of the synchronization signal regeneration circuit in the adapter, and the synchronization signal reproduction with a fast coupling time It is possible to make it even shorter by using a circuit. Next, when the input signal is switched again at time {circle around (2)}, writing is inhibited from T3 to T4 in the same manner as described above, and mode switching is performed according to the first vertical pulse timing that appears during that time. or,
Since the switched signal appears on the Fs output side at time ζ, a signal without any shock can be obtained. Write inhibit control as shown in FIG. 4 can be easily achieved by forming a logic circuit whose state changes depending on the presence or absence of a pilot signal.

以上、詳細に説明したように、本発明によればFsに入
つてくる信号が瞬時に切替わつても切替わつた信号に応
じてFsの動作モードを自動的に切替え、しかもFs出
力に切替えによる画面シヨツクが何ら現われることがな
いフレームシンクロナイザーの自動制御方式が得られる
As explained above in detail, according to the present invention, even if the signal input to the Fs is switched instantaneously, the operation mode of the Fs is automatically switched according to the switched signal, and moreover, the operation mode is automatically switched to the Fs output. An automatic control method of the frame synchronizer is obtained in which no screen shocks appear.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るシステムの例を示す図、第2図は
パイロット信号によるモードの切替えや、書き込み禁止
制御のタイミングを示す図、図において1・・・・・V
TRl2・・・・・・帯域除外フィルター、3・・・・
・・パイロット信号発生器、4・・・・・・混合器、5
・・・・・切替器、6・・・・・・テレビカメラ、7・
・・・・マイクロ波中継装置、8・・・・・・基地局、
9・・・TBCアダプター、10・・・・・・パイロッ
ト信号受信器、11・・・・・・フレームシンクロナイ
ザー。
FIG. 1 is a diagram showing an example of a system according to the present invention, and FIG. 2 is a diagram showing mode switching by pilot signals and timing of write prohibition control.
TRl2...Band exclusion filter, 3...
...Pilot signal generator, 4...Mixer, 5
...Switcher, 6...TV camera, 7.
...Microwave repeater, 8...Base station,
9...TBC adapter, 10...Pilot signal receiver, 11...Frame synchronizer.

Claims (1)

【特許請求の範囲】[Claims] 1 入力が時間軸の安定な信号と不安定な信号とでは動
作モードを変えているタイムベースコレクタ機能をもた
せたフレームシンクロナイザにおいて、入力に時間軸の
安定な第一の入力信号と時間軸の不安定な第二の入力信
号とが入つてくる場合第二の入力信号に判別用のパイロ
ット信号を付加するとともに、前記フレームシンクロナ
イザにおいて前記パイロット信号の有無の変化を検出し
て前記変化時点から所定の時間巾だけ書き込み禁止制御
を行い、且つ入力信号における書き込み動作シーケンス
の区切りで前記モード切替えを行うことを特徴とするフ
レームシンクロナイザの自動制御方式。
1 The operation mode changes depending on whether the input is a stable signal on the time axis or an unstable signal.In a frame synchronizer with a time base collector function, the input is a first input signal with a stable time axis and an unstable signal on the time axis. When a stable second input signal is input, a pilot signal for discrimination is added to the second input signal, the frame synchronizer detects a change in the presence or absence of the pilot signal, and a predetermined signal is detected from the point of change. An automatic control method for a frame synchronizer, characterized in that write prohibition control is performed for a time period, and the mode switching is performed at a break in a write operation sequence in an input signal.
JP53044044A 1978-04-13 1978-04-13 Automatic control method of frame synchronizer Expired JPS6043708B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53044044A JPS6043708B2 (en) 1978-04-13 1978-04-13 Automatic control method of frame synchronizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53044044A JPS6043708B2 (en) 1978-04-13 1978-04-13 Automatic control method of frame synchronizer

Publications (2)

Publication Number Publication Date
JPS54136122A JPS54136122A (en) 1979-10-23
JPS6043708B2 true JPS6043708B2 (en) 1985-09-30

Family

ID=12680611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53044044A Expired JPS6043708B2 (en) 1978-04-13 1978-04-13 Automatic control method of frame synchronizer

Country Status (1)

Country Link
JP (1) JPS6043708B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6445597U (en) * 1987-09-16 1989-03-20

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61130033A (en) * 1984-11-28 1986-06-17 四国化工機株式会社 Production unit for vessel blank
JPS63164775A (en) * 1986-12-26 1988-07-08 Matsushita Electric Ind Co Ltd Television signal processing unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6445597U (en) * 1987-09-16 1989-03-20

Also Published As

Publication number Publication date
JPS54136122A (en) 1979-10-23

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