JPS6037069A - Information storage device - Google Patents

Abstract

PURPOSE:To prevent danger to be accessed by a third person, by providing a storage control means for clearing automatically at least a part of storage contents of an information storage part, when a new collating number is set in a collating number storage part. CONSTITUTION:When a card 19 is inserted into a master machine, a data signal input/output terminal 28a, a control signal input/output terminal 28b, and a two power source input terminal 28c are connected, and when the number is collated and conforms, the card can be used as usual. If the number collation is unsuccessful four times or more, an information data storage in an information storing circuit 22 is cleared. When a collating number setting mode start signal is sent by operating a mode selecting key from the master machine in order to register a new collating number, warning that information in the information storing circuit 22 is erased is displayed, and when it is necessary to protect the information, its processing is executed. Subsequently, information data in the information storing circuit 22 is erased automatically, and a new collating number is stored by inputting it. In this way, it is prevented to utilize storage information by changing a collating number.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information storage device equipped with an information storage section constituted by a semiconductor storage circuit, and more specifically, to an information storage device including an information storage section configured by a semiconductor storage circuit, and more specifically to an information storage device that takes into consideration the confidentiality of information stored in the storage section. It is related to storage devices.

Conventionally, so-called sequential access memories such as magnetic tapes, magnetic cards, or floppy disks have been most commonly used as storage media for information data in various systems using electronic information processing devices such as computers. ing. However, the information stored on the storage media described above can be completely prevented from being read, as the stored contents can be read relatively easily by a person familiar with the technology using an appropriate reading device. It's hard to do! Because it is a public transportation system, a-zushi is also not suitable as a storage medium for information that requires secrecy.

On the other hand, in recent years, so-called built-in ICs have been developed in which a semiconductor chip is embedded in a card body made of plastic material, and information data is written and stored in the semiconductor memory circuit. Information storage systems using storage media are also beginning to be put into practical use. In the information storage system described above, a verification number (PIN, password, etc.) is set in advance to maintain confidentiality, and only a specific person who knows the verification number can access the verification number from outside. A so-called secret maintenance type information storage system, which is equipped with a control means so that the information data stored in the semiconductor storage circuit can be accessed by inputting information, and necessary information can be extracted and used. has also been proposed.

However, in the conventional confidential information storage systems using IC built-in storage media as described above, the system is generally configured on the assumption that the verification number will not be changed during the operation stage of the user. When it becomes necessary to change the information, it is very difficult and inconvenient to do so. Furthermore, if the system is simply configured to allow the verification number to be changed, there is a risk that a third party may change the verification number in advance and then access and retrieve the stored information using the changed verification number. becomes unavoidable. Furthermore, even if the information storage system is configured on the premise that the reference number will not be changed during operation by general users, someone with some knowledge of the technology may change the reference number in advance. Write down 1 using the changed reference number. It is clear that it is not desirable that there remains a risk that the a information may be accessed and extracted.

The present invention solves the drawbacks of the conventional secret-keeping type 1n report (and Q device) described above, and the purpose of the present invention is to provide storage information that is free from the risk of being accessed by a third party. The purpose is to provide a storage device.

Hereinafter, the present invention will be explained in detail according to the drawings.

1 and 2 are a schematic structural diagram and a system block diagram, respectively, of an information storage device according to an embodiment of the present invention. The information storage device 1g of this example is composed of a base unit 6 shown in a perspective view in FIG. 1(a), and an IC built-in car 1''I9 shown in a plan view in FIG. 1(b). , the main device 6 has a display section 7 made of a dot matrix liquid crystal display device, an input keyboard 8, and an IC built-in card insertion section 9. It has a circuit mounting section 29 including one or more IC chips, and four connection terminals consisting of a data signal input/output terminal 28a, a control signal input/output terminal 28b, and two power input terminals 28C. Note that the four connection terminals are exposed from the card body made of plastic material, and when the card 19 is inserted into the insertion section 9 of the base unit 6, the response on the base unit 6 side described later is The device is configured to be connected to the connecting terminal of the device.

Next, FIG. 2 is a block diagram showing the outline of the system configuration of the information storage device of this example, in which (a) shows the base device 6 side, and (b) shows the card 19 side.

mtA' 6 (ilJ Ha, m! CPUIO consisting of unit, control unit, etc., and RA for storing data and programs loaded from outside.
MII, ROM12 that stores monitor programs, routine programs, etc., and I10 for input/output control.
A controller 14 (!:) for display control is connected to the board 13 and the video RAM 11a section occupying a part of the address area of the R A Mll, and includes a driver section of the display section 7 described above. It is composed of a display section 7 connected to the 110th board 3, an input keyboard 8 connected to the 110th board 3, and a power supply circuit 16 for supplying power to each of the aforementioned blocks.
This is a hash line connecting PUIO and each block. Further, a data signal input/output terminal 18a and a control signal input/output terminal 18b are also connected to the I10 port 13, and a power supply terminal 18c is also connected to the power supply circuit 16.

On the other hand, the card 19 side has a configuration in the form of a so-called microcomputer, including a CPU 20 consisting of an arithmetic unit 1, a control unit, etc., a ROM 21 that stores programs, and a ROM 21 for checking verification slips, etc. An information storage circuit 22 consisting of a so-called non-volatile semiconductor memory 1,a circuit such as MNOS for storing data and information data, etc., and an I10 port 23 for input/output control between the base unit 6 and It is composed of a driver 24 for applying a driving voltage for memory writing and memory erasing to the 111i report 1 circuit 22, a power supply circuit 26 for supplying power to each block on the card 19 side, etc. There is also CPU2
0, ROM21, information storage circuit 22, I10 port 23
A pass line 27 is provided between I and I.
The above-mentioned data signal input/output terminal 28 is connected to the 10-bot 23.
a and a control signal input/output terminal 28b are connected, and the aforementioned power input terminal 28C is connected to the power supply circuit 2B.

Note that when writing new memory into the information storage circuit 22, erasing memory, or changing the memory contents, a control signal sent from the CPU 20 via the control bus of the pass line 27 is used. Accordingly, a write drive signal or an erase drive signal is generated by the driver 24, and these signals are sent to a specified address in the information storage circuit 22 (the address specified by the address bus of the pass line 27). is configured to be applied. However, in the following description, when writing, erasing, changing, etc. of the memory of the information storage circuit 22 is mentioned, the operation of the driver 24 and the like will not be explained each time.

Note that in FIGS. 2(a) and 2(b), the power supply circuit 16.
The power supply lines from 26 to each other block are shown by broken lines, and the path lines 17 and 27 actually consist of a data bus, an address bus, and a control bus, but the diagram is simplified. For this reason, illustration of the distinction between each bus is omitted.

When the card 19 is inserted into the insertion section 9 of the base unit 6, the data signal input/output terminal 28a is used as the data signal input/output terminal 18a, and the control/roll signal input/output terminal 28b is used as the control signal input/output terminal. For tj? H child 18b and power input terminal 28C are power supply O::1 child 18c
and are configured to be electrically connected to each other. Therefore, in this example, the control 1~roll signals and data signals are transferred between the base unit G side and the card 19 side via the I/○ board 1/13. This is done through the connection between the output terminals 18a and 28a and the connection between the control signal input/output terminals 18b and 28b. Note that when the above-mentioned mutual signal transfer is performed, I1 on the data sending side
The 0 port converts the signal from parallel to serial before sending it out, and the I10 port on the data receiving side converts the received signal from serial to parallel. However, in the following, when explaining the specific signal transfer between the base unit 6 side and the card 19 side, we will explain the route through which the signal is transferred in each case. The following shall be omitted.

In addition, in this example, the card 19 side has a power supply terminal 1
It is configured such that power is supplied from the parent ta6 side via the terminal 8C and the power input terminal 28c.

Next, FIG. 3 is a flowchart of the main routine program regarding the information storage device of this example, and FIGS. 4 and 5 are flowcharts of the number verification code routine and new verification number registration subroutine, respectively. It is. In each of FIGS. 3, 4, and 5, (a) shows a flowchart of the program stored in the ROM 12 on the base unit 6 side, and (b) shows the flow chart on the card 19 side. 2 is a flowchart of a program stored in the ROM 21. Hereinafter, the operation of the information recorder 1.1 device of this example will be explained with reference to the drawings.

First, the main routine will be explained according to FIG. First, when the card 19 is inserted into the insertion section 9 of the base unit 6, the base unit G side uses the processing such as an emergency interrupt, and the card 19 side receives the card 19 from the base unit 6 and the card 19 through processing such as an emergency interrupt. both sides are 3rd
Controlled by the start stage in the figure. At this point, the main device 6 side waits for an input signal from the mode 1' selection key of keyboards 1-8 to select the job content (step a).
-1), if it is the memory access mode selection signal (step a-2), then the memory access mode start signal is used as the start signal to indicate which job is to be started. Step a-3) to transfer the number to the third party, and then the number verification subroutine (
Proceed to step a-4). On the other hand, the card 19 side also waits for a start signal from the base unit 6 (step b-1), and if each is a memory access mode start signal (
In step b-2), the process proceeds to a number matching subroutine (step b-3). Note that the above memory access mode performs the necessary processing (specifically This mode indicates that a number verification process is to be performed. A detailed explanation of the processing in the above number verification subroutine will be omitted here as it will be described later, but if the access permission state is obtained in the number verification subroutine on both the base unit 6 side and the card 19 side, (Step a-5) involves proceeding to a state in which the intended normal work can be performed in the memory access permission state, and if the access permission state is not obtained, returning to the initial start stage. (step a-4 and step b-4).

On the other hand, if the signal from the mode selection key described above is not a memory access mode selection signal but a verification number setting mode selection signal (step a-6), the base unit 6 uses the verification number setting mode selection signal as the start signal. Step A-7: Transfer the setting mode start signal to the card] and 911ti.
), and then proceeds to a routine for recording a new verification (step a-8).

Also, on the card 19 side, if the star 1- signal from the master device 6 is the verification number setting mode start signal (step b-5), the process proceeds to the new verification number registration subroutine (step b-6). Again, a detailed explanation of the above new verification number registration subroutine will be omitted as it will be described later, but when the new verification number registration returns from the system routine on both the base unit 6 side and card 19, the first start stage will return to.

In this example, if the signal from the mode selection key mentioned above is neither the memory access mode selection signal nor the verification number setting mode selection signal, the system is configured to immediately return to the start stage. This means that when the card 19 is inserted into the insertion section 9, the card 19
This is because even if a mode selection signal for another job unrelated to 9 is input, interruption to that mode is prohibited.

Next, the number verification subroutine will be explained according to FIG. 4. When the number verification subroutine is entered on both the base unit 6 side and the card 19 side, the number verification subroutine enters the fourth stage, which is the start stage in the figure. First, on the card 19 side, it is checked whether the value of M indicating the number of consecutive failures in number verification is 3 or more (step b-11), and if it is 3 or more, the card 19
A memory clear warning signal is transferred to the main unit G side as a standby state signal on the side (step b-12), and if it is less than 3, a normal standby state signal is transferred to the main unit G side as a standby state signal (step b-12). b-13) In any case, the next step is to wait for data transfer of the values of R and S, which will be described later, from the base device 6 side (step b-14). Note that the value M indicating the number of consecutive failures in number verification is stored in a predetermined address in the information storage circuit 22 mentioned above, and as will be described later, it is not possible to perform verification by inputting an incorrect verification number manually. If it fails, the value is counted and amplified (step b-19), but if the correct verification number is entered manually and verification is successful, it is cleared to 0 at that point (
step b-19).

On the other hand, the main unit 6 side waits for the j-text status signal from the card 19 side (step a-11), and if it is a memory clear warning signal (step a-12), this signal is displayed on the display unit 7. If the above number verification fails, the information storage circuit 2
Displays a warning to clear the information data in 2 (step a-13)L, and if the standby state signal is a normal standby state signal, it remains as is, and in any case, the next manual keyboard is displayed. 8 with reference number X, -t- Proceeds to the waiting stage (step a-14). Here, when the reference number is input, a random number R is generated (step a-15) L, and then a function S=f
(A,X.

R) and put the values of R and the result of the calculation into card 1.
9 side (step a-16), and then the process advances to the step of waiting for the determination signal to return from the next card 19 side (step a-17). Note that A above is a type of group number uniquely assigned to a certain group related to a specific company or financial institution, etc. when the information storage device of this example is used within a certain group related to a specific company or financial institution, etc. This data is used to more completely protect against access by people outside the group.

On the other hand, on the card 19 side, from the stage of waiting for the data transfer of the values of R and S from the base unit 6 side (step b-14), when those data are actually received, the function S'=f (
A', X', R) are calculated (step b-15). Here, A' and X' are a group number and a reference number, respectively, which are stored and written in advance in a predetermined address of the information storage circuit 22. If the same intra-group card corresponds correctly to a predetermined intra-group parent device, both group numbers, that is, the value of A' stored in the card 19 and the parent device 6 side. This value is the same as the value of A stored in .

Also, the above-mentioned verification number X entered manually from the main unit 6 side is
If it corresponds correctly to the card 19, the value of both verification numbers, ie, the value of the above-mentioned X, and the value of the verification number

Therefore, if the correspondence between the m device 6 and the card I9 is correct, and the verification number manually entered by the key is also correct, the same data value is substituted as a variable in the same function f on the base device 6 side and the card drawing. Therefore, the calculated value S of the function f on the parent t1!6 side should naturally be equal to the calculated value S' of the function f on the card 19 side. That is, on the card 19 side, in the next step, the above two calculated values S and S
′ are equal to each other (step b-1
6) If they are equal, it is determined that the comparison was performed correctly, and a memory access permission signal is transmitted to the base unit 6 as a 1' signal.

b-17) Clear L and the value of M mentioned above to 0 (
After step b-18), the process returns to the main routine. If they are not equal, it is determined that the matching was not performed correctly, and the value of M mentioned above is increased by 1 (
After step b-19), the process proceeds to a step (step b-20) in which it is determined whether the value of M is 4 or more. Here, if the value of M is 4 or more, the storage of information data in the information storage circuit 22 is cleared (step b-21) L
Further, after transmitting a memory clear execution signal as a determination signal to the base unit 6 side, the value of M is cleared to O (step b-18), and the process returns to the main routine. In addition, if the value of M is less than 4, a verification number re-input designation signal is transferred to the base unit 6 as a determination signal (step b-
23) Then, the process returns to the start stage of the number matching subroutine.

On the other hand, on the base unit 6 side, if the determination signal transferred from the card 19 side is a verification number re-input designation signal (step a-18), a designation to re-enter the verification number from the keyboard is made. is performed on the display section 7 (step a-19), and then the process returns to the start stage of the number verification subroutine.

Also, the judgment signal is not the verification number re-input designation signal mentioned above,
If it is a memory clear execution signal (step a-2)
0), the display section 7 displays that the storage of information data in the information storage circuit 22 has been cleared (step a).
-21) After that, the process returns to the main routine.If the judgment signal is neither the reference number re-input designation signal nor the memory clear execution signal, but a memory access permission signal, the process returns to the main routine. Return to routine.

After returning to the main routine, card 19
Depending on whether or not a memory access signal has been transferred from the side to the base unit 6, it is determined in step 111 whether or not both the base unit 6 side and the card 19 side are in the memory access state as shown in FIG. -5, Step b-4) When the memory access permission state is established, communication tasks in the memory access state, such as display confirmation of the contents of the information data stored in the information record (,1 circuit 22). It is controlled so that it can write new information data, make corrections, and perform calculations, judgments, and other tasks based on the information data.

As described above, in this example, if the act of failing number verification using an incorrect verification number is performed four times in a row, the memory of information data in the information storage circuit 22 of the card 19 is automatically erased. Therefore, access to the information data by someone who does not know the reference number is completely prevented. In addition, in this example, when determining whether the verification number is correct on the card 19 side, the verification number entered manually is not directly transferred to the card 19 side.
The system is configured to transfer the calculated value obtained by substituting the verification number into a predetermined function to the card 19 side, and determine whether the verification number is correct based on the calculated value, but this is not the case with the regular parent. This is to completely prevent the access permission state from being triggered using a device other than device 6.

Next, the new verification number registration subroutine will be explained according to FIG.
This is the starting stage in the figure. First, on the card 19 side, it is checked whether information data has already been stored and written in the information storage circuit 22 (step b-31).
, if it is determined that memory is included, the base unit 6
After transmitting the memory clear caution signal to the side as a standby state signal (step b-32), the process proceeds to the stage of waiting for the next start signal from the base unit 6 side (step b-34), and also as described in 1. If it is determined that a has not been written, a normal standby state signal is transferred to the main unit 6 as a standby state signal (step b-33).After Lk, the main unit 6 is immediately
The stage of waiting for the transfer of a new reference number from the side (step b-3)
Proceed to 9).

On the other hand, when the master unit 6 is actually sent a standby state signal from the stage of waiting for the standby state signal to be transferred from the card 19 side (step a-31), the standby state signal is stored in the memory. Check if it is a clear caution signal (
Step a-32) If it is a memory clear warning signal, if you continue to register a new verification number, the information data in the information storage circuit 22 will be erased. After displaying a caution on the display unit 7 (step a-33) regarding the next inquiry as to whether protection is necessary, etc., there is a step of waiting for an input from the mode selection key (step a-33).
-34), and if it is a normal standby state signal instead of a memory clear caution signal, the process immediately proceeds to a step (step a-38) of waiting for key input for a new verification number.

In the step of waiting for an input from the mode selection key (step a-34), the operator selects the memory retention mode if it is necessary to protect the information data in the information storage circuit 22 from being erased. A memory retention mode selection signal is input using the key for selection, and if erasing is acceptable, a normal mode selection signal is input using the key for selecting the normal mode.

When the memory retention mode selection signal is input (step a-35), the memory retention mode start signal is transferred from the base device 6 to the card 19 (step a-3(i)).
After that, the process proceeds to the number matching subroutine (step a-37) shown in FIG. Immediately after transmitting the mode start signal, the process proceeds to the step of waiting for the input of the key for the new reference number (step a-38). On the other hand, when the card 19 side advances to the step of waiting for the start signal from the base unit 6 side (step -54), it next checks whether the start signal is a memory retention mode start signal. (Step b-35) If it is the memory retention mode I start signal, the card 19111J also proceeds to the aforementioned number verification subroutine (Step b-36). Further, when the normal mode star 1- signal is detected instead of the memory retention mode star 1- signal, the information data in the information storage circuit 22 is automatically erased (step b-3).
7) After that, clear the value of M mentioned above to 0 (step b
-38) The process then proceeds to the stage of waiting for the transfer of the new reference number from the base device 6 side (step b-39).

As described above, the number verification subroutine (step a-37, step b) is executed on the base unit 6 side and the card 19 side.
-36), the same processing as described in FIG. 4 above is performed, so after returning from the number matching subroutine (step a-37), When the process advances to the step of waiting for the number key input (step a-38) and the step of waiting for the rough verification number to be transferred from the base unit 6 side (step b-39),
The state of the information data in the information storage circuit 22 is also determined depending on whether or not the numbers have been verified correctly. In other words, if the number verification can be performed correctly, the information data in the information storage circuit 22 is not erased, but if the number verification cannot be performed correctly, the number verification routine ( It is clear that the information data in the information storage circuit 22 has already been cleared (erased) during the processing in step b-36).

By the way, on the base unit 6 side, when the rough verification number is actually entered manually from the step of waiting for the key input of the above-mentioned rough verification number (step a-38), this new verification number m is data transferred to the card 19 side ( Step a-39) L.

After that, the process advances to a stage (step a-40) of waiting for transfer of execution end verification from the card 19 side.

In addition, on the card 19 side, from the step of waiting for the transfer of the new JJ 4% match number from the master device 6 side (step b-39), the coarse matching number is actually transferred (then the predetermined number in the information storage circuit 22 is After writing the rough verification number into the address of ia (step b-40), transfer the execution completion signal to the main unit G1u11 to indicate that the execution of the new verification number registration has been completed, and then Return to routine.

Furthermore, when the base unit 6 side actually receives the execution end signal from the stage of waiting for the execution end signal in step 1 from the card 19 side (step a-41), the rough verification number is registered on the display section 7. After displaying that the process has ended (step a-41), the process returns to the main routine.

The registration process of the rough verification number is thus completed, and as a result, the new verification number entered manually is stored and held in the memory address predetermined to store the verification number in the information storage circuit 22. Therefore, from now on, in the number verification subroutine, permission to access the information data stored in the information storage circuit 22 cannot be obtained unless this new verification number is used.

In addition, in this example, as mentioned above, if information data has already been stored and written in the information storage circuit 22, it is possible to re-register a new verification number even if this information data is protected from being erased. However, in that case, by passing the number verification subroutine once, only those who know the old verification number can use the verification number while protecting the information data. Since the change is acknowledged, it is impossible for a third party to change only the verification number to a new one before accessing the information.

When passing through the Zunawara number verification subroutine, if you do not know the old verification number, verification will fail.
The information data in the information storage circuit 22 is also automatically cleared (
Step b-21) in Figure 4 will occur, so even if the above-mentioned memory retention mode is selected (steps a-34 and 35) in the new verification number registration routine, one blue report There are no words to protect data.

Note that when you return from the new verification number registration number routine, in order to return to the star 1- stage of the main routine in Figure 3, you can immediately enter the new verification number from that state.
It is possible to move on to processing related to the memory access mode described above.

As described above, according to the present invention, even if a third party attempts to access the stored information after changing the verification number in advance, the C storage information is always automatically cleared when the verification number is changed. Even if you are well versed in information processing technology and receive C, you will already have 1. It's being worn! ! (If you do not know the 1st number, you will not be able to access the stored information at all, and the stored information will be kept completely confidential.

Therefore, for example, even if a card with a built-in IC as in the above-mentioned embodiment is used as a so-called cash card for a financial institution such as a bank, the identification number etc. of a stolen or lost card may be rewritten and fraudulently used. The fear of being used is also eliminated.

In addition, in the above-mentioned embodiment, for those who know the old reference number that was previously used, the stored information stored in the information storage unit is specially protected from being cleared, and furthermore, the verification is performed. Although some efforts have been made to make it possible to change the number to a new one, it is clear that such a consideration does not necessarily have to be provided.

Furthermore, in the above-mentioned embodiment, when determining whether or not the verification number input from the external input means matches the verification number stored in the verification number storage section, the verification number is not directly compared; Although the configuration is such that the determination is made using the calculated value of the function substituted as data, it is clear that the verification number may be used directly to determine the verification.

Furthermore, in the above-mentioned embodiment, the verification number stored in the verification number storage section in the storage circuit is configured to be equal to the verification number inputted from the outside, but the system is constructed by assuming that the two are not necessarily equal. There is no need to configure this; for example, it is possible to configure it so that the two have a certain correspondence relationship and the actual matching between the two is determined based on the correlation between the two. be.

Furthermore, in the above-mentioned embodiment, the reference number storage qB, information storage section, etc. are so-called non-volatile semiconductor memory such as MNOS that can be electrically written and erased. Although it is composed of a circuit, the reference number 1. It is also possible to configure the α section and the information storage section with a RAM, which is a so-called volatile storage circuit, and to configure the RAM 41' so that the RAM is constantly bank-amplified with an auxiliary battery or the like.

In addition, in the above-mentioned embodiment, the overall hardware system for information processing is composed of an IC built-in card and a parent card. Keyboards, etc., which are the only input means for inputting data, are provided separately on the main unit side, but all hardware, such as the above-mentioned verification number storage section, information storage section, external input means for verification numbers, etc. The present invention can also be applied to a system using a unitary information processing device having a built-in hardware system or a portable information device, such as a portable computer.

It is also possible to use the information storage device according to the present invention by connecting it to another large computer or the like online. For example, as in the above-mentioned embodiment, the overall hardware system for information processing is an IC card built-in card. Even in the case where the main unit is configured with a main unit and a main unit, the main unit can be further connected to another large computer or the like.

It is also possible to divide the information storage section into a plurality of blocks, etc., and to set a different verification number for each block.

[Brief explanation of the drawing]

1 to 5 show an information storage device according to an embodiment of the present invention, FIGS. 1 and 2 are a schematic structural diagram and a system block diagram, respectively, and FIG. 3 is a main routine program. Figures 4 and 5 are the flowcharts for the number verification subroutine and the routine for registering a new verification number, respectively. , also (b
) indicates the IC built-in card side. 6--------Base unit, 7--------Display section, 8--
--- Single person keyboard, 9 --- I C
Built-in card insertion section, l0120--CPU, 1l
-----RAM, 11'a'---Video R
AM 11! , 12.2l---ROM, 1
3.23--I/O board 1.14--11--controller, 16.26---1 power supply circuit, 17.27--pass line, 18a, 28
a---Data signal input/output terminal, 18b, 28b-
・-Control signal input/output terminal, 18 C-1--
---Power supply terminal, 19--IC built-in card, 2
2--------1 information storage circuit, 24--------driver, 28 C-----Power input terminal Fig. 1 (G) Mutual (b) (Q) Fig. 3

Claims (1)

[Claims] (1) A verification number storage section and an information storage section comprising a semiconductor memory circuit, an input means for inputting a verification number from the outside, and a verification number inputted from the input means as a verification number in the verification number storage section. a determination means for verification; a memory access control means for permitting access to the information storage section only when verification is confirmed by the determination means; and when a new verification number is set in the verification number storage section. An information storage device comprising: storage control means for automatically clearing at least part of the storage contents of the information storage section.