JPS6036929Y2 - television receiver - Google Patents

Description

[Detailed description of the invention] The present invention is concerned with a television receiver that displays a reduced image of another channel broadcast on the image reception screen of one channel broadcast. This is to eliminate missing screens due to misalignment.

For example, in a TV receiver that displays a reduced B channel broadcast screen on an A channel broadcast screen, conventionally, the B channel signal is alternately written into two memories, one field at a time, and then read out alternately. There is one that is inserted into a predetermined section of the A channel signal.

That is, two memories, each made up of a charge transfer element, such as a BBD, are used, and first, a signal of, for example, an odd field of the B channel is written into the first memory.

This writing is timed based on the horizontal and vertical synchronization signals of the B channel signal.

Also, when reducing the B channel screen to, for example, 1/3 and displaying it on the A channel screen, 1/3 of the scanning lines
Writing is done at the rate of books.

Therefore, if the total number of scanning lines is 525, these memories have ``''-'3=88 lines.2.

BBDs are connected in parallel.

When an odd field signal is written to the first memory, an even field signal is then written to the second memory, and while this writing is being performed, the first memory is being read.

This reading is timed based on the horizontal and vertical synchronization signals of the A channel signal in order to insert the read signal into a predetermined section of a certain field of the A channel.

Further, in this case, reading out each BBD, that is, reading out in the horizontal direction, is performed at a speed three times as fast as the normal horizontal scanning amount.

Immediately after reading the first memory and writing to the second memory, the next odd field is written to the first memory, and the second memory is read based on the synchronization signal of the A channel signal. It will be done.

In this way, by repeating the writing and reading of the two memories alternately and inserting the read signal into a predetermined section of the A channel signal, the B channel screen is displayed within the A channel screen. It can be reduced and displayed.

Therefore, the two memories in such a receiver are:
Writing is performed based on the synchronizing signal of the B channel, and reading is performed based on the synchronizing signal of the A channel.

However, in actual television broadcasting, vertical synchronization signals between two channels are usually not coincident in time.

Depending on the degree of deviation between the two vertical synchronizing signals, the following inconvenience may occur.

For example, consider a case where the vertical synchronizing signal VDA of the A channel and the vertical synchronizing signal VDB of the B channel are shifted as shown in FIG.

First, store the B channel 1 field signal in memory 1.
is written based on VDB.

When this writing is completed, a signal ◎ is written to the memory 2.

During this writing, the signal (2) of the memory 1 is read out, and this reading starts at a time T after the VDA of the A channel is used as a reference.

While this reading of the memory 1 is being carried out, the writing of the signal (2) in the memory 2 is completed, and then the writing of the signal 0 is performed.

At this time, the reading of the signal ■ from the memory 1 has not yet been completed.

Therefore, if reading is stopped and signal 0 is written to memory 1, the lower part of the B channel screen fitted into the A channel screen will be missing.

Furthermore, if the signal 0 is written after the reading of the signal ■ is completed, a part of the signal ◎ will be missing.

Similarly, a similar problem occurs when the signal 0 is written after the signal ◎ has been written while the signal ◎ is being read.

While reading one memory like this, B
When a VDB of a channel is received, a part of the screen to be inserted will inevitably be missing.

The present invention is intended to solve the above problems, and embodiments of the present invention will be described below with reference to the drawings.

In FIG. 2, a video signal of channel A broadcasting is applied to input terminal 5, and a video signal of channel B broadcasting is applied to input terminal 6.

The A channel signal is applied to the contact a of the switch 7, and is also applied to the synchronization separation circuit 8 to generate the horizontal synchronization signal HD,
and vertical synchronization signal VDA are separated.

The B channel signal is applied to the four memories 1, 2, 3, and 4 via switches 9 and 10, and is also applied to the synchronization separation circuit 11, where the horizontal synchronization signal (IDB) and vertical synchronization signal VDB are separated. Ru.

Memory 1. 2.3. Each village of 4 has a memory select signal from the control circuit 12, a shift clock,
One field of the B channel signal is written and read at a predetermined timing using the write clock and the read clock.

The above various signals and clocks applied from the control circuit 12 to the memory 1.2.3.4 are applied to HDAlVDA, HD8 and V
It is output at a predetermined timing based on each DB synchronization signal.

The signal read from the memory 1.2.3.4 is sent to the clock trap circuit 1 through switches 13, 14 and 15.
After the clock frequency component is removed by applying the signal to the switch 6, the signal is applied to the contact point of the switch 7 through an amplifier 17.

The switch 7 can switch between contacts a and b in response to a switching signal applied from the control circuit 12 that designates the fitting location of the screen.

At the output terminal 18, a composite signal is obtained in which the B channel signal is permanently inserted into a predetermined section of the A channel signal.

In this embodiment, for example, B is displayed at the bottom right of the A channel screen.
The channel screen shall be reduced to 1/3 and displayed.

Also memory 1. In each village of 2.3.4, a signal obtained by reducing one field of the B channel signal to 173 in the vertical direction is written.

For this purpose, switches 9 and 10 are closed to contacts a and b every 3H (H: horizontal scanning period).

Also, switches 13 and 14 have contacts a for each field.

b, and the switch 15 closes contact a every two fields.
, b.

All these switchings are done by the control circuit 12)
This is performed by a switching signal formed based on [)VDA1HDB1■DB.

Further, a memory selector signal is applied to each memory to select each of the memories 1, 2, 3, and 4 at a predetermined timing for writing or reading.

This memory selector signal is formed based on the pulses shown in FIG. 3 obtained from the output terminals u, v,
2. The circuit of the inverter 23 is configured as shown.

Memories 1 and 2 are each configured to write 1/2 of a signal obtained by reducing one field of the B channel signal to 173 in the vertical direction.

For this purpose, each of the memories 1 and 2 has a configuration in which 44 BBDs are connected in parallel.

The memory 3.4 is also composed of 44 BBDs in the same manner as described above.

Incidentally, one BBD may be made up of, for example, 64 pieces.

Next, the operation of the above configuration will be explained.

In this embodiment, writing and reading from memories 1, 2, 3, and 4 are performed at the timing shown in FIG. 3.

First, 1n' signals of a certain field of the B channel signal are written into memories 1 and 2.

This writing is performed as follows. First, switch 9
is closed to contact a, and the signal of the third scanning line of a certain field of the B channel signal is written into memory 1.

Then, the switch 9 is closed and the signal of the sixth scanning line is written into the memory 2.

Next, the switch 9 is closed to contact a again, and the signal of the ninth scanning line is written, and then the signal of the first scanning line is written to the memory 2.

By repeating the above operations, memory 1,
2, each signal is written alternately to the three scanning lines of the signal ■, and in the end, each memory 1 and 2 has 1/1/1 of the signal -1, respectively.
The signals of two fields each are reduced to 173 in the vertical direction and written.

When this writing is completed, the signal ■ for the next field is input, but it is not written.

When the field (2) of the A channel is started in the middle of the field of this signal (2), the memory 1 is read out after a time T has elapsed since the VDA.

This reading is performed in the horizontal direction at three times the IH speed.

The read signal is taken out through the contact a of the switch 13, and is further applied to the output terminal 18 through the contact a of the switch 15, the clock trans 1 circuit 16, the amplifier 17, and the contacts of the switch 7.

The switch 7 is switched between contacts a and b at a predetermined timing in response to a signal from a control circuit 12 that specifies the location where the screen is to be fitted.

Therefore, the output terminal 18 outputs B to a predetermined section of the ■ field of the A channel signal (for example, the section corresponding to the lower right of the screen).
Reduced channel signal - 1/2 of the signal
A composite signal with one field inserted is obtained.

When the signal -W field of the B channel signal starts while the memory 1 is being read, the signal ◎ is written to the memories 3 and 4 based on the VDB.

This writing is performed in the same manner as the writing into the memories 1 and 2 described above, and by switching the switch 10, 1n' times the zero number are written.

During this writing, when the ■ field of the A channel begins, reading from the memory 2 is performed after a time T has elapsed from that VDA.

The read signal is taken out from the contact point of the switch 13, inserted into a predetermined section of the field 2 of the A channel signal, and applied to the output terminal 18.

At this time, the signal read from memory 1 and inserted into the ■ field and the signal read from memory 2 and inserted into the ■ field are in a relationship in which the scanning lines interlace, and this causes the B channel signal to be inserted into the ■ field. The screen is reduced to 173 and completed.

Next, the 0x field of the B channel starts, but this is not written, and during this time, memory 3 is read and A
It is inserted into the ■ field of the channel.

Then, the B channel signal [F] is again stored in memory 1.
．． During this time, memory 4 is read out and inserted into the ■ field.

As mentioned above, memories 1 and 2 have signals ■, ■, ■...
... is written, and signals ◎, ■, are written in memories 3 and 4.
■... is written, and the signals ■, ■, [F]...
The field of ... will be skipped.

During this skipped field period and while writing to the two memories, the other two memories are read, reducing the 172-field screen of the B channel to 173 in the 1-field screen of the A channel. It can be fitted.

Incidentally, the signals ``■'' and ``copy ■'' may be written in the memories 3 and 4.

Figure 4 shows a timing chart of pulses appearing on the u, v, It is.

As described above, according to the present invention, for example, ■DB and V
Even if the DA is shifted as shown in FIGS. 1 and 3, there will be no problem and no image will be missing.

[Brief explanation of the drawing]

Figure 1 is a diagram to explain that image loss occurs due to deviation of the vertical synchronization signal, Figure 2 is a circuit diagram showing an embodiment of the present invention, and Figure 3 is a diagram showing the writing and reading of three memories. Figure 4 is a diagram to explain the timing of
5 is a time chart for obtaining the memory selector signal shown in the figure. In addition, in the symbols used in the drawings, 1...
・Memory, 2...Memory, 3...
Memory, 4...Memory, 5...A
Channel signal input terminal, 6...B channel signal input terminal, 7...Switch, 12...
...control circuit, 18...output terminal.

Claims (1)

[Scope of Claim for Utility Model Registration] In a television receiver that displays a reduced image receiving screen of a second channel broadcast in a receiving screen of a first channel broadcast, one field of the second channel broadcast. A first memory into which a signal of a predetermined scanning line among the signals of the one field is written; a second memory into which a signal of a predetermined scanning line different from the predetermined scanning line among the signals of the one field is written; means for alternately writing into the memory and writing into the second memory for each scanning line; a third memory into which signals of a predetermined scanning line among the signals are written; a fourth memory into which signals of a predetermined scanning line different from the predetermined scanning line among the signals of the other fields are written; Means for alternately writing into the memory and writing into the fourth memory for each scanning line; means for sequentially reading out the first to fourth memories; and means for sequentially reading out the first to fourth memories; A television receiver comprising means for sequentially inserting into predetermined intervals of each field signal of a first channel broadcast.