JPS6031678A - Binarization circuit - Google Patents

Abstract

PURPOSE:To obtain a binary signal regardless of periodical fluctuations of an input signal, by impressing the output signal of a positive/negative peak signal holding circuit on one input terminal of a comparison circuit and by impressing an intermediate-level signal of a voltage division circuit on the other input terminal to compare both signals. CONSTITUTION:When output voltages V1-V3 of a voltage division circuit indicate waveforms as shown in the diagram, V1>V3 is obtained, and when a negative peak holding circuit OP2 obtains an output Vl which is produced by negatively peak-held V1, an input signal at one terminal of an arithmetic amplifier OP1 indicates the intially broken line in the diagram. When waveforms of the input signal change into Vl<V3, Vh is obtained as the output of a positive holding circuit OP3. At this time, Vh attains to the input signal of the OP1 because of Vl<V1, the negative peak holding circuit Vl attains to the input signal of the OP1. The changing direction of the input signal amplitude and the magnitudes of Vl and Vh supply the input signal Vl or Vh alternately. When this signal is used as the reference signal of the OP1 and compared with the signal of V2, a binary output is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that can binarize an analog signal such as a read signal of a bar code reader with high performance.

In order to identify large quantities of products in supermarkets and the like, bar codes displayed on product packaging are optically read and processed by electronic computers. Therefore, the analog signal read by optical-to-electrical conversion must be converted into a binary signal. Conventionally, the following circuit has been used as a binarization circuit for this purpose. In FIG. 1, an analog input signal is applied from a terminal IN and input to one terminal (''-) of an operational amplifier op, which operates as an amplitude comparator. The input signal is applied to the other terminal (-) of the operational amplifier op via a diode D3 and a resistor R. At this time, as shown in FIG. 2, when the amplitude of the input signal e is increasing, the capacitor C starts to be charged via the forward resistance r of the diode D3, and becomes as shown in e, and is maintained at a predetermined value. . (Positive peak hold operation) The output e of the operational amplifier OP is a predetermined value "1". el gradually becomes smaller, and e2. When e3 becomes equal, the output of the operational amplifier OP changes from 1'' to On. At this time, the amplitude of the input signal e1 increases again, but when it decreases again to a value below the forward voltage Vd of the diode D3. ,
The output of operational amplifier OP does not become "1", that is, el
It is not possible to obtain a binary output due to amplitude changes. Since barcode readers differ in their proficiency levels, the amplitude of the input signal varies greatly, and this circuit has the disadvantage of poor accuracy.

In addition, the forward resistance of the diode D3 and the capacitor C
The time constant for the forward current obtained by the product of the diode DI, the time constant for the reverse current obtained by the product of the reverse resistance of D2 and the capacitor C was selected so that it matches the signal with a fast period among the input signals. When a signal with a slow period or a signal with a wide space among codes is handled, the period of the output "O" of the operational amplifier op is shortened from t to t' as shown in FIG. Conversely, as shown in Figure 4, when the time constant is adjusted to a signal with a slow period or a signal with a wide space, the time width t of "O" becomes t' for a signal with a fast period or a signal with a narrow space. It becomes wider. The conventional circuit shown in FIG. 1 has a drawback that it cannot sufficiently follow changes in signal amplitude because it uses diodes in the capacitor charging/discharging circuit.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a circuit which can overcome the above-mentioned drawbacks and can perform binarization with sufficient accuracy even when the input analog signal is very small or when the repetition period of the input signal changes significantly.

Embodiments of the present invention shown in the drawings will be described below. Fifth
The figure is a circuit diagram of an embodiment of the present invention, in which the analog signals applied to the input terminals are divided by a voltage divider VD, in this example Vl, V2 . It is divided into three for each voltage of V3. Vl is equal to the input voltage, V3 is the lowest voltage, V2 is equal to Vl
, V3. Operational amplifier OP2. In OP3, Vl and V3 are applied to one terminal (+), respectively.

Also OF2. Each OF2 has a time constant that can sufficiently hold the peak value of the input signal. The OF2 side constitutes a negative peak signal hold circuit, and OF2 constitutes a positive peak signal hold circuit. OPI indicates an operational amplifier that operates as an amplitude comparator for the signal applied between the terminals (+) and (-).
The output voltage of OF2°OF2 is applied as described later.

C indicates a capacitor and corresponds to C in FIG.

The operation of the circuit shown in FIG. 5 will be explained with reference to the waveform diagram in FIG. 6. Each output voltage V1. of the voltage divider circuit VD. V2.
When V3 has the waveform shown in Figure 6, yl
>v3 and the negative peak hold circuit OP2 obtains the output ■A obtained by negative peak holing of ■1, the output of the negative peak hold circuit OP2, that is, the input signal at the terminal (-) of the operational amplifier OPI is the sixth It will look like the original broken line in the figure.

The input signal waveform changes to V-11! <V3, the output vh obtained by bolding the positive peak of v3 is obtained as the output of the positive peak hold circuit 0'P3, and at this time ■7 <
Since Vh, vh becomes the input signal to the terminal (-) of OPI. vh changes as shown by the broken line in FIG. Next, when Vh > Vl, the negative peak hole 1-° circuit V
, E become the input signals of OPl.

The input signal to the OPI alternately gives V, ε, and vh depending on the direction of change of the input signal amplitude and the magnitudes of V, , Z, and vh. This signal is used as the standard for OPl and is compared with the signal of 2, resulting in "1" as shown in FIG.

A binary output of "0" is output from the OP1 output terminal No.2.

When selecting the negative resistor 41 for setting the voltage in (3) in Fig. 5, consider the amplitude on the right side of the peak in Fig. 6, and make sure that the forward voltage of the diode is 0.7 V or less, or t+sL;! Even if the input signal contains 911 sounds, they can be identified and selected so that a 2 (pointed output) can be obtained. The following characteristics are determined by the characteristics of each positive peak hold circuit at the rising edge and by the characteristics of the negative peak hold circuit at the falling edge.

And since the amplification degree of the operational amplifier is extremely large,
The follow-up characteristic of the circuit shown in FIG. 5 is also very good, and a binarized signal can be obtained regardless of the periodic fluctuation of the input signal.

In this way, according to the present invention, although the configuration is relatively simple, it is possible to obtain an accurate 2I chastization signal even when the amplitude of the input signal to be converted into a z-value is small or there is a periodic variation.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional binarization circuit, FIGS. 2 to 4 are diagrams explaining the operation of FIG. 1, FIG. 5 is a circuit configuration diagram of an embodiment of the present invention, and FIG. The operation explanatory diagram of FIG. 5 is shown. I N - Human power signal terminals OP, OPI, OP2, 0P3 - Operational amplifier DI, D2
．． D3-Diode C-Capacitor VD-Voltage divider Patent applicant: Tohoku Ricoh Co., Ltd. Agent Patent attorney: Eisuke Suzuki - Tsukune Ichisho (spontaneous) February 4, 1981 Patent Application No. 139855 2 , Name of the invention Binarization circuit 3, Relationship with the case of the person making the amendment Patent applicant 41: Place Miya j+) 1 name of Nakamei Shinmeido 3, Shibata-cho, Shibata-gun, Prefecture Representative of Tohoku Ricoh Co., Ltd. Various amounts Kanji 4 , Agent address: 2-13-36 Yoyogi, Shibuya-ku, Tokyo, Number of inventions to be increased by amendment: None 7, Subject of amendment: Column B for detailed explanation of the invention in the specification, Contents of amendment: As attached (1) Details 2nd page, line 18, -1 is changed to ``e'', as in re+.
2,” he corrected. (2) In the second to third lines of page 4 of the specification, "The conventional circuit is for the diode used in the charging/discharging circuit of the capacitor" has been corrected to "The conventional circuit is for the capacitor used in the charging/discharging circuit." do.

Claims (1)

[Claims] In a binarization circuit that compares an analog signal to be binarized with a predetermined level to obtain a binarized signal, the analog signal is applied to a voltage divider circuit that obtains three outputs at different voltage division ratios, and the voltage divider circuit The negative peak signal hold circuit to which the highest level signal of ? is applied and the lowest level signal strength of the voltage divider circuit? A positive peak signal holding circuit is applied, and a comparison circuit is provided, and one input terminal of the comparison circuit receives the positive peak signal holding circuit output when the input signal amplitude is increasing, and receives the output from the positive peak signal holding circuit when the input signal amplitude is increasing. When the voltage is small, a negative peak signal hold circuit output is applied, an intermediate level signal of the voltage dividing circuit is applied to the other input terminal, and the comparison circuit output is a binary output signal. Binarization circuit.