JPS6031647A - Data processor - Google Patents

Abstract

PURPOSE:To designate any one of an instruction reading request signal and a data reading request signal smoothly in accordance with the number of instructions by providing a data processor with an instruction register for holding the selecting conditions of the instruction reading request signal and the data reading request signal. CONSTITUTION:An instruction request signal generating circuit 4 monitors whether an instruction is accumulated in an instruction prereading buffer 2 or not, and if there is a space, sends an instruction request signal to a signal line 21. Subsequently, an instruction set up in an instruction register 5 is decoded by a decoder circuit 6, and when an operand data is requested, an operand data request signal is outputted to a signal line 22. When the operand data request signal is simultaneously sent to the signal line 21, any one of the request signals is selected and executed in accordance with the number of effective bits in the instruction prereading buffer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an instruction reading method and an operand data reading method for a data processing device.

(Prior Art) Conventionally, when reading an instruction and reading operand data, the same signal line is used to send a request signal.
Both signals were controlled to prevent them from colliding with each other. However, in computers that pursue higher speeds, a smooth flow of instruction execution is realized by prefetching instructions and storing them in a batcher. In addition to reducing the burden, it also achieved higher performance processing. However, in this case, the reading of the instruction and the reading of the operand occur asynchronously, so it is necessary to avoid conflict between the two.1 As a countermeasure, a method is adopted that gives priority to reading the operand data. was. With this method, the reading of instructions always has to wait, and when there is little storage time! If there is not enough space, it will interfere with the execution of the next instruction, which has the disadvantage of hindering smooth instruction execution.

(Object of the Invention) An object of the present invention is to eliminate the above drawbacks by providing an instruction register for holding selection conditions for an instruction read request signal or a data read request signal, so that both occur at the same time. It is an object of the present invention to provide a data processing device configured so that, in the case where the priority order is not fixed, one of the instructions can be smoothly specified according to the number of already accumulated instructions.

(Structure of the Invention) A data processing device according to the present invention includes a storage device, an instruction prefetch buffer, an instruction address register, an instruction request generation circuit, an instruction register, a decoding circuit, and a request signal selection circuit. It is.

The storage device is for storing at least a plurality of instructions. The instruction prefetch buffer is used to prepare and store at least one or more instructions from the storage device before execution. The instruction address register is used to specify the address under an instruction in a storage device in which instructions to be stored in the instruction prefetch buffer are stored. The instruction request generation circuit generates an instruction request signal for requesting an instruction from the instruction address of the storage device when the contents of the instruction prefetch buffer are empty, and also generates an instruction request signal for requesting an instruction from the instruction address of the storage device. It is used to count the number of instructions by the number of valid bits. The instruction register is for receiving the above instructions from the instruction prefetch buffer. The decode circuit is for generating an operand data request signal requesting data from the storage device according to the contents of the instruction register. The request signal selection circuit selects the instruction request signal when the instruction request signal and the operand data request signal are generated at the same time and the number of instructions accumulated inside the instruction request generation circuit is smaller than a predetermined number. This is to give priority to the operand data request signal when the numbers are equal or larger.

(Example) Next, the IC of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention.

In FIG. 1, 1 is a storage device, 2 is an instruction prefetch buffer, 3 is an instruction address register, 4 is an instruction request generation circuit, 5 is an instruction register, 6 is a decode circuit, 7 is a request signal selection circuit, and 8 is a data address. 9 is a data register, and 10 is an arithmetic/general-purpose register circuit.

In FIG. 1 showing an embodiment of the present invention, an instruction prefetch buffer 2 is composed of a plurality of registers and can store a plurality of instructions. By preparing these in advance before executing an instruction, it is generally possible to execute the instruction smoothly. The instruction request signal generation circuit 4 monitors whether or not instructions are stored in the instruction prefetch buffer 2. Since all areas are not filled with instructions, if there is an empty area, the pressure is increased on the signal line 21. It sends a command request signal to the If there is no operand data request signal on the output signal line 22 from the decode circuit 6 for decoding the contents of the instruction register 5, the request signal selection circuit 7 transfers the instruction request signal on the signal line 21 to the main memory 1. The request signal is sent to the signal line 24 as a request signal.

The data on signal line 25 indicates to storage device 1 whether the current request signal is a command or an operand data request. When the main storage device 1 receives the verification that it is an instruction request, it uses the corresponding data inside the storage device 1 as an instruction according to the address specification of the instruction address register 3 that was set at the same time as above.
Send to instruction prefetch buffer 2. If all registers inside the instruction prefetch buffer 2 are filled with instructions, the instruction request signal generation circuit 4 suppresses the instruction request. When execution of one instruction is completed, the next instruction is taken out from the instruction prefetch buffer 2 to the instruction register 5. This empties one or more registers in the instruction prefetch buffer 2, so that an instruction request signal is generated on the signal line 21 again, causing a request to the storage device 1. The instruction set in the instruction register 5 is decoded by a decode circuit 6 and executed. However, when data inside the storage device 1 is required as operand data, the decoding circuit 6 sends out an operand data request signal onto the signal line 22. When no command request signal is sent on the signal line 21, the request signal on the signal line 24 is input to the storage device 1 via the signal line 22 as an operand data request.

Specifically, when request signals are simultaneously sent on the signal line 21, the request signal selection circuit 7 sends a signal on the signal line 23 that is used to display the number of empty registers constituting the instruction prefetch buffer 2. According to the priority designation control signal of
Assuming that the above request signal is an instruction request signal or an operand data request signal, either one is selected. Signal line 2
When the priority designation control signal above 3 specifies an operand data request, the operand data is requested by the request signal, and at the same time, according to the contents of the data address register 8,
The internal data of the corresponding storage device 1 is stored in the data register 9.
Vc is sent out.

In this embodiment, the address signal lines 33, 34, instruction or data signal lines 31, 32, etc. are individually connected to the main memory device 1, but the signal line 25 indicates that they are instructions or operands. is displayed and the corresponding data is selected inside the storage device 1. 〇 FIG. 2 shows the structure of the instruction destination bit buffer 2, the instruction request signal generation circuit 4, and the request signal selection circuit 7 shown in FIG. It is a block diagram showing details. In FIG. 2, 251 to 54 are first to fourth internal registers, 65 is a selector, 41 is a valid bit counting circuit, 42 is a NAND gate, 43.4
4 is the first and second AND gate, 45.46 is α・
R gate, 47 is a negative gate, and 55 to 58 are valid bit signal lines.

In FIG. 2, the instruction destination buffer 2 is made up of first to fourth internal registers 51 to 54, and one valid bit 55 to 58 is prepared for each register. When an instruction is input, the corresponding valid bit is set, indicating that the instruction exists inside each register 55-58.

The command is selected by the selector 65 via signal lines 61 to 64 and transferred to the command register 5. The corresponding buffer may have any configuration as long as it has the F'IFO method.b0 In the instruction request generation circuit 4, by adding an instruction valid bit to the NAND gate 42, an instruction request is sent on the signal line 21. A signal is sent out. The above is a circuit that sends out an output if at least two or more of the valid bits 55-58 are "off". The request signal selection circuit 7 transfers the request signal onto the signal line 24 when the priority designation control signal on the signal line 23 is “on” and the command request signal on the signal line 21 is “on”. At the same time, the request signal on the signal line 25 is turned off,
This indicates that the request signal is a command. At this time, even if an operand data request is output on the signal line 22, it is ignored. If three or more valid bits are "on", the priority designation control signal is "off". At this time,
When both request signals go "on" at the same time, the signal on signal line 25 goes "on", indicating a request for operand data. The operand data read in FIG. 1 is used by the arithmetic/general-purpose register circuit 10 via the data register 9 to execute an instruction.

(Effects of the Invention) As described above, the present invention includes an instruction register for holding the selection conditions for the instruction read request signal and the data read request signal, so that the instruction and operand data can be exchanged. If read requests occur simultaneously,
This has the advantage of being able to smoothly designate any one of the commands that has already been stored, and to smoothly process the command execution without delay.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. FIG. 2 is a block diagram showing details of the instruction prefetch buffer, instruction request generation circuit, and request signal selection circuit in FIG. 1. 1...Memory money 2...Instruction prefetch buffer 3...
・Instruction address register 4...Instruction request generation circuit 5-instruction register 6...
Decode circuit 7...Request signal selection circuit 8...Data address register 9...Data register 10...Arithmetic/general-purpose register circuits 51-54...Internal register 65...Selector 4
1... Effective bit counting circuit 42... NA, ND gate 43.44... AND gate 45.46... OR gate 47... NOT gate 55
~58... Effective bit signal line patent applicant Hisashi Inoro, agent for NEC Corporation, patent attorney

Claims (1)

[Claims] a storage device for storing at least a plurality of instructions; an instruction prefetch buffer for preparing and storing at least one or more instructions from the storage device in advance; an instruction address register for specifying an instruction address of the storage device in which instructions to be stored are stored; and an instruction address register for requesting the instruction address of the storage device when the instruction prefetch buffer is empty. a further instruction request generation circuit that generates a further instruction request signal and counts the number of instructions already stored in the instruction prefetch buffer according to the number of valid bits; an instruction register for receiving the instruction register; a decoding circuit for generating an operand data request signal requesting data from the storage device according to the contents of the instruction register; When the number of instructions accumulated in the instruction request generation circuit is smaller than a predetermined number when they occur at the same time, the instruction request signal is given priority, and when they are equal or a thick number, the instruction request signal is given priority. 1. A data processing device comprising: a request signal selection circuit for prioritizing data request signals.