JPS6028450B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked loop (PLL) frequency synthesizer type channel selection device, and particularly to a sensor for automatically controlling the local oscillation frequency and obtaining information necessary for broadcast channel search operations. The purpose is to simplify the

A block diagram of a subsidiary PLL frequency synthesizer type television channel selection device is shown in FIG.

To explain this, the outputs of the high frequency amplifier 1 and the voltage controlled local oscillator 2 are mixed in the mixer 3, and the resulting intermediate frequency signal passes through the intermediate frequency amplifier 4, is detected and amplified by the video amplifier 5, and is sent to the video tube 6. is supplied to From this video signal processing system, a video/audio carrier wave detector 7, a frequency discriminator 8,
A sensor consisting of a vertical synchronization signal detector 9 and a group of voltage comparators 10 provides information necessary for automatic local oscillation frequency control (AFC) and broadcast channel search operations.
The sensor output passes through a control logic circuit 11, an automatic/manual tuning logic circuit 12, and an up/down counter 13 to control a programmable counter 14 and sequentially increment or decrement the address of a code converter 16. however,
It is assumed that the latter address increase/decrease occurs when there is no incoming signal to the high frequency amplifier and the search prohibition switch is switched to the search mode. The PLL frequency synthesizer includes a voltage controlled local oscillator 2, a prescaler 17, a first
The output of the reference oscillator 21 is divided by the second programmable frequency divider 14, and the output of the reference oscillator 21 is divided by the second programmable frequency divider 14. The frequency division ratio of the first programmable frequency divider 18 is determined by the output of the code converter 16 controlled by the channel selector 22, and the output is applied to the other input terminal of the phase comparator 19. The configuration is such that it is used as input.

Figure 2 shows the first programmer full frequency divider 1 in the subordinate example.
8 and a second programmable frequency divider 14, respectively. A portion 23 surrounded by a dotted line is usually formed into one chip of an integrated circuit. Local oscillator 24, prescaler 25
, first programmable frequency divider 26, phase comparator 27,
The low-frequency moat generator 28, the reference oscillator 29, and the second programmable distributor 30 are designated by symbols 2, 17, and 17, respectively, in FIG.
18, 19, 20, 21 and 14. now,
When it is desired to receive a certain channel (country channel), a code is determined according to the code conversion table shown in Table 1, and this code is applied to the first programmer full frequency divider 26.

For example, if you want to receive channel 4, "000111"
0001'' is given. Therefore, the reciprocal of the division ratio is determined by the following formula: 0 x Yu + 0 x Yu + 0 x 2.
711 x Taju1 x Ko + 1 x Kiju0 x Shioju○ Equal to the integer part when displayed.

The same applies to other channels. The local oscillation frequency of channel 4 is 113MHZ, and prescaler 2
Considering that the frequency division ratio of 5 is 1/256 and the frequency divider ratios in the front and rear stages of the first programmable frequency divider 26 are 1/2, the input frequency to the phase comparator 27 is: IM
Hz/(256×2×2)=IMHz/1024=97
It becomes 6.5629MHz.

This value is the same for other channels. Then, when a signal having this frequency is applied to the other input terminal of the phase comparator 27, the PLL becomes locked. It is assumed that the second programmable frequency divider 301 provides a frequency division ratio of, for example, 1/3667.

At this time, the frequency divider 30
The reference oscillator 29 must be 3.5810
Must oscillate at 59MHZ. This frequency is controlled by a crystal oscillator 31. When the frequency division ratio of the frequency divider 30 is changed, the reference input frequency to the phase comparator 27 changes, so the oscillation frequency of the local oscillator 24 is finely adjusted. This fine adjustment is used for AFC operation, which will be described later. Load signal input section 32, latch selection decoder 3
3. The data input 34 to each latch should be controlled from the code converter 16 and up/down counter 14 shown in FIG.

Actually, along with these 16 and 14, the control logic circuit 1
1. Since the automatic/manual tuning logic circuit 12 and up/down counter 13 are composed of a 4-bit, 1-chip microcomputer, the integrated circuit 23 in FIG. 2 inputs data to each latch every 4 bits, When a load signal is sequentially applied to latches 0 to 4 selected by the latch selection decoder, the first
The code shown in the table is to be programmed.
FIG. 3 is a detailed diagram of the voltage comparator group 10 shown in FIG.
FIG. 4 is a diagram of its operation.

In those drawings, a vertical synchronization signal detector 35, a frequency discriminator 36, and a video/audio carrier detector 37 correspond to blocks designated by reference numerals 9, 8, and 71 in FIG. 1, respectively. The output voltage of the frequency discriminator 36 is compared with a reference voltage by a voltage comparator 40.

The reference voltage is the reference intermediate frequency fr (45.7
9MHZ) is set equal to the voltage Vr (see FIG. 4a). Therefore, information on whether the intermediate frequency is higher or lower than the reference value is transmitted to the H level and L level in Figure 4c.
It can be converted into a level and added to the input port 45 of the information processing device (microcomputer). In order to avoid narrowing of the AFC operation due to the intersection of the frequency discriminator characteristic with the reference voltage axis that occurs near the adjacent audio carrier fa, the output voltage of the vertical synchronization signal detector 35 changes when the vertical synchronization signal disappears. Taking advantage of this fact, the output shown in FIG. 4 d is obtained from the voltage comparator 38, which is input to the input port 45 for information processing, and the logical sum of A+B shown in FIG. 4 e is obtained, and the AFC The direction of tuning up or down is determined. In this manner, the frequency division ratio of the second programmable frequency divider 30 increases or decreases in accordance with the determined direction.

Unlike analog AFC, the intermediate frequency changes discretely, so when the frequency range that can be considered as correct reception is entered, the change in the division ratio of the second programmable frequency divider 30 must be stopped to prevent hunting. wake up Information for stopping is obtained by identifying whether the APC control voltage is within a certain defined voltage range Vq-Vp (see Figure 4a). The voltage comparators 41 and 42 are used for this purpose, and when the logical product of these outputs C4 and C5 is equal to (see FIG. 4b), the frequency division ratio stops changing. In addition to this logical product, voltage comparators 39, 43, and 44 are required to stop the change in the frequency division ratio, but these will be described in the following description of the station searching operation. The information necessary for station searching includes information such as whether the incoming signal is a television broadcast wave and whether the tuned carrier wave is a video carrier wave.

The reference voltage of the voltage comparator 39 is set by the vertical synchronizing signal,
When the received signal is a television signal, a pulse signal having the same period as the synchronizing signal from the voltage comparator 39 is obtained.

This signal identifies that the incoming signal is a television signal. If the control range of AFC is set to a wide band of 1.9 MHz or more, when the local oscillation frequency increases by 1.8 MHz, the lower adjacent channel audio carrier wave will be mistakenly identified as the video carrier wave of the desired channel selection.

To prevent this, if the voltage comparators 43 and 44 detect the video carrier at the same time, the received carrier is identified as the video carrier. In the United States, there is a mountain MHZ vacant frequency band between the regular channels 4 and 5 according to the channel plan, and it is permitted to insert new cable TV channels into this area.

In that case, the reception frequency must be shifted to lower channel 4 by 2 MHZ or channel 5 to higher channel 2 MHZ. Alternatively, to avoid adjacent channel interference, the carrier wave of channel 4 or channel 5 may be changed to about aMH2.
It is also possible to move to the above-mentioned blank frequency band. The complexity of the conventional sensors described thus far arises from such US cable television considerations.

The offset frequency of television broadcast waves is stipulated by law, and is negligibly small compared to the carrier frequency offset of the cable television signal, and the carrier frequency offset of the high frequency conversion output of a video tape recorder is several tens of thousands. Since it is below HZ, if measures are taken separately for channels 4 and 5 in the United States, the complexity of the sensor in the conventional example can be considerably simplified.

The present invention focuses on this point, and for channels 4 and 5, the codes given to the first programmable frequency divider are, in addition to the regular codes, a plurality of codes having new offsets. A block diagram of one embodiment is shown in Fig. 5, an explanatory diagram of the PLL integrated circuit is shown in Fig. 6, a code conversion table is shown in Table 2, and a sensor circuit is shown in Fig. 7.
The operating waveforms are shown in FIG. This example is the fifth
As shown in the figure, a code switch 47 is provided, but instead of this, a video/audio carrier wave detector 7 shown in FIGS. 1 and 3 is provided.
and 37, and 38 of the voltage comparator group in Figure 3.
, 43, and 44 are removed to simplify the sensor.

Further, the complicated AFF operation shown in FIG. 4 is simplified as shown in FIG. In FIG. 5, voltage comparator 1
0', control logic circuit 11', second programmable frequency divider 14', code converter 16', first programmable frequency divider 18' and code switcher 47, blocks designated by other symbols is the same as in FIG. 1 and operates in the same way.

The different points will be explained below using FIG. 6, FIG. 7, FIG. 8, and Table 2. In FIG. 6, a latch 5, indicated at 46, is added, so that the output terminal of the latch selection decoder 33' becomes 1.
Only the terminals have increased. First programmable frequency divider 26
The lowest part of ' is variable, and the data shown in latch 5 of the code conversion table in Table 2 is given here. On the other hand, the variation range of the frequency division ratio of the second programmable frequency divider 30' is set narrower than that of the second programmable frequency divider 30 of FIG.

Now, assume that the code given to the first programmable frequency divider 26' is based on the code conversion table shown in Table 2.

Table 2 shows codes corresponding to temporary channels displayed with channel numbers 4L, 4th, 5L, and 5th. For example, the code corresponding to channel number 4L'
Well, it is "000111000," but as explained in Table 1, the reciprocal of the division ratio can be found using this code using the following formula.
Therefore, in this embodiment, the local oscillation frequency is 112 MHZ, which is IMHZ lower than the regular local oscillation frequency of channel 4, 11 arc 4 Hz.

Similarly, for channel numbers 4, Hiro and Ta, IMHZ is higher but lower than the regular local oscillation frequency. These temporary channels are switched to the 4L, 4 or 4 day code for channel 4, and to 5L, 5 or 5 day code for channel 5, using the code switch 47 mentioned in FIG. On the other hand, the variation range of the frequency division ratio of the second programmable frequency divider 30' is selected to be a variation range of ±IMHZ with respect to the local oscillation frequency.

Then, the intermediate frequency changes only between the upper and lower frequency limits of the signature, fu and f, shown in FIG. 8, and does not exceed frequencies near the adjacent audio carrier frequency fa, as shown in FIG. From the above, the complicated sensor shown in FIG. 3 can be simplified as shown in FIG. 7.

That is, the video/audio carrier wave detector 37 shown in FIG.
Voltage comparators 38, 43 and 44 could be removed. The effects obtained by the present invention are as follows.

That is, for channels 4 and 5, the division ratio of the first programmable frequency divider is switched so that the local oscillation frequency becomes ±IMHZ, and the division ratio of the second programmable frequency divider is switched so that the local oscillation frequency becomes ±IMHZ. Since the local oscillator frequency tuning range is ±IMHz, the video/audio carrier detector can be eliminated even with an incoming signal offset frequency of ±2MHz, and the number of voltage comparators required is reduced. The sensor can be simplified. It should be noted that the frequency indicated as IMHZ above is merely an example, and it goes without saying that the design can be arbitrarily changed without changing the gist of the present invention. Table 1 (US Channel) Table 2 (US Channel)

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional PLL frequency synthesizer television channel selection device, FIG. 2 is a block diagram of a conventional PLL integrated circuit, and FIG. 3 is a circuit diagram of a conventional sensor.
4a, b, c, d, and e are waveform diagrams for explaining the operation of the conventional example, and FIG. 5 is a block diagram of an embodiment of the present invention.
6 is a block diagram of a PLL integrated circuit used in an embodiment of the present invention, FIG. 7 is a circuit diagram of a sensor used in an embodiment of the present invention, and FIGS. 8a, b, and c illustrate the operation of an embodiment of the present invention. It is a waveform diagram for explanation. 2... Voltage controlled local oscillator, 8... Frequency discrimination circuit, 9... Vertical synchronization signal detector, 10'
...Voltage comparator, 11'... Control logic circuit,
13...Up Downtown Evening, 14'...
Second programmable frequency divider, 16'... Code converter, 17... Prescaler, 18'... First
programmable frequency divider, 19... phase comparator, 21... reference oscillator, 26'... first programmable frequency divider, 30'...... 2 programmable frequency divider, 33'...latch selection decoder, 3
8, 39, 40, 41, 42, 43, 44...
Voltage comparator, 45... Input port of information processing device (microcomputer), 46... Latch 5 4
7... Code switch. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. A phase lock loop frequency synthesizer type tuning device, which includes a means for finely adjusting the local oscillation frequency by changing the reference input frequency to the phase comparator, and a programmable device for dividing the output of the local oscillator (voltage controlled oscillator). A means for selecting a reception channel by changing the frequency division ratio of the frequency divider is provided, and when receiving a channel adjacent to an empty frequency band, the frequency division ratio is shifted from the regular frequency division ratio corresponding to that channel. and means for applying a new frequency division ratio to the programmable frequency divider.