JPS6025851A - Speed checking device for automatic train stop - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a speed checking device for a variable frequency automatic train stopping device, and in particular, a receiving antenna for receiving information from an on-board device and a speed check device for an on-board device. The present invention relates to a speed checking device that includes a plurality of combinations with wayside elements that provide stop information, spaced apart in the running direction of a train.

PRIOR ART This type of speed checking device generally has the following structure, as shown in FIG.
Receiving antennas such as loop coils and resonant circuits (AI, A2
) and a ground element (CI, C2) such as a resonant circuit, a plurality of receiving control means provided spaced apart from each other in the direction of train movement, and selecting a predetermined frequency component in the input signal, A processing circuit (5) that amplifies, rectifies and smoothes the output, a timer (6) that is triggered by the output signal of this processing circuit (5), and a timer relay (6) that is operated by the output signal of this timer (6). TMR) and this timer relay (
A counter (1) that calculates the number of times the TMR) is operated, and a plurality of counter relays (CORO) that are operated according to the count value of this counter (7).

COR+, CPR2, COR3) and the processing circuit (
5) a switching circuit (8) for switching the receiving antenna (AI, A2) connected to the input side of the timer relay (TMR);
) (Hereinafter, relay contacts are indicated by the same symbols as the corresponding relays, operating contacts are indicated by V-shaped marks, and falling contacts are indicated by inverted V-shaped marks.) C1,C
2) multiple control relays (QRI,
QR2) and a set relay (STR) that sets and overrides the counter (7) according to external conditions.
, C2>, the beacon is disabled and stop information is not given to the on-board device only when the time required to reach C2> is longer than a predetermined time.

As shown in FIG. 8, the conventional device of this type is as follows.
The switching circuit (8) is configured by a hybrid transformer (Proceedings of the 19th Domestic Symposium on the Use of Cybernedics in Railways, pp. 336-340, 1982)
. However, in this device, since the secondary coil of the hybrid transformer is connected in parallel to the processing circuit, noise from the train, for example, noise may be mixed in due to the receiving antenna facing the train's motor or chopper.

Malfunction may occur.

OBJECTS OF THE INVENTION An object of the present invention is to provide a speed checking device for an automatic train stopping device that is simple in construction, unaffected by noise, and highly reliable.

Structure of the Invention According to the above object, a plurality of combinations of receiving antennas for receiving information from an on-board device and ground switches for providing stop information to the on-board device are provided spaced apart from each other in the direction of train movement, In a speed checking device for an automatic train stop device, the receiving antenna is connected via a switching circuit to the input side of a processing circuit that selects and amplifies a predetermined frequency component in a signal received by the antenna, in which a semiconductor switching element is used. This is achieved by configuring the switching circuit using .

Example The present invention will be described below based on embodiments shown in the drawings.

In FIG. 1, (1) is a train equipped with an on-board device (2), which travels along a running path (3) from C left to right in FIG.

As shown in FIG. 2, the on-board device (2) has a frequency f O
An oscillator (10) that oscillates at It has a smoothing processing circuit (12) and a main relay (MR) operated by its output signal, and the operating contact of the main relay (MR) is inserted into the brake command circuit (13).

The processing circuit (12) includes a bandpass filter (14) that passes the frequency [0 that is the output of the oscillator (10), an amplifier (15) that amplifies the output, and a rectification and smoothing circuit that rectifies and smoothes the output. 16), and the frequency f
If the O signal is not input, there will be no output, which causes the main relay (MR> to drop).

The brake command circuit (13) is connected to the main relay (
MR) has fallen, and a brake command is output to the effect that the brakes should be applied.

On the running path (3), there is a receiving antenna (A1) and a ground coil (C
A total of two sets are provided: a combination with 1) and a combination with the reception ffl antenna (A2) and ground element (C2). The receiving antenna (A1) and control antenna (C1) are connected to the train (1)
are installed at intervals of (Ll) in the direction of travel,
The receiving antenna (A2) and the beacon (C2) are installed at an interval of (L 2 ) in the running direction of the train.

Each receiving antenna (A1, A2) is a known circuit in which a capacitor and a load resistor are connected in parallel to a coil, as shown in FIG.
It is connected to the.

Each ground element (C1, C2) is a known circuit, as shown in Fig. 3, in which operating contacts of control relays (QR+, QR2), which will be described later, are provided in a resonant circuit in which a coil and a capacitor are connected in parallel. be.

The verification circuit (4) determines the time it takes for the onboard element (11) of the train (1) to reach the control element (C1) from the receiving antenna (A1) and the time it takes for the onboard element (11) of the train (1) to reach the ground element (C2) from the receiving antenna (A2). It is determined whether or not the time until each time is longer than a predetermined time, and when it is shorter than the predetermined time, the controllers (CI, C2) are enabled and stop information is given to the on-board device.

As shown in FIG. 3, this checking circuit (4) detects the frequency f O
A processing circuit (20) which selects the component of, amplifies it, and obtains an output by rectification and smoothing (); Timer (
21), a timer relay (TMR) operated by the output signal of this timer, and a timer relay (-r MR).
A counter (22) that counts the number of operations, and a counter (22) that counts the number of operations.
A plurality of (three in the illustrated example) counter relays (CORO, CORI, C
0fl2) and the receiving antenna connected to the input side of the processing circuit (20) is connected to the counter relay (COR[1, CO
A switching circuit (23) that switches depending on the contact condition of the counter relay (COR+, C01-2) and a control relay (1. ) and a relay (STR) for overloading the counter (22).

The processing circuit (20) includes a bandpass filter (24) having a pass characteristic of a frequency fO, an amplifier (25) that amplifies its output signal, and a rectification and smoothing circuit (26) that rectifies and smoothes the output signal. This is a known circuit with

The timer (21) is triggered by the output signal of the processing circuit (20) and outputs a predetermined time signal after a predetermined time.

The counter (22) is a known circuit made of a semiconductor, such as a diode or a transistor, and the count signal is sent to the signal input terminal via the operating contact of a timer relay (TMR). The signal is set relay (
STR) is input to the terminal via the operating contact. This counter (22) is a set relay (STR)
When the timer relay <i-MR> operates in this state, the open value becomes '1''.
Why does the first output terminal (OUTI) have an output?
Next, when the timer relay (TMR-) operates again, the agent value becomes "2" and the second output terminal (OU2) becomes output.

The counter relay (CORD> is operated by the signal of the first output terminal of the counter (22), and the counter relay (CORD>
OR2) is operated by the signal at the second output terminal of the counter (22). In the illustrated example, the counter relay (CORo) is configured to be energized via the operating contact of the set relay (8fl) and the drop contact of each counter relay (COR1, COR2), but the counter relay (CORo) n of
1 Counter when the numerical value is other than “1” and “2” (2
2) The output signal allows operation.

The switching circuit (23) includes two pairs of transformers (30+, 31+), (
302, 312) and two pairs of diodes (32+.

331 , 322 , 332 ) and counter relay (
CORO, CORI> operating contacts.

The primary coils of transformers 1 to 3 (lI, 302) are connected to the corresponding receiving antennas (AI, A2), the secondary coils are connected to the primary coils of transformers (311, 312), The secondary coil of 312> is connected to the bandpass filter (24) of the processing circuit (20). Each diode (3:N, 331, 322, 332) is connected to the secondary coil of the corresponding transformer (301, 302). They are each inserted between the coil and the primary coil of the transformer (311, 312).The middle points of the secondary coil of the transformer (30+) and the primary coil of the transformer (31+) are connected to the counter relay (C
The counter relay (
COR+) is connected to a DC power supply (34) via an operating contact.

The current value of the DC power supply (34) is the same as that of the diode (321°3
3 + , 322 , 332 ), but the transformer ( 30 + , 311 , 302 , 312 )
does not saturate because the DC currents flow in opposite directions.

The control relay (QRI> is energized via the operating contact of the counter relay (COR1), and the control relay (OR2>) is energized via the operating contact of the counter relay (COR2).

The set relay (STR) is energized and operates under conditions such as when the train (1) enters a blocked section where the speed check device is installed or an area where the speed check device is installed. If the vehicle enters a closed section where the speed check device is installed or moves out of the area where the speed check device is installed, it will be cut off and fall.

Next, the operation of the above device will be explained with reference to FIG.

The oscillator (10) of the on-board device always oscillates at the frequency fO, so the main relay (MR) operates,
Brake command is not output. Also, the speed check device on the ground is set! - Since the relay (STR) has fallen and there is "C", each counter relay (C, ORO, CORI, C
OR2) and each control relay (QRl, OR2) Gt have fallen. Therefore, since no forward bias is applied to the diodes (321, 331, 322, 332) of the switching circuit (23), each diode maintains an off state. Therefore, the receiving antenna (AI, A2) is connected to the processing circuit (
20), and even if the receiving antenna (A1) or <A2) receives noise, it will not be input to the processing circuit (20).

When the set relay (STR) operates at time C1 (t1) as the train (1) runs, the counter relay (CORθ) is set. , COR2). As a result, the switching circuit (23>) connects the diodes (32+, 34N
) is forward biased to connect the receiving antenna (AI>) to the processing circuit (20). However, the switching circuit (23)
Since the diodes (322, 332> are not forward biased, the receiving antenna (A2) is connected to the processing circuit (
20).

As the train (1) is running, when the onboard element (11) reaches the receiving antenna (A1) at time (t2), the diodes (32+, 33+) are both on, so the frequency [0] A signal is received by the receiving antenna (AI), the signal with frequency fO is input to the processing circuit (21), the timer (20) is triggered from 1 to output the signal for a certain period of time after a certain period of time, and as a result, the timer The relay (TMR) operates for a certain period of time.

When the timer relay (TMR> operates, the counter (
22) becomes 1″, the counter relay (CO
RI) operates, the counter relay (CORO)
falls down.

When the counter relay (CORO) operates and the counter relay (CORO) falls, the switching circuit (23) applies a forward bias to the diode (322, 332>) and switches the receiving antenna (A2) to the processing circuit 20. ) and
And the diodes (32+, 33+) become non-biased and disconnect the receiving antenna (A1) from the processing circuit (20).

Also, when the counter relay (CORl> operates), the control relay (QRM) operates, which causes the ground element (C1) to
is shorted and becomes invalid. Therefore, the time (running time of the Zunawara train) from the time when the onboard child (11) reaches the receiving antenna (A1) until the time when the onboard child (11) reaches the receiving antenna (C1) is the same as when the onboard child (11) reaches the receiving antenna (C1). Within the time (T2) from when A1) is reached until the control relay (QRl) operates, the onboard device (2) changes the oscillation frequency of the oscillator (10) to the resonant frequency of the ground element. , main relay (MR
) falls and outputs a brake command. However, when the onboard device (11) reaches the beacon (C1) after the above-mentioned time (TI), the onboard device (2) is disabled due to the short circuit of the beacon (CI), so the oscillator (10 ) continues to oscillate at the frequency fO, and the main relay (MR) continues to operate.

As the train (1) progresses, when the onboard child (11) reaches the receiving antenna (A2) at time ([3), the frequency t
Since the signal of o is received by the receiving antenna (A2) and input to the processing circuit (20), the timer <21) is triggered again and outputs the signal for a certain period of time after a certain period of time (T1),
As a result, the timer relay (TMR> operates again for a certain period of time).

When the timer relay (TMR) operates, the counter (22
) becomes "2", which activates the counter relay (COR2), and the counter relay (CORI) turns off 1FL, fi1F1 (23), hataiode (322).
, 332> becomes unbiased and the receiving antenna (A2)
is separated from the processing circuit (20).

In addition, the control relay (QRI) is a counter relay (COR).
+) has fallen and the ground element (C1) is activated, and the control relay (OR2) is activated by the counter relay (C
When OR2) was activated, the ground element (C2)
Disable. Therefore, the time from the time when the onboard child (11) reaches the receiving antenna (A2) to the time when it reaches the wayside child (C2) (i.e., the running time of the train) is
The control relay (
Within the time (-r2) until OR2) operates, the onboard device (2) activates the main relay (M R
) falls and outputs a brake command, and the main relay (MR) continues to operate even after time (T2).

When the kick relay (STR) falls at time (t4), the counter (23) stops and the counter relay (COR2) stops.
) falls, which causes the control relay (QR2) to fall and activate the ground element (C2).

In the above device, unless the diode (32+, 331, 322°332) is forward biased, the received signal of the receiving antenna <AI, A'2) will not enter the processing circuit;
In a state where one receiving antenna, for example (A2), is connected to the processing circuit (20), the processing circuit (20)
Even if the other receiving antenna (A1) that is not connected to receives noise, it will not be affected by this noise. In addition, when the diodes (32+, 331, 322, 332) have an open circuit failure, the signal of frequency fO is transmitted to the processing circuit (20).
Since there is no human input, the timer relay and even the control relay (QRI, OR2) do not operate, and when the onboard device (11) reaches the corresponding ground device (CI, C2), the onboard device (2)
) to give stop information. Furthermore, a diode (32+.

331, 322, 332> is short-circuited, each receiving antenna (A1, A2) is connected together to the processing circuit 20), thus the input level to the processing circuit (20) is reduced, and the timer (21) is connected to the processing circuit 20). ) is not triggered and the timer relay (TM
R) and therefore the control relay (G) RI.

OR2) does not work.

FIG. 5 shows an embodiment of a switching circuit (39) using transistors instead of diodes, and each transistor (35
+', 361, 352, 362) is the resistance (37+, 3
81, 372, 382> are individually self-biased. This switching circuit is also a counter relay (CORo)
When -C is activated, the transistors (35+, 3G+) are turned on and the receiving antenna (A1) is processed by the processing circuit (20).
When the counter relay (COR1) is operated, the transistor (352°362) is turned on and connects the receiving antenna (A2) to the processing circuit (20). When the transistor has an open circuit failure, the signal of frequency f O is not input to the processing circuit (20), and the number of short circuits FI! Then, the receiving antennas (A1, A2) are both connected to the processing circuit (20
), the level of human power to the processing circuit (20) is reduced, and the timer relay (TMR) does not operate.

FIG. 6 shows yet another embodiment of the switching circuit.

This switching circuit (40) includes a transformer (3(N, 302
) and an amplifier circuit using transistors (41+, 412). Transistor (411,412
), the base is connected to one end of the secondary coil of the transformer (3(N, 302)) via the capacitor (421, 422), and the emitter is connected to one end of the secondary coil of the transformer (301, 302) via the resistor (46+, 462). It is connected to the other end of the secondary coil, and the base and collector are resistors (44+, 442).

451. 452) and Karatan Relay (CORO, CO
R1) is connected to the positive terminal of a DC power supply (not shown) through the operating contact of the capacitor +1 (43+, 432
) is connected to the processing circuit (26>).

In this switching circuit (40), when the counter relay (COR port) is operating, the transistor (41+) is turned on, connecting the receiving antenna (A1) to the processing circuit (26), and the counter relay (CORI) is operating. When this happens, the transistor (412) turns on and connects the receiving antenna (A2) to the processing circuit (2G).

Then, if the transistor 1~ has an open circuit failure, the frequency fO
If the signal is not input to the processing circuit (20) and a short circuit occurs, both the receiving antennas (A1 and A2) will be input to the processing circuit (26).
), the input level to the processing circuit (26) decreases, and the timer relay (TMR) does not operate.

The present invention is applicable not only to a device using a resonant circuit consisting of a coil and a capacitor as a receiving antenna (A1, A2), but also to a device using a loop coil as a receiving antenna (A+", A2') as shown in FIG. In addition, it can be applied not only to devices that check the speed at two points, but also to devices that check the speed at three or more points by increasing the number of stages of the counter (23). Furthermore, other semiconductor switching elements such as Zyristors may be used instead of diodes and transistors.

The C counter may be a known semiconductor circuit, however, it may be configured such that no output occurs in the event of a failure, or it may be a contact point of a relay.

Effects of the Invention As described above, in the present invention, the switching circuit is configured with a semiconductor switching element to switch the receiving antenna connected to the processing circuit, so compared to the conventional device using relay contacts or a hybrid transformer. The configuration is extremely simple. Further, as long as the switching element is not turned on, even if noise is input to the corresponding receiving antenna, the noise will not be input to the processing circuit, so it will not be affected by the noise. Roughly speaking, even if a switching element fails, the output is interrupted and the train is controlled to stop, so it is always on the safe side, and therefore reliability is extremely high.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of an automatic train stopping device, FIG. 2 is an electric circuit diagram showing an example of an on-board device, and FIG. 3 is an electric circuit diagram showing an example of a speed checking device according to the present invention. The circuit diagram, Figure 4 is an explanatory diagram of the operation of the same speed checking device, and Figure 5 shows another embodiment of the switching circuit. r Electrical circuit diagram, Fig. 6 is an electrical circuit diagram showing yet another embodiment of the switching circuit, Fig. 7 is a diagram showing another embodiment of the automatic train stop device, and Fig. 8 is a diagram of a conventional speed checking device. FIG. 2 is an electrical circuit diagram showing an example. (20): Processing circuit, (22): Counter, < 2
3.39.40) : Switching circuit, (A I , A 1'
, A2, A21: Receiving antenna, (CI, C2): Ground element, (QR+, QR2): Control relay. Patent applicant: Nippon Signal Co., Ltd. - tlE'? Date: 1982; -O-Mon. 28-,) Director of the Japan Patent Office 1, Matter f'] Indication Patent 1t158-133682 2, Title of invention Speed checking device 36 for automatic train stopping device
Name of the patent applicant (465) Nippon Signal Co., Ltd. 6, Number of inventions increased by the amendment No change 7, ?ni
Positive object in the specification (detailed description of the invention, drawings) 8,? d
i Correct contents As shown in the attached sheet fzo;・ 1゛-)・“” 5 8, Contents of amendment 1) Details rcPR2J on page 2, line 16 in 1
R2J and correction. 2) In the same page, page 8, lines 16 to 17, I ``1'' is corrected to ``r''``1''. 3) Same, page 11, line 8, (car) 2 device, oscillator (10)
`` is corrected to ``is the oscillator (10) of the on-board device.'' 4) Same, page 12, line 18, [Processing circuit (21) J]
Processing circuit (20) Correct as J. 5) Same, page 12, line 19 [Timer (20) J is corrected to "Timer < 21) J." 6) Same, page 14, line 4 [The said time (T-1) J is corrected to "The said time (T2) Add J. 7) Same, page 18, line 11 to page 19, line 2, 1. This switching circuit (
40) also...does not work. ' shall be corrected as follows. In this switching circuit (40), when the counter relay (COR) is operating, the transistor (111,) is operated to connect the receiving antenna (△1) to the processing circuit (26), and the counter relay (CORI) is activated. When is operating, transistors 1 to (412) are operating and connect the receiving antenna (Δ2) to the processing circuit (2G), and the signal of frequency fo is amplified and input to the processing circuit (26). 1-If the transistor (4L, 412) has either an open-circuit failure or a short-circuit failure, it will lose its amplification compensation, and the receiving antenna (
The input level of the signal of frequency fO from ΔI, A2) to the processing circuit (26) decreases, and the timer relay (TMR)
doesn't work. 8) Same, p. 19, lines 13 to 14, replace ``a known semiconductor circuit (however, even if it has a configuration in which no output occurs in the event of a failure)'' be may be 4 (configuration), but it can be corrected. 9) j not shown in the attached drawing; sea urchin, code [3
32'' is corrected to r322J, and the code 1-3[3J in FIG. 5 is corrected to 1-36+J.

Claims (1)

[Claims] 1)! A plurality of combinations of receiving antennas that receive information from the on-board device and ground switches that provide stop information to the on-board device are provided spaced apart from each other in the direction of train movement, and In a speed checking device for an automatic train stop device, the receiving antenna is connected to the input side of a processing circuit that selects and amplifies a frequency component via a switching circuit, and the switching circuit is configured using a semiconductor switching element. A speed check device for an automatic train control device, characterized in that it comprises: