JPS60254318A - Magnetic disc control device - Google Patents

Abstract

PURPOSE:To execute data transfer efficiently and rapidly by exciting a microprocessor on the basis of a buffer full status signal and executing head advancing processing prior to the transfer of the data block of the final sector in a data buffer in a magnetic disc control device having a structure using a bus in common for a microprocessor and a data buffer. CONSTITUTION:If the microprocessor sets up a head advancing flip-flop (FF)101 to start data transfer when five sectors are to be read out from a sector 14 of a certain cylinder head 0, an FF118 is set up and data transfer is started. When data in a sector 15 are read out from a disc, a detecting signal 104 is outputted from a block end detecting circuit 102 and synchronized with a buffer full status display signal 107 (DRLFUL) by an FF108 and a signal 109 is outputted. Then, a signal (FULL) indicating the buffer full status is outputted from an OR gate 111 on the basis of the output signal 109. Consequently, the output 115 of a control circuit 114 is reset and data transfer of the host side is interrupted.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a controller for a magnetic disk device used for external storage of an information processing device, and in particular to a magnetic disk control structure in which a microprocessor and a data buffer share a path. Regarding equipment.

[Technical background of the invention and its problems]

A hard disk controller having a configuration as shown in FIG. 1 is widely used in node disk drives that provide external storage for information processing devices. In FIG. 1, 1 is a hard disk controller, 11 is a host system (H-CPU), and 12 is a hard disk device (DI
SK). Reference numerals 2 to 10 each form a component of the hard disk controller 1, and 2 is a microprocessor that controls the entire controller 1, and 3 is a program storage ROM. 4 is a RAM, consisting of a work area for the microprocessor 2 and a /47 hard memory for temporarily storing data read and written from the disk. 5 is a host interface control circuit (HO8T-IF-
CNT), 6 is a control circuit (6) consisting of a format timing control section and a notnotsufa memory control section.
FTC/BMC), 7 is a disk interface control circuit (DD-IF-CNT), 8 is a data bus,
9 is a host interface, and 10 is a disk interface.

Here, the buffer memory in the RAM J provided in the controller 1 is constituted by a FIFO buffer in units of sectors, and the buffer size is assumed to be 4 sectors. Also,
In order to share the data bus 8, it is assumed that the microprocessor 2 is in a halted state (hold state) during data transfer, and that head switching and seek operations are performed by the microprocessor 2.

Conventionally, with a controller configured like this, there is a wait for the disk to rotate when the head is switched, and a high-speed processor must be used to switch the head without waiting for this rotation. , rising costs;
This has led to the inconvenience of a very disadvantageous configuration, which leads to the complexity of the software.

A specific example of this will be explained with reference to FIGS. 1 and 2. Here, the head of the cylinder consisting of "0".

The operation when reading five sectors from sector "14" will be described as an example. Assuming that the final sector number is A16, the order of access is sectors 14, 15, and 15 of head 0.
16, and sectors 0 and 1 of head 1. Figure 2 (a
) is disk myo) et al.'s index no J? Luz (IND
EX), and the same figure (b) shows the position of the sector on the magnetic surface and its nanno (A). The same figure (C) shows the hold request signal (HOLD REQ). The microprocessor 2 starts the data transfer (B and F in the diagram).
), the microprocessor 2 becomes active and starts data transfer, and the microprocessor 2 enters a hold state (C in the figure).

G). In addition, in the figure, states A and E indicate microprocessor 2.
is operating (busy).

Also, Figure 2(d) shows the data from the disk.
→BF), and (-) in the figure represents the data transfer state from the buffer to the host system 11. In addition, Fig. 2(f) shows the full buffer (FUL).
L) A flag indicating the status. When this flag is active, it indicates that transfer on the host side is not possible.

First, when the microprocessor 2 is activated at point B shown in FIG. 2(C), a hold request signal (HO
LD REQ) is output and the microprocessor enters the hold state, thereby opening path 8 and starting data transfer. 3 sectors from the disk (sector 14.1
5.16), the buffer is full (FU
LL) state, the hold request signal (HOL
D REQ) falls (point D in Figure 2 (C)), the microprocessor 2 starts operating again, and changes the head to head 0.
to head 1 (E in FIG. 2(C)). When this head switching is completed, the remaining two sectors (SEFF, ″,
In order to read data (0, 1), data transfer is activated again (point F in FIG. 2(C)). At this time, since sector O has already passed when restarting after switching the head (point F in Figure 2 (, )), if you have to wait for -rotation,
Data in sector O cannot be read. That is, in order to read sector 0 without causing a rotational wait, it is necessary to start up by point H in FIG. 2, which requires an expensive system configuration capable of high-speed processing.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances.In a magnetic disk control device having a configuration in which a microprocessor and a data buffer share a data bus, a low-speed and inexpensive microprocessor is used to wait for rotation after a head advances. An object of the present invention is to provide a magnetic disk control device that can avoid this problem and efficiently perform data transfer at high speed.

[Summary of the invention]

In the present invention, a magnetic disk control device in which a microgross data pad 7a shares a data bus,
When moving from the last sector of a track to the next head, a pseudo-full (FULL) occurs after accessing the last sector.
By creating the state, it is possible to provide a magnetic disk control device that can efficiently perform r-to-back transfer after head switching using a low-speed and inexpensive microprocessor without waiting for rotation.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing the hardware configuration of essential parts in an embodiment of the present invention. In the figure, reference numeral 101 is a head-addressed flop, and can be set/reset by a microprocessor. A block end detection circuit (BLOCK END DETECT) 102 counts the number of blocks read/written to the disk. The initial setting of this block end detection circuit 102 is performed by a microprocessor.
FHDADV). 104 is the output signal (DBLKE-1 signal) of the block end detection circuit 102, which is the block one block before the final block (final block-1).
Outputs a detection signal. 105 is an AND dart p which inputs the output 103 of the head advance flip-flop 101 and the output 10.4 of the block end detection circuit 102, and 1oe is the output signal of the AND gate 105 (DSB
LKE). 107 is a block transfer end signal (
DRLFUL). 10g is and dirt 105
A flip-flop is used to synchronize the output 106 of the block transfer end signal 107.

109 is the output of the flip flora f108.

Reference numeral 110 is a buffer full state display signal (DFULL) indicating the full state of the data buffer, and when this signal 109 is 111#, it indicates that transfer on the host side is not possible. Reference numeral 111 is an OR dart which receives the output 109 of the flip 70 f108 and the buffer full state display signal 110, and 112 is the output of the OR gate 11. Reference numeral 113 is the output of the block end detection circuit 12, and is a final block access display signal (DDSKED) representing the final program access on the disk side.

114 is a data request signal (DR) to the host system.
115 is the data request signal (DRQ). Reference numeral 116 is a Nordart which inputs the output 112 of the OR gate 111 and the final professional access display signal 113, and 117 is the output of the Nordart 116. 11g is a hold request 7 flip-flop to the microprocessor, and when data transfer is activated by the microprocessor, this flip-flop is also set. 1 to 9 are hold request signals (HOI, DREQ). When the signal becomes '1', the microprocessor releases the data bus, address bus, control signals, etc., and becomes ready for data transfer.

FIGS. 4(a) to 4(0) are time charts showing the signal timings of each part in FIG. 3 for explaining the operation of one embodiment.

Here, the operation of one embodiment will be described with reference to FIGS. 3 and 4. Here, the cylinder head consists of 0. sector 1
The operation when reading sectors 4 to 5 will be explained.

First, the microprocessor sets the head advance flip-flop head 101 at the five points shown in Fig. 4 ←) and sets the output cuff o s (FHDADV) to
After that, when data transfer is activated at point B shown in FIG.
The output 119 (HOLD REQ) becomes 0.1'' and data transfer begins (period C shown in FIG. 4C).

When the data of sector 15 is read from the disk, the block end detection circuit 102 outputs a detection signal 104 (DBLKE.; last sector 1) as shown in FIG. 1
08, synchronized with the buffer full state display signal 1 o y (DRLFUL) shown in FIG. 4(h),
The signal 109 (FBLK 21) shown in FIG.
21) According to k, the OR gate 111 outputs a signal (FULL) indicating the buffer full state as shown in FIG. 4(j). As a result, the output 11 of the control circuit 114 is first
5 (DRQ) is reset and data transfer on the host side is interrupted. Then, at the end of accessing the final book kick (sector 16), Pro.

As shown in FIG. 4(o), the last block access indication signal 113 (DDSKED)
) is output, and as a result, the NOR gate 116 outputs the signal 117 (R8THLD) shown in FIG. (Point D in Figure 4(c)).

The above halt request signal 119 (HOLD RE
When Q) is reset, the microprocessor starts operating again and executes the head switching process (within period E in FIG. 4(c)). For the next access, do not perform a head admission, reset the head admission Frizzoff 101 at the point shown in Figure 4 (←). Then, data transfer is activated again at point F shown in FIG. 3(c), the flip-flop 118 is set, and the data transfer state (within period G in FIG. 4(c)) is entered. At this time, since point D (the point at which the microprocessor starts operating again) shown in FIG.
It becomes possible to restart (point F in FIG. 2(c)) before starting. Therefore, after the head advances, data in sector O can be accessed without waiting for rotation.

As mentioned above, the head advance flag (F)tDAD
By setting V), a pseudo full (FULL) state (FBLK'21) is created, which resets the hold request signal 779 (HOLD REQ) at the end of the final sector access. Therefore, the point at which the microprocessor starts working again is earlier. That is, what was conventionally the point D in FIG. 2 becomes the point D in FIG. 4 according to the embodiment of the present invention. Therefore, compared to the conventional case, the point in time for restarting the device after head advance operation, preparation for the next access, etc. is made earlier (see point F in FIGS. 2 and 4). According to the embodiment of the present invention, data can be transferred after a head advance without waiting for rotation, whereas in the past, the head advances had to wait for rotation.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a magnetic disk control device that shares data nozzles/cutters with a microprocessor, when moving from the last sector of a track to the next head, after accessing the last sector, By creating a pseudo-FULL state, it is possible to provide a magnetic disk control device that can efficiently perform data transfer after head switching without waiting for rotation using a low-speed and inexpensive microprocessor. .

[Brief explanation of the drawing]

Fig. 1 is a professional diagram showing the configuration of a magnetic disk control device targeted by the present invention, Fig. 2 is a time chart for explaining the conventional operation, and Fig. 3 is a diagram showing one embodiment of the present invention. FIG. 4 is a circuit block diagram showing the configuration of the main parts of the embodiment, and FIG. 4 is a time chart for explaining the operation of the above embodiment. 101.108.1111...Flip-flop, 1
02...Pro, end detection circuit, 105...and dart, 111...OR gate, 116...nor dart, 114...control circuit.

Claims (1)

[Claims] In a magnetic disk control device in which a data bus is shared by a multi-block FIFO data buffer that inputs and outputs data in block units and a microprocessor that controls processing within the device, the data buffer is operated under the control of the microprocessor. A circuit that generates a head advance flag that indicates whether or not a head advance is being executed, and a pseudo signal that indicates a puffed state at a predetermined timing before the end of the final sector access when this head advance flag indicates that a head advance is being executed. ° and means for notifying the microprocessor of a buffer full state according to a pseudo signal generated by this circuit at the end of the final sector access, and activating the microprocessor in response to the buffer full state signal. . A magnetic disk control device characterized in that head advance processing is performed prior to data block transfer of the final sector in the data buffer.