JPS60252925A - Constant current circuit - Google Patents

Abstract

PURPOSE:To obtain a constant current circuit having high accuracy by using a reference voltage generating circuit of an FET based on the Fermi level difference of a gate electrode to produce a constant current. CONSTITUTION:A reference voltage generating circuit is provided with an FET which has the threshold voltage difference (Vth1-Vth2) based on the Fermi level difference of a gate electrode and the same mutual conductance beta. When a resistance 20 has a level sufficiently higher than the impedance of an FETT1, the drain voltage (gate voltage) of the FETT1 is approximately equal to the threshold voltage Vth1. When an FETT2 is set in a saturated area, the current I2 flowing to the FETT2 is equal to I=(Vth1-Vth2)<2>.beta/2. In such a way, a constant current circuit of high accuracy is obtained with use of a reference voltage generating circuit of high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic devices, particularly to a reference voltage generator and its applications, as well as an insulated gate field effect transistor and a manufacturing method thereof.

In various semiconductor electronic circuits, it is essential to use a physical quantity having the dimension of voltage in order to generate a voltage that is a differential rate. Until now, the physical quantities have mainly been the forward voltage drop vF of a PN junction diode, the reverse breakdown voltage (Zener voltage) Vz, and the threshold of an insulated gate field effect transistor (often represented by IGFET or MOSFET). Value voltage Vth etc. are used.

These physical quantities do not indicate absolute voltage values (the voltage values are subject to fluctuations due to various factors. Therefore, in order to use these physical quantities as reference voltage generators for various electronic circuits, it is necessary to Attention must be paid to the fluctuation factors of the voltage value and the permissible fluctuation range.

First, regarding the temperature characteristics of these physical quantities, the above V
F and Vth usually have a temperature dependence of about 2 to 3 nV/C, and the temperature change in the reference voltage that accompanies this temperature change is so large that it may be necessary to give up on practical use depending on the application. .

For example, if you want to create a battery checker for an electronic watch that uses a nominal 1.5V silver oxide battery to warn that the battery voltage has dropped,
It is necessary to judge whether the battery voltage is high or low using 1.4 Vi degrees as the boundary (detection level).

This is the MOSFET threshold voltage Vt of approximately 0.6V.
Or, if you try to configure it using the diode's forward drop voltage ■F, the detection level with a target of 1.4V will have a temperature dependence, and the practical operating temperature range will be OC~50C.
Even if we make a narrow estimate, if the voltage fluctuates significantly from 1.23V to 1.57V, it will be K, and it cannot be used as a practical battery checker.

Next, regarding manufacturing variations in these physical quantities, MOS
The FET (7) threshold voltage ■th has a variation of about ±0.2V, and this variation is larger than the temperature change. Therefore, when the above-mentioned battery checker is made into an IC (integrated circuit) using Vth, not only external parts and connection pins (terminals) for correcting the reference voltage but also adjustment after the IC is manufactured are required. .

In addition, the Zener voltage vz has a low voltage limit of about 3V, which is inappropriate as a reference voltage used in the low voltage range of about 1 to 3V. The k used as
It is necessary to flow a current of approximately A to several tens of mA, which is inappropriate in terms of reducing power consumption.

As is clear from the above explanation, conventional reference voltage generators using Vtb, v, and z are not necessarily suitable for all uses, considering temperature characteristics, manufacturing variations, power consumption, voltage levels, etc. It's not something (,
For applications that require extremely strict characteristics, it has often been necessary to abandon practical application or mass production.

From the above studies, the present inventors learned that there are physical limits to the improvement of conventional reference voltage generators, and decided to research and develop a reference voltage generator with new ideas and ideas.

Incidentally, as a constant current circuit, one shown in Japanese Patent Application Laid-Open No. 51-28645 is publicly known.

An object of the present invention is to provide a reference voltage generation circuit based on a completely new concept not seen in the past, and to facilitate the design and mass production of electronic circuits.

Another object of the present invention is to provide a reference voltage generator with small temperature changes.

Another object of the present invention is to keep fluctuations in the obtained voltage values small with respect to fluctuations in manufacturing conditions, such as manufacturing variations between lots (
It is an object of the present invention to provide a reference voltage generating device with a small deviation).

Another object of the present invention is to provide an integrated circuit reference generator that can reduce manufacturing variations to the extent that post-manufacturing adjustments are not required.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generating device that can be manufactured with a large margin of tolerance to target specifications.

Another object of the present invention is to provide an integrated circuit electronic circuit device including a reference voltage generator with a high manufacturing yield.Another object of the present invention is to provide a reference voltage generator suitable for an IGFET integrated circuit. It is to provide.

Still another object of the present invention is to provide a reference voltage generator and a voltage comparator that consume less power.

Another object of the present invention is to provide a reference voltage generator capable of obtaining a highly accurate low voltage (1.1 square meters or less).

Another object of the present invention is to provide a standard Mi5 pressure generator that is compatible with relatively low voltage (approximately 1 to 3 cm) power sources, such as 1.5 V silver oxide batteries and 1.3 V mercury batteries. be.

Another object of the present invention is to provide a reference voltage generator suitable for semiconductor integrated circuits.

Another object of the present invention is to provide a highly accurate voltage comparator, regulated power supply, constant current circuit, and battery checker.

Another object of the present invention is to provide a semiconductor integrated circuit device for an electronic watch that has a built-in highly accurate battery checker and has a small number of external terminals.

Another object of the present invention is to provide a reference voltage generator compatible with a complementary insulated gate field effect transistor integrated circuit (0MO8IC) and a method of manufacturing the same.

The present invention has been made by returning to the origins of semiconductor physical properties and focusing on the 4IK energy gap Eg, Fermi level Ef, etc.

That is, it is well known that semiconductors have various levels such as energy gap Eg, donor, acceptor, and Fermi level, but the physical properties of these semiconductors, energy and
A reference voltage generator that focuses on the gap Eg or the Fermi level Ef has made remarkable progress in a wide range of fields since the discovery of semiconductors, and has never been seen before.

In terms of results, the present inventors considered using this energy gap Eg, 7 Hermi level Ef, etc. as a reference voltage source, and succeeded in realizing it. Using energy gap Eg, Fermi level Bf, etc. as a reference voltage source is not a difficult theory in itself, and the results are easy to understand and accept. However, in the field of the semiconductor industry, which no longer has a short history, this success story brought about by the present inventors, which is believed to be unprecedented, is original and groundbreaking, returning to the origins of semiconductor physical properties. It is expected that this technology will greatly contribute to the further development of the electronic circuit and semiconductor industries in the future.

According to one embodiment of the invention, two IGFETs with different conductivity types of silicon gate electrodes are fabricated within a silicon monolithic semiconductor integrated circuit chip. These FETs
Since they are manufactured under almost the same conditions except for the conductivity type of the gate electrode, the difference in Vth between the two is approximately equal to the difference in Fell unit between P-type silicon and N-type silicon. Each gate electrode is doped with each impurity near the saturation concentration, and this difference is the silicon energy gap E, (approximately 1, I
V), which is used as a reference voltage source.

A reference voltage generating device based on such a structure has low temperature dependence and small manufacturing deviation, so it can be used as a reference voltage generating device for various electronic circuits.

The present invention and further objects thereof will be more clearly understood from the following description with reference to the drawings.

Numerous documents explain the physical properties of semiconductors, starting from the crystal structure of semiconductors and extending to the energy-ψ band of semiconductors and the phenomena caused by donor and acceptor impurities in semiconductors.

It is of course well known that semiconductors of different compositions each have a specific energy gap, and that the energy gap Eg, expressed in eV, has the dimensions of a voltage. However, as mentioned above, there has never been an example in which semiconductors have a unique energy gap Eg and this temperature dependence is small, and this is used as a reference voltage source.

Since this embodiment was developed starting from the basics of semiconductor physical properties, a detailed explanation of the present invention will first start from the fundamentals of the present invention with reference to the physical properties of semiconductors. The physical properties of semiconductors are explained in detail in many documents, and the following is one of them, S.

M, SZE, 'Physics of Sem1c
onductorDevices”, 1969Jo
Published by hn Wiley & 5ons, special 1cch
apter 2 ”Physics and Prop
ertiesof Sem1conductors −
A brief explanation with the help of A Resume' pages 11-65.

Snake-iroji-22! ! '; f E (D and black) There are various compositions of semiconductors, but the most representative semiconductor currently used industrially is the non-compound semiconductor of germanicum (G e ) + silicon (Si). and galycum... are arsenic (GaAs) compound semiconductors.The relationship between these energy φ gap Eg and temperature is explained on page 24 of the aforementioned book, and this is
Elevate to figure.

As understood from FIG. 1, Ge, Si and GaA
The Eg of s is 0.80 at room temperature (300K), respectively.
(eV), 1.12 (eV) and 1.43 (eV). In addition, the temperature dependence is 0.39 (
m e V/K), 0.24 (m e V/K)
and 0.43 (meV/K). Therefore, by extracting a voltage corresponding to or close to the energy gap Eg, the temperature dependence of the forward voltage drop vF of the PN junction diode and the threshold voltage Vth of the IGFET can be reduced by one order of magnitude. A reference voltage generation IA-position having a small temperature dependence is also obtained. moreover,
The voltage obtained is the semiconductor-specific energy m-gap Eg
For example, in the case of Si, the voltage is determined to be about 1.12 (V) at room temperature, almost independently of other factors, and it is possible to obtain a reference voltage that is not easily affected by variations in manufacturing conditions, etc.

Now, an example will be explained based on which principle the voltage corresponding to the energy gap Eg of this semiconductor can be extracted.

The state of energy levels when a semiconductor is doped with donor and acceptor impurities is well known. In particular, what we have focused on in this invention is that the 7 Hermi energies of N-type and P-type semiconductors are located toward the conduction band and valence band, respectively, based on the Fermi energy level Ej of the intrinsic semiconductor. It is a physical property that it is divided into two parts. The higher the concentration of acceptor and donor impurities, the more the 7-luminium unit Ei of the intrinsic semiconductor
With a tendency to further deviate from
p approaches the upper limit level Ev of the valence band, and the fer r level Efn of the N-type semiconductor approaches the lower limit level Ec of the conduction band, and the difference between the two fer levels (Efn - Ef, ) can be taken. Ba,
This approaches the energy gap Eg of the semiconductor, and its temperature dependence also approaches that of the energy gap Eg. As will be described in detail later, the higher the impurity concentration, the smaller the temperature dependence (Efn-Efp), and it is preferable to keep the concentration as close to the saturation concentration as possible.

The Fermi unit Efn p Efp is related not only to the concentration of donor and acceptor impurities but also to the donor and acceptor levels Ed and Ea&C, and these levels Ed,
Ea varies depending on the impurity material1, levels Bd and E
The closer a is to the conduction band and valence band, respectively, the closer the Fermi levels Efd and Efa are to each. In other words, the donor and acceptor impurity levels Edlf
The shallower is the difference in the 7-luminium level (Efn ``fp), the more the energy of the semiconductor 11 V, -π, t, tA to the donor and acceptor impurity unit Ed.

The closer Ef is to the Fermi level Ei of the intrinsic semiconductor, that is, the deeper it is, the further the Fermi unit difference (Efn-Bfp') is from the semiconductor energy gap Eg. However, this does not necessarily mean that the temperature dependence becomes worse, but the Fermi level difference (E
This means that the absolute value of fn-Bfp) becomes small. Therefore, the Fermi level difference (Efn −Efp)
is unique to semiconductor materials and impurity materials, and from another perspective, it can be regarded as a reference voltage source on par with the energy gap Eg, which is in a different category from the semiconductor energy gap Eg. In other words, the Fermi level difference (Efn-Efp
) itself increases the forward voltage drop VF and I of the PN junction.
It has less temperature dependence than the threshold voltage Vth of GFET and can serve as a reference voltage source that is less affected by manufacturing variations. Difference (Efn-Ef
Therefore, extracting p) can be one way to extract a voltage close to the energy gap E of the semiconductor. On the other hand, in terms of setting the voltage value to be obtained, if the aim is to obtain a relatively large reference voltage equivalent to the energy gap of the semiconductor,
When an impurity exhibiting a shallow level is used and the purpose is to obtain a relatively small reference voltage, an impurity exhibiting a deep level may be used.

Fermi level Bf, donor level Ed, acceptor level E
. , donor concentration Nd, acceptor concentration Na and temperature T
The relationship between Ge, Si and G will be explained in more detail with reference to FIGS. 2 and 3.
In order to understand what level each impurity exhibits in the aAs semiconductor and how to use these impurities in the present invention, the data on page 30 of the above-mentioned document is used as Figure 4. Figures 3(a), (b) and (C), respectively, are
Ge.

It is a diagram showing the energy distribution of various impurities with respect to Si and GaAs, and the numbers in each diagram represent the energy from the lowest unit of the conduction band EC for the level located above the center Ei of the gap represented by the broken line. Difference (EC
-Ed), and for the lower level, the energy difference from the uppermost level Ev of the valence band (Ea-Ev)
The unit is (eV).

Therefore, impurity materials indicated by small numbers in the same figure indicate that their units are close to the lowest level EC of the conduction band or the highest level Ev of the valence band, and the energy gap Eg It is suitable as an impurity to obtain a similar voltage. For example, for Si, which is currently widely used, the level difference (Ec-Ed) of donor impurities of Li, Sb, P, As, and Bi and acceptor impurities of B, AI, and Ga, ( Ea-Ev) is the smallest, and each level difference is about 6% or less of the Si energy gap Eg.

The difference in Fermi levels between N-type Si and P-type Si using these impurities (CEfd - Efa) is approximately 94% to 97% of the energy gap E of 54, if the temperature change from 0'K is ignored. Therefore, is a value equal to Eg. In addition, the second smallest −S phase difference (Ec E
The donor impurity exhibiting cl)-(Ea-Ev) is S(E
(about 16% of Eg), and the acceptor impurity is In (about 14% of Eg), and the difference in r level (Efd - Efa) of N-type Si and P-type S1 using each impurity is OK. It is found that the deviation in the energy gap Eg of Si is about 15%, and the deviation becomes extremely wide with respect to the above-mentioned impurities.

Below margin l/ Therefore, P type and Nlj to obtain a voltage approximately equal to the energy gap Eg of Si! As the impurity material for ISi, one donor impurity selected from the group of Li, Sb+P, As and Bi and one acceptor impurity selected from the group of B, A4 and Ga are suitable, and the other impurities are Si It would be suitable for the purpose of obtaining a voltage considerably smaller than the energy gap Eg of .

7 Physical properties of the lumi level EfNext, regarding the Fermi level difference (Efn-Efp),
The physical properties will be explained with reference to FIG. Figure 2 is a diagram showing the energy levels of a semiconductor, with (a) and (
Figure b) shows an energy level model of an N-type semiconductor and its temperature characteristics, and Figures (c) and (d) each show an energy level model of a P-type semiconductor and its temperature characteristics.

Carriers in the semiconductor are electrons nd generated by ionization of the donor impurity Nd, and pairs of electrons and holes excited from the valence band. When the impurity Nd is sufficiently large, the excited electron and hole pairs can be ignored, and the number n of conduction electrons is n+nd (1). nd is the probability of being trapped in the donor level,
Further, n is determined from the number of electrons present in the conduction band, and is determined by the number of electrons present in the conduction band. Here, h&h: blank constant, m*: effective mass of electron.

Here, the first term of equation (5) can be ignored since the Fe level ε is determined to be at a position close to EC.

This equation shows that when the temperature is low, the Fermi level is located between the lower end of the conduction band and the donor level, and the temperature dependence is approximately equal to the temperature characteristic of EC.

However, if the temperature is sufficiently high, electron-hole pairs excited from the single valence band will become hyperactive, and the influence of impurities will be small (the Fermi unit will be at the level E of an intrinsic semiconductor). The relationship described above is shown in Figure 1 (
b).

In the case of a P-type semiconductor containing only acceptor impurities as shown in FIG.

The Fermi S level is located approximately between the top of the valence band and the acceptor level, and as the temperature increases, it approaches the Fermi level of an intrinsic semiconductor.

This relationship is shown in FIG. 1(d).

The relationship between the temperature characteristics of the Fermi level Ef and the impurity concentration - Specific example 7 We have explained the physical properties of the relationship between the temperature dependence of the Fermi levels Efp and Efn and the impurity concentration. Using Si semiconductors in practical use as a specific example, we will explain the Fermi unit difference (fn-E(p) and its temperature dependence in practical use, with reference to the data on page 37 of the aforementioned book. Figure 3 shows the data.

In the normal Si semi-semiconductor integrated circuit manufacturing process, boron B and SyP are mostly used as impurity materials, and in areas where the impurity concentration is high, 10" (atoms/m
'), but the impurity concentration is 10'' (
Even if atoms Δ), as can be read from Figure 3, the Fermi level difference (E
fn-Efp) is 0.5- (-
0,5) -1,0 (eV), which is a relatively close value to the energy gap E g" 1.1 eV K at the same temperature. The change with temperature is from 200°K to 400°K.
(-70°C to 130°C), approximately 1.04 (eV)
o, 56 (eV), the rate of change is 0.9 (
mV/'C). This is a small value of about 1/3 of the previously mentioned rate of change of the threshold voltage Vth of the IGFET and the forward drop voltage vF of the diode with respect to temperature, which is 2 to 3 mV/'C.

If the impurity concentration is 10"0X-3 or more, silicon energy #df-df-wyp(Eg) S t-1-1(V
) K becomes equal and the rate of change of temperature is about 0.2 mV
/'C, which is a sufficiently small value.

Therefore, if the impurity concentration is about IQ"01-3 or more, it is small (temperature dependence reduced to 1/2 to 1/3 compared to the conventional one can be obtained, and more preferably lQ"01-
3 or more (improved to about 1710), and most preferably saturation concentration.

In the theory and example, we will explain on what principle the voltage corresponding to the Fermi level difference (Efn - Efp) can be extracted. Two MOSs with different semiconductor gate electrodes
This method utilizes the difference in threshold voltage Vth of the FETs. A specific example will be explained below.

FIG. 5 shows a conceptual cross-sectional structure of each FBT. Hereinafter, for the sake of simplicity, a MOS transistor with a gate electrode of a P+ type semiconductor will be referred to as a P+ MOS transistor, and a MOS transistor with a gate electrode of an N+ type semiconductor will be referred to as an N+ MOS transistor MO8. FIG. 6 shows that in the general 0MO8 manufacturing process, the above P÷ Gegu MO8 and N+ Gegu MO8 are obtained without any change or addition of the final process.
It is a sectional view of one main food item showing that it can be manufactured.

Figure 7 shows the pattern actually used in the circuit structure.
- This is a detailed explanation of the case of a channel MOS transistor, together with the cross-sectional structure.

In Fig. 7, in order to obtain a self-aligned structure,
At both ends of the gate electrode in contact with the source and drain, there is a P+ gate MOS because it is a P-channel MOS transistor in this case.

P impurities are diffused into both N+Dag-MOSs. In the center of the gate electrode, a P-type impurity is diffused in the P+Goo-MOS, and an N-type impurity is diffused in the N+Dug-MOS. A region in which no impurity is diffused is provided between the central region and both ends in contact with the source and drain, and the difference between the P10-MOS and the N+DC-MOS is simply the central region of the gate. Care has been taken to ensure that the region is only a P-type medium conductor and a %N-type semiconductor.

Furthermore, the pI of the gate taken for self-alignment
Sl! The deviation (change) in the effective channel length of the MOS transistor due to the impurity diffusion region being biased to the left or right side (source side or drain side) during manufacturing due to mask alignment errors is minimized. As shown in FIG. The difference between left and right) is FEf of each column.
Even if the effective channel length of f' changes, the average effective channel length of the P+Goo-MOS and N+Dag-MOS of each column connected in parallel will remain constant as long as the overall deviation is canceled out. Become.

Figure 6 shows how P+Goo)MOS and N''Ge) are formed in the normal silicon G)0MO8 manufacturing process.
This shows how the MOS is configured.

(a) In the figure, 101 is N with a specific resistance of 1Ω to 8Ω.
A thermal oxide film 102 is formed on the silicon semiconductor, and a window for diffusion is selectively formed thereon using a technique of forming a thermal oxide film 102. Boron, which will serve as a P-type impurity, is ion-implanted at an energy of 50 KeV to 200 KeV in an amount of about 10'' to 10''am-'', and then thermally diffused for about 8 to 20 hours to form a substrate for an N-channel MOS transistor. A P-fel 103 is formed.

(In Figure b1, the thermal oxide film 102 is removed, and the thermal oxide film 104 is formed to a thickness of about 111 m to 2 μm to form a MOS.) Regions that will become the source, drain, and gate of the transistor are removed by etching. Thereafter, a gate oxide film 105 of about 300λ to 1500A is formed.

On top of that, polycrystalline Si 106 is applied at 2000A to 6000A.
It is then removed by etching, leaving only the gate portion of the MOS transistor.

In the figure (c), an oxide film 107 is formed by vapor phase growth and removed by photoetching in the region where P-type impurities are to be diffused. After that, boron, which becomes a P-type impurity, is diffused to a high concentration of 1020 to 10" to form the source of a P-channel MOS transistor.

A drain region 108 is formed, and at the same time, a P-type semiconductor gate electrode is formed.

(In figure d1, the oxide film 1 is formed by vapor phase growth as before.
09 is formed, and a region where N-type impurities are diffused is removed by photoetching. After that, phosphorus, which becomes an N-type impurity at a high concentration of about 1020 to 1O-, is diffused into the source and drain regions 110 of the N-channel MOS transistor.
, and simultaneously form a KNN type semiconductor gate electrode.

(In Figure e1, the oxide film 109 is removed, an oxide film 111 with a purity of 4000A to 8000A is formed by vapor phase growth, and the electrode extraction part is removed by photoetching. Thereafter, gold M (An) is vapor deposited and then photoetched. The electrode wiring portion 112 is formed using a technique.

In the figure (f), an oxide film of 1 μm to 2 μm is formed by vapor phase growth.

Next, the threshold voltage of a MOS transistor using a semiconductor as a gate electrode will be explained with reference to FIG. First of all, for the case of P+Goo) MOS, see Figure 8 (
From the energy band diagram in a), φM φ.

It is shown that

However, here: ■G: Potential difference between the semiconductor substrate and the gate electrode (p+ conductor) 7 Hermi potential φ2 of a P-type medium conductor; Fermi potential q of an N-type semiconductor substrate based on the Fermi potential of an intrinsic semiconductor; unit charge of an electron ■. ; Potential difference Ec applied to the insulator; Lower limit Ev of the energy level of the conduction band; Upper limit Ei of the energy unit of the valence band; Fermi level of the intrinsic semiconductor In equation (7), the work function of the gate electrode is expressed as a potential. Assuming that φMP is ten, and the number of semiconductor parts J#IE is similarly φ81, then Vo−−VG+φM−φ8goφg・”(10).

Also, from the relationship of charges in Figure 8 (bl), -COX・Vo+Qss+Qi+Qa=0 ``'αυ. Here, COX is the capacitance of the insulator per unit area, Qss is the fixed charge in the insulator, QB is the impurity in the semiconductor substrate. Fixed charge Ql due to ionization; carrier field formed as a channel, −COX (−Vo + φMP + −φ8 − φ5rf) + Qs from αυ
s +Qi +Qp -0·”03.

Gate voltage when channel Q+ is formed ■. is the threshold voltage, so P+g) MO8L cox co
x ""3 At this time, φ8-2φ2.

Similarly, in the N+GEGMO8) transistors, the only difference is the work function φMN+ of the gate electrode. Therefore, the threshold voltage VthN0 is φ
It becomes 8-2φF.

From this, the difference in threshold voltage between the P+ gate MOS and the N+ gate MO8, Vthp"-VthN+, is vthp""-
■thN"φMP+-φMN"-φFP"-φFN+・
...0e, and the Fermi of the cow conductor that makes up the gate electrode
It becomes a difference in potential. This is shown in (a) in Figure 8.
, (c), the gate voltage when the potential distribution is the same is the work function difference between the gate electrodes, and Fermi
This can be easily understood by the difference in levels.

The above explanation is based on the case of a P-channel type MO8) transistor, but the same applies to the case of an N-channel type MO8) transistor.

Next) A circuit for extracting the difference in Vth of CMOS transistors will be explained.

The circuit explained below is based on the above-mentioned 7-luminium level difference (Ef
This can be one way to extract n-Elp'), but
In addition, the present invention can generally be applied as a reference voltage generation device that uses a voltage based on the difference in Vth of FETs having different Vths as a reference voltage.

FIG. 9(b) shows a circuit that generates a voltage corresponding to the threshold voltage of a MOS transistor. The drain and gate of T and IT were commonly connected. It constitutes a so-called MOS diode.

Io is a constant current source, T, , T are different threshold voltages Vt
It is a MOSFET with mutual conductance β almost equal to hl and Vth2, and each drain voltage V, ,
V, then ■. −−β(V+ −Vl)B )” 1 −β(Vz −Vthx ) ” Since −Q71, v, −Vth+ +p calendar/I −tJ&V, −vth
, 10J2 I. /l/-09, and by taking the difference in drain voltage, it is possible to extract the difference in threshold voltage.

As a constant current source, you can use a sufficiently large resistor, and as long as it has the same characteristics, you can use a diffused resistor.

Polycrystalline St resistor resistor made by bayon implantation,
MOS) resistors can be used.

In this circuit, N+Dag-M, which was explained earlier as T, ,T,
By using an OS and a P+ gate MOS, it is possible to extract the Fermi level difference ("'fn-Efp)" between the N-type semiconductor and the P-type semiconductor, which is approximately equal to the difference in threshold voltage.

In addition to changing the composition of the gate electrode, it is also possible to create a different threshold voltage by, for example, implanting ions into the channel, doping the gate oxide, changing the thickness of the gate insulating film, etc. , if this is applied to the circuit shown in Figure 9, the difference in threshold voltage corresponding to the amount of ion implantation, the amount of impurity implanted in the gate insulating film, and the threshold voltage depending on the thickness of the gate insulating film. Based on the difference as well! s! It can be taken out as pressure.

For example, it is well known that in the ion implantation method, the implantation amount can be monitored in the form of current, so the accuracy of impurity concentration is extremely good compared to normal diffusion. Figure 10 shows this situation. It is. M before ion implantation
OS) Assuming that the characteristic of the transistor is T, the threshold value varies by ΔVth after ion implantation, and even if each transistor is balanced, the difference in threshold voltage between the two is Since Δvth is determined by the amount of ion implantation, there is extremely little variation, and similarly, it can be used as a reference voltage with little manufacturing variation. In other words, if Vthx is the threshold voltage of the transistor T (MOS) without ion implantation, it is the same as Equation 09, and the increase in the fixed charge of the substrate due to ion implantation is Δ
Q, then ion-implanted MOS) transistor T
The threshold voltages Vth2 of , are adjacent to each other. The temperature change in this threshold voltage difference voltage is ΔQ
Since B is almost constant against temperature changes, it is extremely small.

Another great advantage is that the base s'fiL pressure can be freely changed depending on the amount of ion implantation, and that it can be easily realized even in a single channel Pwtos manufacturing process.

Figures 11 and 12 in the following margin are examples of circuits in which FETs having different threshold voltages are connected in series in the form of MOS diodes to extract the difference in threshold voltage. It is assumed that T has a threshold voltage V and h1#'rt has a threshold voltage ■the.

Under the condition that the resistance R3 is sufficiently large compared to the impedance of T, and the resistance R1 is sufficiently large compared to the impedance of T, Vt −Vt +V, ), 1−−−−−−+23V +
* V @ h2 ...... (to) Therefore, ■!
``thl-vthe'' (c).

18+ in FIG. 13 applies a voltage corresponding to the threshold voltage between both terminals of the capacitor, and extracts the voltage held in the capacitor as a differential voltage. FIG. 13 18+ shows the operation timing. By turning on Ts and Ts by clock pulse φI, capacitance c, VC'rt,
'r, (F'lLJ i value [pressure Vth1. Vth.

Charge the voltage difference between.

After φ, is turned off, T is turned on by clock φ, and C
Ground node 3. At this time, since the difference voltage between the threshold voltages of C and K is maintained, that potential is output as is to the node (2). When used in a voltage detection circuit as described later, the potential of node (2) at this time can be used as it is as a reference voltage. Since K can be used in a more general form, K can be transformed into a transformer by clock φsK during the time when clock φ is entered.
If s and T are turned on and the potential is taken into the capacitor C, and the output is fully fed back to the negative phase input (-) of the operational amplifier 5, it is received by a so-called voltage ◆ follower. In a state of low impedance, 'r
, 'r' is obtained as a reference voltage.

FIG. 14 shows a reference voltage generating device that similarly utilizes the capacitor C1. Ts is turned on by the clock φ. At this time, T is in an off state due to clock φ. The potential of node ■ is higher than the potential of node ■ by the threshold voltage Vthl of T,
The potential of node ■ is lower than the potential of node ■ by T,
The threshold voltage of C is lowered by thg, and the difference voltage between the two is charged across the capacitor C. Next, T is turned off by φI, and φ! When T is turned on, a voltage difference between the threshold voltages is obtained at the node (2).

FIG. 15 shows a known operational amplifier used in the circuit of FIG. 13. T, ,T, is a differential pair constituting a differential amplifier circuit, and TI.

Ts is its active load. T constitutes a constant current circuit together with Ts and a bias circuit with T<K. T.I.
, T? is a level conversion/output buffer circuit with T as a constant current source load. Although the figure shows an example of the circuit configuration using c-Mos, it goes without saying that it can also be configured with a single-channel MO8.

In addition, in this operational amplifier, the differential pairs T, , T, and K constituting the differential amplifier circuit are given different threshold voltages by the method described above. The difference can be used or extracted as a reference voltage, and this is an unprecedented application of an arithmetic multiplier.

FIG. 16 schematically represents a general operational amplifier by taking only its differential part.
S) The transistors T, , T, each have a different threshold voltage■
thl e■th2, and other characteristics are assumed to be equal. Also, (-) and (
The signs (+) indicate that the outputs are in opposite phase and in phase, respectively.

If the input of T is V, and the input of T is ■, then V+
-■tbl= Vt V1h2 Tsumari■i 't""
tht VthS -...With the condition of w as the boundary,
The output level changes.

An operational amplifier has an input offset equal to the difference between the threshold voltages, and if one of the inputs is connected to ground or the power supply, it can operate as a comparator using this offset voltage as the reference voltage. I can do it. Therefore, as shown in FIG. 16, if the output is connected to the (-) input terminal and the +) input terminal is grounded, a difference in threshold voltage can be obtained for the output outK. In this case, in order to operate the operational amplifier, T needs to be a deplexing voltage. For example, P+ Gegu MOS in T1.

When using T, KN + Gamegoo O8, both M
Ion implantation may be performed in the channel portion of the OSFET under the same conditions to form a deep gin type.

FIG. 17 shows a summation using the operational amplifier in FIG. 16 so that the reference voltage can be set arbitrarily. If the output is fed back to the (-) input through the voltage dividing means R, , R, and the voltage dividing ratio is r, the output voltage will be ■. becomes ■thx −vthl vo==□ ・・・・・・■. The voltage dividing means Rs, R, is preferably a linear resistance, but
Any resistor may be used as long as it has sufficiently uniform characteristics to be acceptable.

The circuits shown in FIGS. 16 and 17 are based on the assumption that a depression type MO8 is used, whereas the circuits shown in FIGS. 18 and 19 are designed to be operable with an enhancement type MO8. Of course, it doesn't matter if it's a Depledge Gin type.

The example shown in FIG. 18 is similar to the example shown in FIG. 16, in which the output is directly fed back to the (-) input, and the output is ■. is the power supply voltage ■D
If D, then "'=VDD-(vthl-■tbs) °"-@. In the circuit shown in Figure 16.17, it is necessary to set one of the differential pairs to the depletion mode, which may require an increase in the number of manufacturing steps depending on the case. It can be dammed based on.

Conversely, in the circuits shown in Figures 18 and 19, the reference for the resulting differential voltage is the power supply voltage other than the ground potential, but there are no particular conditions for the operating mode of the FET.

Which circuit format to adopt can be decided depending on which advantages and disadvantages are considered.

The example in FIG. 19 is the same as the example in FIG.
The output is fed back to the (-) input through , and the output is .

Figure 20 shows how the reference voltage from the reference voltage generator that uses the difference in Vth is added to one input of the comparator, and the voltage to be detected is added to the other input. This is a voltage detection circuit that allows for differentiation.

In the example shown in Fig. 21, a reference voltage from a reference voltage generator that utilizes the difference in Vth is added to the comparator's output, and the detected voltage is divided into the other input by voltage dividing means Re and Ro. This is a voltage detection circuit that applies voltage.

The voltage division ratio is r, the reference voltage is ref, and the detection level is vse.
nse, and the detection level v, e□ due to the partial pressure ratio r. can be set arbitrarily.

The example in FIG. 22 uses an operational amplifier with an offset corresponding to the difference in Vth, and uses an off-set signal as described above.
This is a voltage detection circuit that uses a set voltage as a reference voltage. Further, R+t-R□ is the same voltage dividing means as in the example of FIG.

In the example of Figures 20, 21, and 22, if the voltage to be detected is the power supply voltage, it can be used as a battery checker in a system that uses a battery as the power supply. A specific example in which the voltage detection circuit of FIG. 22 is applied to a battery checker for an electronic watch is shown in FIG. 29, and detailed explanation will be given later.

The example shown in FIG. 23 is applied to a stabilized power supply circuit. The reference voltage generation circuit is configured using several methods described above, and compares a part of the stabilized output with the reference voltage using R,,lR,, and adjusts the gate of T'to so that they match. Control voltage and stabilize output voltage. Any operational amplifier may be used as long as its characteristics are acceptable.

The example in FIG. 24 is T, in the example in FIG. Bipolar transistor T instead of using transistor (MOS) transistor
R, is used.

The example shown in FIG. 25 uses an operational amplifier having the offset voltage shown in the example shown in FIG. T□ may be a MO8 transistor, a bipolar transistor, or a junction field effect transistor.

The example in FIG. 26 is a constant current circuit determined by the difference in threshold voltage between T and Tm.

Tz and Tt have the same transconductance, but have different threshold voltages Vthl e Vthj. If the resistance R2゜ is sufficiently high compared to the impedance of Tl, the drain voltage (=gate voltage) V+ of T is V
It becomes almost equal to th□.

When T, is in the saturated region, the electric light flowing through T.

■=-β(Vtht-Vtbs)” −−−−−−
C3f).

The example in Fig. 27 is a voltage drop system using the current IK flowing through T□. This is a constant current circuit that compares utRlI with a reference voltage ref and controls the gate voltage of KT so that both are always equal.

・・・・・・(To) becomes.

Here, the reference voltage may be obtained by providing an operational amplifier with an off-set, as in the previous example.

The example shown in FIG. 28 is a constant current circuit using the same transistor as T□tT'ss and using a so-called current mirror circuit.

The example shown in FIG. 29 is an example in which the battery checker shown in FIG. 22 is applied to an electronic watch.

TI HTtr T41~T41 and R4, and R4
, constitutes a circuit that checks the voltage level of a mercury battery E, nominally 1.5V. The transistor pair in the differential section is set to P+
Consists of gate/N-channel MOS, N+gegu/N-channel MO8T, T, so that the threshold voltage of both is within 1.0V to 1.5■, which is the operating power supply range of electronic watches. , ion implantation is applied to the channel part.

The difference between the threshold voltages that serve as reference voltages is approximately 1.1■ in the case of silicon semiconductors, and the resistance means R+ is used to adjust the level at which the voltage drop of the battery is detected to around 1.4■. - It is adjusted by the resistance ratio of Rt.

This battery checker operates intermittently using a clock signal φ obtained from the 1-frequency divider circuit FD through the timing circuit TM in order to reduce the current consumption to a practically negligible level.

The output of the battery checker is NAND gate goo I
, NA! The logic level of this latch circuit output controls the timing circuit TM, which changes the drive output of the motor, changes the way the hands move, and changes the battery voltage. A decrease in battery voltage can be indicated without changing the movement of the pointer, or by blinking an electro-optical element such as a liquid crystal or a light emitting diode.

In the figure, O8C is a crystal oscillator circuit that is composed of a CMOS inverter and includes a crystal Xtal and a capacitor CGICD outside the IC, WS is a waveform shaping circuit that converts the oscillation output from a sine wave to a rectangular wave, and CM BF is an excitation coil of a step motor that drives the second hand, and BF is a buffer for driving the excitation coil CM, which is composed of a CMOS inverter and inverts the polarity every second.

All circuits in the IC are nominally 1.5v mercury battery E.

It works. TM is a timing pulse generation circuit that generates pulses with arbitrary periods and pulse widths by inputting the divided outputs of a plurality of different frequencies of the frequency dividing circuit FD and the control output of a latch composed of NA, , NA, etc. It is. The IC is a monolithic Si semiconductor chip for a pointer type electronic wristwatch manufactured by the Si Gegu CMOS process shown in FIG.

The present invention has been described above based on various embodiments, but
Without being limited to this, the technical ideas described herein may be applied to electronic devices for various other uses.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the energy gap Eg of GaAs, Si, and Ge semiconductors and its temperature dependence. Figure 2 is a diagram showing the band structure and Fermi level Ef of a semiconductor, where +u # tbl is an N-type semiconductor, lc
l and ldl indicate examples of P-type semiconductors. FIG. 3 is a diagram showing the temperature characteristics of the Fermi level of N-type and PWSi with impurity concentration as a parameter. Figure 4 1al,
lbl and (cl are diagrams showing the energy level distributions of Ge, Sl, and GaAs semiconductors, and various donor and acceptor impurities, respectively. Figure 5 shows the Fermi unit difference (E
Fig. 3 schematically shows the cross-sectional structure of a P+ gate and N+ gate MO8FET that can be used to extract fn-Efp), with the left half showing the P-channel FET and the right half showing the N-channel FET. Figure 6 (secondary to 1fl are N+gegu (B part) and P
+Gate (A part) P-channel MO8FET constitutes a normal complementary MO8
(section C) and an N-channel FET (section D). It is a sectional view in a main process. Figure 7 1al, tl)I respectively show a plan view and a cross-sectional view of an N+Goot P-channel MO8FET;
ldl shows a plan view and a cross-sectional view of a P+gegu P-channel MO8FET, and the line indicated by the arrow in each plan view is assumed to be the cutting line of the cross-sectional view. Figure 8 1al and tbl show the energy state and charge state of the P+ type semiconductor-insulator-NfJ conductor structure, respectively, and Figure 1cI and tdl show the energy state of the N+ type semiconductor-insulator-N type semiconductor structure, respectively. FIG. 3 is a diagram showing the state of charge. FIG. 4 1al p tbl are respectively different threshold voltages V
10 is a characteristic diagram of a MOS diode circuit for extracting the difference in Vth between two FETs having th, and a diagram showing the circuit. FIG. 10 is a characteristic diagram showing how Vth changes due to ion implantation. 11 and 12 each show an example of a reference voltage generation circuit that utilizes the difference in Vth, FIG. 13 (181) shows an example of another reference voltage generation circuit, and FIG. shows. FIGS. 14 to 19 show reference voltage generating circuits according to still other embodiments. Figures 20 to 22 show examples in which they are applied to voltage detection circuits, and Figures 23 to 25 show examples in which they are applied to voltage regulators.
Figures 26 to 28 show examples of applications to constant current circuits.
Figure 9 shows an example of application to a battery checker for electronic wristwatches. T...MOSFET, R...resistance, C...capacitor, Xtal...crystal resonator, O8C...crystal oscillation circuit, WS...sine wave-square wave conversion waveform shaping circuit,
FD...Binary power counter multi-stage connection frequency divider circuit, TM...
Timing circuit, CM... Excitation coil # of the step motor for driving the second hand, BF... Buffer for driving the CM, N
A...NAND gate, IC...monolithic Si
Semiconductor integrated circuit chip, φ...clock pulse, Eg
...Energy gap of the semiconductor, Ev...The highest level of the valence band, E,...The lowest level of the conduction band, E
i...Fermi level of intrinsic semiconductor, Efn, "fp
...Fermi level of side-type, P-type semiconductor, Ed, Ea...
- Donor acceptor level. Figure 1 Figure 3 tct) Figure 2 Figure 4 (a-) Figure 9 (L) (b! Figure 11 Figure 12 Figure 13 (σ) District 14 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25

Claims (1)

[Scope of Claims] 1. A first cell having a threshold voltage difference according to the Fermi level difference of the gate electrode. A constant current circuit comprising a second IGFET and generating a constant current using a reference voltage formed based on this threshold voltage difference. 2. The drain of the first IGFET is DC coupled to the gate thereof, the first IGFET is provided between the gate and source of the second IGFET, and the first IGFET is provided between the gate and source of the second IGFET, and the first IGFET is provided between the gate and source of the second IGFET. 2nd IG
The constant current that is suitable for the threshold voltage difference of the FET is the second
2. The constant current circuit according to claim 1, wherein the constant current circuit is configured to flow through the drain of an IGFET. 3. Above 1. 3. The constant current circuit according to claim 1, wherein each gate electrode of the second IGFET has a semiconductor layer portion having a different conductivity type.