JPS60248046A - Address system of receiver in digital transmission system - Google Patents

Abstract

PURPOSE:To attain various controls at a high speed with rich flexibility and simple constitution by adding a control data to plural receivers to a service bit of a system. CONSTITUTION:A signal of an analog signal subject to A/D conversion 7-10 from, e.g., terminals 1-4 in a wired TV system or the like, an FAX signal from a terminal 5 and a game software signal from a terminal 6 are inputted to a multiplexer MPX12. The MPX12 distributes an input signal to each channel, adds an error check code, scrmbles (13) and gives it to a synchronizing signal/ service bit generator 15. A synchronizing signal and a service bit are added at the generator 15, each control data is extracted from memories 17-18 and added to the service bit. The signals are equalized (20) and amplitude-modulated (21) and outputted while being subject to frequency conversion. The synchronizing signal, the service bit and the control data are separated from the detected and reproduced signal at the reception side, they are rearranged by a demultiplexer and outputted while being D/A-converted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to sending control data to each receiver in a digital transmission system having a large number of receivers as terminals, such as a cable television system. The present invention relates to an addressing method for a receiver in a digital transmission system suitable for use in digital transmission systems.

Background technology and its problems Conventionally, for example, in cable television systems,
When controlling each receiver, there are two methods: the so-called in-band method, in which control data is added to information data such as video data, and the so-called out-band method, in which control data is sent using a separate dedicated transmission path. 0ut-Band
) method.

However, in the case of the in-band method, since control data is added to the information data before being sent, it has drawbacks such as not being able to transmit large amounts of control data at high speed, and having no negative impact on the information data. .

In addition, in the case of the out-hand method, a dedicated transmission path must be used for control data, which requires a dedicated transmitting and receiving circuit, which has the disadvantage of complicating the circuit configuration and increasing costs. there were.

Purpose of the Invention In view of the above, the present invention provides a digital system that can simplify the configuration by adding control data for each receiver to the service bits of the system, and that can perform various types of flexible control at high speed. It provides an addressing scheme for receivers in transmission systems.

Summary of the Invention In the present invention, in a digital transmission system that serially transmits at least a plurality of service bits following a synchronization signal, the plurality of service bits are respectively made to correspond to predetermined digits of address numbers of a plurality of receivers, and the service bits are Control data is sent to each of the above receivers.

As a result, in the present invention, it is possible to transmit a large amount of control data at high speed, and it is also possible to control a variety of receivers with a high degree of flexibility, allowing group or simultaneous addressing in addition to individual addresses.

EXAMPLE Hereinafter, an example of the present invention will be described in detail based on FIGS. 1 to 8.

First, let's talk about the signal format used in this invention! ! Figure 81~6rI! This will be explained with reference to J.

Figure 1 shows the 1-word data format in neo format.
This l word consists of 168 bits, and as shown in FIG.
Service bit SR consisting of 4 bits.

128 bits (32 bits per ICFI for 4ch)
data, and 28 bits (1
It consists of an error check code C8 (7 bits per H, 4 CIs). The data other than the synchronization signal and service bit and the error check code are shown in Figure 1B.
As shown in the figure, the data of each channel and the error check code are exchanged bit by bit, and so-called bit interleaving is applied.

No. 21g1 shows the data format of one frame, and this one frame consists of 256 words with the data format shown in Fig. 1 as one word. The first word at the beginning is made up of the check code cs, and the next second word is the word sync Ward 5ync (11, service bit SR.

It consists of data and error check code C8, and the next third word is similarly word sync Ward 5sync (
2), service bit SB, data and error check code C8, and the last 256th
Word is Word Sync-ard 5sync (255)
, service bit SR, data, and error check code CS.

Incidentally, 4 service bits per word becomes 1024 bits per frame. In other words, there are 256 bits each of Sth to SB4 per frame. Therefore, in the present invention, as will be described later, the 256 bits (a predetermined number of bits) of each of SB1 to SB4 are used to send control data to each receiver.

The format for sending control data using service bits consists of five types of formats, as shown in FIG. That is, FIG. 3A is a unique service format (Llnique SBFormat).
, Figure 3B shows the group service format (Grou
SB Forysat), Figure 3C shows the channel service format (Channel SB Forysat).
rmat), the third diagram is the all-service format (8115B Format), and the third diagram E is the scrambling key format (Scramble K).
ey Portsat) are shown respectively. In Fig. 3 A to E, H is a header for identifying each format, C is a command for instructing each receiver what to do, and T is the address number of the receiver. ,
G, Ilh are group numbers that are grouped in arbitrary ways, such as the district where each receiver is located or the occupation of the owner, and Ti
er does not indicate the contract conditions of each receiver, such as allowing reception if it is below a predetermined level and not being able to receive it if it exceeds a predetermined level, and the tier level, CH, NO, indicates the music broadcast transmitted by this system. IIHY represents descramble key data (initial value data of M series) for descrambling data, and C5 represents an error check code. Also, as in FIG. 4, the command C in FIG. 3 includes commands such as start of emergency broadcast, start of communication broadcast, start of fax, start of data loading, etc.

As shown in FIG. 5, for example, in odd-numbered frames, each format in FIG.
SSF (or scrambling key format) is sent out alternately, while unique service format O8F is sent out individually in even-numbered frames.

Figure 6 also shows how the transmitting side allocates the unique service format to each receiver in memory. For example, the address number J+T of the receiver
, ll&l are binary representations, and when the lower two bits are "00", a unique service format as shown in Figure 6A is used, and when it is "01", a unique service format as shown in Figure 6B is used. , 10'', a unique service format as shown in Figure 6C is assigned, and when it is ``ii'', a unique service format not shown in Figure 6 is assigned.Of course, these four types of unique The service formats have different contents except for the head H. In the figure, ζ and N represent memory addresses, and L represents the length of the unique service format.

Next, how control data for controlling the receiver is added to the service bits will be explained separately for the receiver and the transmitter.

First, on the transmitter side, as will be described later, there is a memory for simultaneous information corresponding to the all service format, channel service format, and scrambling key format, a memory for group information corresponding to the group service format, and a unique memory. A memo for individual information for the service format and three memories are arranged, and data of people is transmitted alternately at the timing shown in FIG. 4, as described above. Then, the data in the memory for C1-simultaneous information and the memory for group information are stored in SR1-SR1 so that the receiver can select which service bit and receive °ζ.
The same data is transmitted to SB4. In addition, when transmitting a unique service format by adding it to the service bit, the memory map for individual information is
Draw it as shown in Figure A.

As described above, among the service bits SB1 to SB4, first add the unique service format shown in Figure 6A to SBt, add the unique service format shown in Figure 6B to SB2, and add the unique service format shown in Figure 6B to SB3. Adding the unique service format shown in Figure 6C, S
The unique service format shown in Figure 6 is added to B4. When a unique service format is added to a service pin for high-speed addressing, the unique service format is transmitted in the even-numbered frame sections shown in Figure 4, and at the same time, it is also temporarily transmitted in the odd-numbered frame sections. . Due to contamination, the cycle of the unique service format is longer depending on the number of receivers, but the cycle of the group service format is much more rectangular, so the four-speed transmission is H1
Becomes J Noh.

On the other hand, on the receiver side, the 4 bits SB+ added to the l word
- Number of SB4 - Manually input one service bit according to the own address number (T, Nn) among the bis pits. Immediately, bit 2 of own address number is “00”
It is as if inputting SB1 when the input is ``Ol'', SB2 when the input is ``Ol'', SR3 when the input is ``10'', and SB4 when the input is ``11''.

Then, the service bit corresponding to this own address number is manually input during one frame period in synchronization with the frame synchronization code.At this time, since the service bit is transmitted in serial full form, the microcomputer Data sampling and data error checking can be easily performed by using the serial port.

Next, of the service bits sampled during one frame period, only the data part excluding the start pit (.) and stop pit is synthesized.The format is as shown in Fig. 3 mentioned above.In other words, , the data sampled during one frame period corresponds to any of the formats A to E in Figure 3. Each format of A to F in Figure 3 is unique as shown in Figure 4 above. Service format and other service formants are 1
These formats are identified by the header H inserted at the beginning of each format.
carried out by

Next, the processing performed when each formant is received will be explained. First, in the case of the unique service format, a receiver whose own address number matches the address number specified by address number TJ&l has group number G,
The group number specified by Nll and the tier level specified by t are stored, and the process specified by command C is executed.

For group service format, group number G
, The receivers belonging to the group number specified by Na are:
Performs the process specified by command C.

In other words, a receiver whose stored group numbers G and Na specified in the unique service format match the bluef number specified in the group service format performs the process in which t is added by command C.

In the case of channel service format, the tier level of the data channel (music broadcast, etc.) transmitted by this system is specified for all receivers. Then, the tier level of the channel selected by the user is specified in the unique service format, and the service is started for the user only when it matches the stored tier level.

In the case of the all-service format, the command C specified unconditionally is processed, and in the case of the scrambling key formant, the data is descrampled with the key code specified unconditionally.

FIG. 7 and FIG. 8 show an embodiment of this invention in neo form.
FIG. 7 shows the configuration of the transmitting side, and FIG. 8 shows the configuration of the receiving side.

First, to explain the transmitting side in Fig. 7, the manual terminal (1
For example, analog information of stereo music is supplied to input terminals (3) and (4), analog information of contact broadcasts and guide broadcasts is supplied to input terminals (3) and (4), and facsimile information is supplied to input terminal (5). Digital information such as game software is supplied to the input terminal (6). Analog information from the input terminals (11 to (4)) is analog-
Digital converter (hereinafter referred to as A/D converter) (7) ~
At (to), the analog signal is converted into a digital signal, and the facsimile signal from the universal terminal (5) is supplied to the multiplexer (12) via the facsimile interface circuit # (11). In addition, the digital information from the input terminal (6) is directly transferred to the multiplexer (
12).

The input signal is then distributed to each channel by the multiplexer (12), subjected to signal processing such as addition of an error check code and bit interleaving, and then output. The output signal from the multiplexer (12) is supplied to one input terminal of a multiplier (13), and the other input terminal of this multiplier (13) is supplied to an M-series signal generator (1
4) is multiplied by the M-sequence signal supplied from 4) and scrambled.

The thus scrambled data and error check code are supplied to the next stage synchronization signal/service bit generator (15), where the synchronization signal and service bit are inserted. At this time, the memory (17) is controlled by the controller (16).

The above-mentioned collective information, group information, and individual information are extracted from (18) and (19), and supplied to the synchronization signal/service bit generator (15) to be added to the service bit. Further, the M-sequence signal generator (14) is configured to have its initial value (descramble key data) set in synchronization with the frame synchronization signal by the controller (16). Additionally, this initial value is changed at regular intervals to increase security.

In this way, the signal into which the synchronization signal and service bit have been inserted into the data is passed through the binary transversal filter (20), which serves as an isotherm, to match the frequency characteristics of the entire transmitting and receiving system to eliminate code interference. M modulator (21) where the carrier wave from the oscillator (22) is modulated by the output signal from the filter (20). An intermediate frequency signal is therefore obtained at the output of the transformer (21), which signal is fed through a reverberant sideband filter (23) to a mixing circuit (24) where it receives the local The signal is mixed with the oscillation frequency signal, frequency-converted, and outputted as a signal representing the difference between the local oscillation frequency and the intermediate frequency signal. In addition, the oscillation circuit (25
) is set to a frequency higher than the transmission frequency of any channel by the intermediate frequency. The transmission channel is therefore determined by selecting the local oscillator frequency.

The output signal from the mixing circuit (24) is taken out through a bandpass filter (26) to an output terminal (27), and the signal from this output terminal (27) is supplied to a so-called head end (not shown) of the CATV system. Ru. and,
Signals from the head end are supplied to the receiving side via a CATV line (not shown).

The signal thus transmitted via the CATV line is supplied to the front end (32) from the receiving side input terminal (31) shown in FIG. 8, where it is amplified and then
It is converted into an intermediate frequency signal of a predetermined frequency. This intermediate frequency signal is supplied to an AM detector, such as a PLL detector (33), where the baseband signal is demodulated. In addition, ^h
Although a detector used in a conventional television control system may be used, it is preferable to use a PLL detector as described above in order to avoid waveform distortion.

Also, part of the output of the PLL detector (33) is
I (34), which connects the front end (
32) is multiplied by 80C.

The output from the PLL detector (33) is sent to the data regeneration circuit (3).
5), and here, based on the clock signal regenerated by the clock regenerator (36) from the output of the PLL detector (33), the level is identified at the widest point of the eye pattern and digital data is extracted. . This extracted data is sent to the next stage synchronization signal/service bit separator (3
7), where the synchronization signal and service hint are separated from the data and supplied to the controller (3B), and the controller (38) synchronizes with the synchronization signal and performs various control operations. Control data added to the service bits is stored in a memory (39) via a controller (38).

The data from the synchronization signal/service node separator (37) is then fed to one input end of the multiplier (40).
This multiplier (40) is multiplied by an M-sequence signal from an M-sequence signal generator (41) supplied to the other input terminal, thereby descrambling and extracting the data. Incidentally, when changing the initial value of the M sequence signal generator (41), the initial value is set in synchronization with the transmitting side under control from the controller (38).

The data from the multiplier (40) is transferred to the demultiplexer (42).
), where signal processing such as data rearrangement (bisotode interleaving) and entertainment correction is performed. The digital signal from the demultiplexer (42) is sent to the D/A converter (45) via switches (43) and (44).
, (46), where the digital signal is converted into an analog signal and then output to the output terminal (47), (4
8) respectively. In addition, the switch (43) is the contact a
When it is on the side, the input terminal (1) on the transmitting side (7th sill)
When the input terminal (2) (Fig. 7) is on the contact side, the signal corresponds to the information from the input terminal (2) (Fig. 7), whereas when the sui-nochi (44) is on the contact a side, A signal corresponding to the information from the input terminal (3) (Fig. 7), and when it is on the contact side, a 76- signal corresponding to the information from the input terminal (4) (Fig. 7) is sent to the demultiplexer ( 42
) is switched and taken out in a time-divisional manner by address signals from .

A facsimile signal from the partial demultiplexer (42) is taken out to an output terminal (50) through a facsimile interface circuit (49), and digital data such as game sorting is taken out directly to an output terminal (51).

"Effects of the Invention" - As described above, according to the present invention, control data is sent to each receiver using the serially transmitted service bit of the system, so a large amount of control data can be transmitted at high speed with a simple configuration. In addition, since only the information for each unique address is transmitted for multiple service bits, the addressing speed becomes high.Furthermore, the format of service bits can be classified as shown in Figure 5. Therefore, group and simultaneous addressing is possible in addition to individual addressing.Furthermore, since the service bits are transmitted in a serial format, control data can be easily sampled.

Furthermore, since the channel service format and the unique service format are used, the contract conditions of each data channel can be changed easily and quickly in real time. Further, since the scrambling key format is provided, the descrambling key can be changed easily and quickly.

[Brief explanation of drawings]

Figures 1 to 6 are diagrams showing an example of a signal format used in the present invention, Figures 7 and 8 are diagrams showing one embodiment of the present invention, and Figure 7 is a diagram showing an example of a signal format used in the present invention. , jFj8 are respective Pronk diagrams on the receiving side. (12) is a multiplexer, (13) and (40) are multipliers, (14) and (41) are M-sequence signal generators, (1
6). (38) G;! Control 1m, (17) ~ (19),
(39) memory, (15) synchronization signal/service bit generator, (33) PLL detector, (35) data regeneration circuit, (37) synchronization signal/service bit M
I! , (42) are demultiplexers.

Claims (1)

[Claims] In a digital transmission system that serially transmits at least a plurality of service bits following a synchronization signal, each of the plurality of service bits corresponds to a predetermined digit of an address number of a plurality of receivers, and the service bit controls each of the receivers. An addressing method for a receiver in a digital transmission system characterized by transmitting data.