JPS60246437A - Dividing circuit - Google Patents

Abstract

PURPOSE:To execute dividing operation processing without a code by detecting an overflow generated by addition or subtraction of a partial surplus and a divisor, by a carry flag, an arithmetic flag, and MSB of a result of operation. CONSTITUTION:An operating circuit 3 subtracts a value of a divisor register 2 from a value of a dividened register 1, sets a carry flag 5 to ''1'' if an overflow is generated, and sets it to ''0'' if it is not generated. The carry flag 5 is inputted to a quotient register 7, and the quotient register 7 is shifted to the left by 1 bit. an output of the operating circuit 3 is shifted to the left by 1 bit through a shifter 6 and inputted to the dividened register 1. An operation controlling circuit 8 sets an operating flag 4 to ''0'' if both the operating flag 4 and MSB of output data of the operating circuit 3 are ''0'', sets said flag to ''1'' if both of them are ''1'', sets the carry flag 5 in other cases. Addition and subtraction of a dividened and a divisor, and the shift repeat the operation by a word length + once of the divisor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a division circuit that performs division, which is one of the basic operations of a digital computer.

Conventional configuration and its problems The processing speed of digital computers has improved, and dedicated division/multiply ports are provided to improve the processing speed of basic operations.

A conventional division circuit will be explained below.

FIG. 1 shows a block diagram of a conventional division circuit.

1 is the dividend register that inputs the dividend at the beginning of the division operation, holds the partial remainder during the division operation, and holds the remainder of the division result at the end of the division operation. 2 is the register that inputs the divisor and holds the partial remainder during the division operation. , a divisor register that holds the value, 3 is an arithmetic circuit that adds or subtracts the value of dividend register 1 and the value of divisor register 2, 4 is an arithmetic flag indicating the operation of arithmetic circuit 3, and 6 is the arithmetic result of arithmetic circuit 3. 6 is a shifter that shifts the output of arithmetic circuit 3 to the left by 1 bit when inputting it to dividend register 1, R is a quotient register that holds the quotient of the result of the operation, and 8 is a carry flag from 5. , an arithmetic control circuit that generates the next arithmetic flag,
Reference numeral 9 denotes a timing control circuit that controls the division operation process.

The operation of the conventional division circuit configured as described above will be described below.

In non-recovery division, either +1 or -1 is selected as the quotient depending on the situation. In the quotient selection process, errors caused by each selection are corrected in subsequent steps, and extra delays due to additions, subtractions, and shifts caused by the corrections are removed.

The selection range of the quotient is given by the following formula.

(ko+1) IRl<IDI・・・・・・・・・・・・・・・・・・
...(1) The absolute value is each partial remainder R"1)(j
``J, 1,..., n-1) can be a positive or negative number.If we assume that the divisor can only take positive numbers, then equation (1) is as follows. It can be rewritten as

+ R(j+1)l<D・・・・・・・・・・・・
(2) From equation (2), as long as the absolute value of the remainder is smaller than the divisor, there is no need to restore a negative remainder to positive. Therefore, in each iteration, the divisor is added or subtracted from the partial remainder. The operations performed in each step are shown by the following equations.

The quotient corresponding to the above formula is determined as follows.

The operation of the circuit will be explained below according to the above algorithm.

The dividend and divisor necessary for the division operation are input into dividend register 1 and divisor register 2, respectively.

The input dividend and divisor take values that satisfy equation (2). Arithmetic shifter OP indicating addition or subtraction of arithmetic circuit 3
f4 corresponds to equation (3) and becomes K as follows.

Operation flag 4 is set to 1 at the beginning of the division operation.

According to the calculation flag 4, the calculation circuit 3 subtracts the value of the divisor register 2 from the value of the dividend register 1.

If a geooverflow occurs as a result of addition/subtraction in the arithmetic circuit 3, the carry flag 5 is set to 1, and if no overflow occurs, the carry flag 5 is set to the OK stage. This carry flag 6 is input to the right input of the quotient register 7, and the quotient register 7 is shifted to the left by 1 bit. The carry flag 6 is input to the calculation flag 4 through the calculation control circuit 8. The output of the arithmetic circuit 3 is sent to the left through the shifter 6.
Bit shifted and input to dividend register 1.

Addition, subtraction, and shifts between the dividend and divisor are performed using the word length of the divisor +
Repeat the operation once.

As a result of the division process, the quotient is set in quotient register 7K and the remainder is set in dividend register 1.

The flow of the above operation will be explained using the flowchart shown in FIG.

((a) Set the dividend and divisor in dividend register 1.
is input to divisor register 2. (b) Set calculation flag 4 to 1
Set to . (c) If the calculation flag 4 is φ, addition is performed, and if it is 1, subtraction is performed. ) Add the partial remainder and the divisor. (e) Subtract the divisor from the partial remainder.

(f) Set the carry flag based on the calculation result. (g) Shift quotient register 7 to the left [1 bit]. (Input the carrier lag to the force calculation flag. (S) If the calculation process has not finished, return to G/Now. 0) The quotient of the calculation is set in quotient register 7, and the remainder is set in dividend register 1. , the above flow ends.

However, in the above configuration, in order to satisfy the operation in equation (3) and eliminate errors due to overflow, it is necessary to always set the MSB of the divisor to φ, and unsigned division cannot be handled. Can not.

Purpose of the Invention The present invention solves the above-mentioned conventional problems and eliminates overflow caused by operations on partial remainders and divisors, and M
It is an object of the present invention to provide a division circuit that can handle unsigned division by setting the next operation flag using the SB and operation flag.

Structure of the Invention The present invention has the following features: an overflow caused by the operation of a partial remainder and a divisor, the MSB of the operation result, and the operation flag;
By setting the next operation flag, unsigned division processing can be performed.

DESCRIPTION OF THE EMBODIMENT FIG. 3 shows the configuration of a division circuit in an embodiment of the present invention.

In FIG. 3, 1 is a dividend register that inputs the dividend at the beginning of the division operation, holds the partial remainder during the division operation, and holds the remainder of the division result at the end of the division operation, 2 inputs the divisor, 3 is an arithmetic circuit that adds or subtracts the value of dividend register 1 (7) i and divisor register 2, 4 is an arithmetic flag indicating the operation of arithmetic circuit 3, and 5 is a divisor register that holds a value during a division operation. A carry flag that holds the carry output based on the calculation result of the calculation circuit 3, 6 is the calculation circuit 3
When the output of is input to the dividend register 1, the output is shifted by 1 bit to the left. , an arithmetic control circuit that generates the next arithmetic flag, and 9 a timing control circuit that controls the division arithmetic process.

The operation of the division circuit of this embodiment configured as described above will be explained below.

The dividend and divisor necessary for the division operation are input into dividend register 1 and divisor register 2, respectively.

The input dividend and divisor take values that satisfy equation (2). Arithmetic flag op indicating addition or subtraction of arithmetic circuit 3
f4 is expressed as equation (5).

Operation flag 4 is set to 1 at the beginning of the division operation.

According to the calculation flag 4, the calculation circuit 3 subtracts the value of the divisor register 2 from the value of the dividend register 1. If an overflow occurs as a result of addition and subtraction in the calculation circuit 3,
Carry flag 6 is set to 1, and if no overflow occurs, carry flag 6 is set to 0. This carry flag 6 is input to the right input of the quotient register, and the quotient register is shifted one bit to the left. The output of the arithmetic circuit 3 is shifted to the left by 1 bit through a shifter 6 and input to the dividend register 1.

The arithmetic control circuit 8 controls the arithmetic circuit 3 when the arithmetic flag 4 is 0.
If the MSB of the output data of the calculation circuit 3 is 0, the calculation flag 4 is set to 0, and if the calculation flag 4 is 1 and the MSB of the output data of the calculation circuit 3 is 1, the calculation flag 4 is set to 1.

In other cases, carrier lag 5 is set to calculation flag 4. Addition, subtraction, and shifting between the dividend and the divisor are repeated by the word length of the divisor + one time. As a result of the division process, the quotient is set in the quotient register 7 and the remainder is set in the dividend register 11C.

The flow of the above operation will be explained using the flowchart shown in FIG.

(・Input the dividend and divisor to dividend register 1 and divisor register 2, respectively. (C) Set calculation flag 4 to 1. (C) If calculation flag 4 is -, execute addition; if calculation flag 4 is 1, execute subtraction. .) Add the partial remainder and the divisor. (e) Subtract the divisor from the partial remainder.

(c) Set carry flag 5 based on the calculation result. (to)
Shift quotient register 7 to the left by 1 bit. ←→ Compare calculation flag 4 and the MSB of the output data, and if they are equal, do not change the value of the calculation flag. (S) Input carry flag 5 to calculation flag 4. 0) If the arithmetic processing has not been completed, return to (c). The quotient of the result of the Qarithmetic operation is stored in the quotient register 7K,
The remainder is set in dividend register 1, and the above flow is completed.

Effects of the Invention The division circuit of the present invention detects an overflow caused by addition or subtraction between a partial remainder and a divisor from a carry flag, an arithmetic flag, and the MSB of an arithmetic result, and manipulates the next arithmetic flag. can handle division operations, and its practical effects are great.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of a conventional division circuit;
3 is a block diagram showing the configuration of a division circuit according to an embodiment of the present invention, and FIG. 4 is a flowchart showing the operation of the division circuit of the present invention. . 1... Dividend register, 2 - Divisor register,
3. Arithmetic circuit, 4 Arithmetic flag, 5 Carry flag, 6 Shifter, 7 Quotient register, 8 Arithmetic control circuit, 9 Timing. control circuit.

Claims (1)

[Claims] a dividend register for inputting a dividend, holding a partial remainder during a division operation, and holding a remainder at the end of the operation; a divisor register for inputting a divisor and holding a value during said division operation; an arithmetic circuit that adds or subtracts the value of the dividend register and the value of the divisor register; an arithmetic flag that indicates the arithmetic operation of the arithmetic circuit; a carry flag that holds a carry output based on the arithmetic result of the arithmetic circuit; A thick circuit that shifts the output of the circuit by one bit to the left when inputting it to the dividend register, a quotient register that holds the quotient of the operation result, a timing control circuit that controls the operation process, and an addition or A division circuit comprising: an arithmetic control circuit that detects an overflow caused by subtraction according to the carry flag, the arithmetic flag, and the MSB of the arithmetic result, and operates the arithmetic flag.