JPS6024497B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer system, and in particular to a data transfer system for controlling an input/output device having a high data transfer rate and connected via an asynchronous interface that operates asynchronously with the clock of the control device. - Concerning data transfer methods.

As shown in FIG. 1, when data is transferred between the transfer control device 1 and the input/output device 2 that transmit and receive data, the following procedure is performed.

First, when the transfer control device 1 requests the input/output device 2 to read data, as shown in FIG. 1 to report the data transfer timing and send the transfer data onto the data bus 6. At this time, this is the time to compensate for the skew before and after the strobe-in signal Si and the skew on the frame interface. When transfer control device 1 detects this strobe signal Si, it receives the data on data bus 6 and sends a reception strobe signal SO onto strobe signal line 3. This completes the transmission of one unit of data, and thereafter data is transferred as many times as necessary in accordance with the same procedure. The opening in FIG. 2 shows a write operation, that is, a case where data is sent from the transfer control device 1 to the input/output device 2.

In the case of this write operation, the input/output device 2 sends a strobe-in signal Si to make a data transfer timing, that is, a data request, to the transfer control device 1, and the transfer control device 1 transmits the strobe-in signal Si. After the detection, the strobe out signal SO is sent to the input/output device 2 after compensating for the time skew, thereby reporting that data transfer has been performed. In this case, the strobe out signal SO is
Similarly to the response to the strobe signal Si, which is a data transfer request, it indicates that the data on the data bus 5 is valid. As a result, the input/output device 2 receives the data and performs the write operation. The transfer control device 1 turns off the strobe out signal SO after a predetermined time determined by the interface specifications, but the data 80 on the data bus 5 is made more valid for a limited time for skew compensation. In this way, one unit of data transfer is completed, and thereafter, data transfer is performed as many times as necessary in accordance with the same procedure.

Note that in FIG. 2A, the diagonally shaded portions of data Bi and BO are portions whose values are unstable due to bus switching at the time of transfer unit transfer. Generally, the strobe-in signal Si, which is an interface signal between the transfer control device 1 and the input/output device 2 for executing the data transfer described above, is asynchronous with the internal clock signal of the transfer control device 1. occurs in

On the other hand, internal operations in the transfer control device 1 for the transfer control device 1 to transmit and receive data with a host device such as a channel device (not shown) are performed in synchronization with an internal clock signal of the transfer control device 1.

Therefore, the transfer control device 1 needs to be equipped with special control means for handling the asynchronous interface signal.

Conventionally, the method of controlling such an asynchronous interface is to completely synchronize the asynchronous strobe signal (Si in the above case) on the interface with the clock signal inside the transfer control device, and then generate several types of transfer timing signals. A transfer timing circuit configured as follows was used.

However, this method requires a large number of clock synchronizations in order to stably synchronize asynchronous signals and obtain transfer timing signals. Therefore, when high-speed data transfer is required, the repetition period of the strobe signal that is input to the transfer timing circuit is limited, and therefore the timing circuit must be multiplexed, resulting in a circuit The drawbacks are that it becomes complicated and large. In addition, when data transfer speeds are increased, it is impossible to keep up with the increased transfer rate with a single configuration of interface registers for data transmission and reception, so multiple registers including buffer castles are required. There is a method of configuring the data to form a shift register, but this method has disadvantages such as a time difference between the input and output of the interface register due to data shifting and a complicated shift timing control circuit. Ta.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data transfer system that has a transfer timing generation circuit that has a simple configuration and can operate stably and at high speed by duplicating only the asynchronous strobe signal receiving circuit.

Another object of the present invention is to transfer data at high speed with simple control by using a pair of parallel-connected interface registers in combination with synchronous timing and asynchronous timing generated from the transfer timing generation circuit. The objective is to provide a data transfer method that enables To this end, in the data transfer method of the present invention, a data transfer control device having a transfer timing signal generating means that generates a transfer timing signal synchronized with the clock of the device itself based on a strobe signal and an interface register alternately switches between A first strobe signal receiving circuit and a second strobe signal receiving circuit are configured to be used in the first strobe signal receiving circuit, and a timing signal synchronized with the clock of the eye device is generated from the output of either one of the two strobe signal receiving circuits. a synchronization circuit that delays the strobe signal to generate a timing signal that is asynchronous to the clock of the device itself; and a first register connected in parallel that functions as an interface register for data transmission and reception. and a second register, and the switching of the input side and the switching of the output side between these two registers are controlled by the synchronized timing signal and the asynchronous timing signal. An embodiment of the present invention will be described below based on FIGS. 3 to 7.

3 is a block diagram showing one embodiment of the present invention, FIG. 4 is a detailed explanatory diagram of the transfer timing generation circuit in FIG. 3, and FIG. 5 is a timing chart showing the circuit operation of FIG. 6 is a detailed explanatory diagram of the interface/register circuit in FIG. 3, and FIG. 7 is an operation timing chart of the interface/register circuit in FIG. 6.

In the figure, the same reference numerals as in other figures indicate the same parts, 10 is an interface register circuit, 11 is a transfer timing generation circuit, 12 is a data buffer, 13 is a transfer control circuit,
14 is an interface control circuit; 15 and 16 are a data buffer 12 and an interface register circuit 10;
17 is a channel, 2 channels, 2 interface signal receiving circuits, 21 are interface signal transmitting circuits, 22a, 22b are delay circuits, 23 to 25 are NOT circuits, 26 to 28 are AND circuits, 29 and 30 are NAND circuits. circuit,
31 is an OR circuit, 32 to 39 are J-K flip-flop circuits, 40 is an interface signal receiving circuit, 41 is an interface signal transmitting circuit, 42 to 51 are AND circuits, 52 to 54 are NOT circuits, and 55 to 59 are OR circuits. It is a circuit. The interface register circuit 10 is a register in which received data transmitted from the input/output device 2 or transmitted data to be transmitted to the input/output device 2 is temporarily held, and includes a pair of registers 10a and 10a connected in parallel. lob, and an input switching circuit and an output switching circuit corresponding to these registers 10a and 10M, the details of which are shown in FIG. 6, which will be described later. Registers 0a and lob are registers equal to the data width of data bus 5 or 6. Transfer timing generation circuit 1
1 generates various transfer timing signals; upon receiving the strobe-in signal Si, it generates various synchronization signals necessary for sending data to the host device based on the strobe-in signal Si, or generates the strobe-out signal SO. Do the same actions as you would.

The data buffer 2 temporarily holds data when sending data from the transfer control device 1 to a higher-level device such as the channel 17, or when data is sent from the higher-level device to the interface control circuit 14. , a buffer that temporarily holds the data sent out via the interface control circuit 14.

The transfer control circuit 13 performs various controls when the transfer control device 1 receives data from a higher-level device or sends data to a higher-level device, and also controls between the transfer control device 1 and the input/output device 2. It performs overall control of the transfer control device 1, such as performing various controls regarding data transfer during the transfer.

The interface control circuit 14 performs various interface controls such as data transmission and reception between the transfer control device 1 and a host device.

The connection bus 15 is a bus used when transmitting data held in the data buffer 12 to the interface register 10 when transferring data sent from a host device to the input/output device 2.

The connection bus 16 is a bus used when transmitting data sent from the input/output device 2 and held in the interface register 101 to the data buffer 12. First, the operation of the transfer timing generation circuit 11 will be explained based on FIGS. 4 and 5.

The internal clock CLK of the transfer control device 1 is constantly applied to the JK flip-flop circuits 32-38.
Here, when the strobe-in signal Si is applied from the input/output device 2, the interface signal receiving circuit 20 receives it, and the interface signal transmitting circuit 21 sends the strobe-out signal SO to the input/output device 2 in response. do. At this time, the above-mentioned strobe signal Si is input as is to one input terminal of the AND circuit 26, and a signal corresponding to the strobe signal Si is input to the other input terminal via the delay circuit 22a and the /t circuit 23. Therefore, a signal SIPLS shown in FIG. 5E is outputted to the AND circuit 26 in synchronization with the strobe signal Si.

Separately, the strobe-in signal Si passes through a delay circuit 22b that constitutes an asynchronous timing signal generating means, and then passes through a JK flip-flop circuit 3 that constitutes an asynchronous timing signal.
9 is applied. Therefore, when the first strobe-in signal Si-1 is input, the signal B which is asynchronous with the clock CLK which is the output of the JK flip-flop 39 is input.
Since OEVN is "0" and the NOT circuit 24 is outputting "1", when the above signal SIPLS is output, the NAND circuit 29 outputs "0", and as a result, the JK flip-flop 32 is It is preset to produce the output "1" shown in FIG. 5A. This J-K flip-flop 32
The output "1" causes the J-K flip-flop 33 to output the "1" shown at the falling edge of the clock CLKI.
This is input to the OR circuit 31. On the other hand, when the second strobe signal Si-2 is input, the JK flip-flop 39 outputs the signal BOEVN "1" based on the output of the delay circuit 22b.

Therefore, the signal SIPLS generated by the second strobe-in signal Si-2 causes the NAND circuit 30 to output "0", and the J-K flip-flop 34 is preset to produce the output shown in FIG. 5C. ``1'', which causes J-K flip-flop 35 to clock CLK3.
At the falling edge of , it outputs "1" as shown in Fig. 5 D, and the OR circuit 3
Enter 1. Thus, the outputs of the JK flip-flops 33 and 35, which are the outputs of the first and second strobe receiving circuits, are applied alternately to the OR circuit 31, and the outputs of the JK flip-flops 33 and 35, which are the outputs of the first and second strobe receiving circuits, are applied alternately. The -K flip-flop 36 generates a synchronization signal SYNCO synchronized with the clock CLK, thereby generating the synchronization signal S from the J-K flip-flops 37 and 38, respectively.
YNCI and SYIEV are output.

That is, the strobe-in signals Si-1, Si-2...
・Based on Knot circuits 24, 25, NAND circuits 29
, AND circuit 27, J-K flip-flop 32,3
3, a NAND circuit 30, an AND circuit 28, and a JK flip-flop 3.
After the second strobe signal receiving circuit consisting of 4 and 35 is operated alternately to achieve quasi-synchronization, the OR circuit 31, J-K
Flip flop.

SYNC0, SYNC1, which are timing signals synchronized by a synchronization circuit consisting of switches 36, 37, and 38.
SYIEV can be obtained. Note that an asynchronous timing signal 80EVN is generated by a synchronization circuit composed of a delay circuit 22b and a JK flip-flop 39.
is used not only to switch the inputs of the first and second strobe signal receiving circuits, but also to control the switching of the first and second registers 10a and 10b in the interface register circuit 10', as described later. It is something that Next, the operation of the interface register circuit 10 in FIG. 3 will be explained with reference to FIGS. 6 and 7.

'11 Read Case ■ When the transfer control device 1 reads data from the input/output device 2, the data input from the data bus 6 is transmitted via the interface signal receiving circuit 40.

At this time, since the read signal READ is "1", the above data is inputted to the interface register 10a and lob via the AND circuit 48 and the OR circuit 57. At this time, the first strobe signal Si-
1, the asynchronous signal SIP melon is generated,
Moreover, since the signal BOEVN output from the J-K flip-flop 39 is in the initial state of 0, the NOT circuit 52 is
1" is being output. Therefore, data is set only in register 10a via AND circuit 44 and OR circuit 55 by asynchronous signal SIPLS corresponding to this first strobe signal Sj. ■ When the second strobe signal Si-2 is transmitted, this time the signal BOEVM output from the J-K flip-flop 39 is "1" as described above, so this time the AND circuit 4
4 is off, and the AND circuit 46 is turned on, and data is set only in register 1ob by the asynchronous signal SipLS.

In this way, when reading, registers 10a, 1
Data is alternately set to 0b based on asynchronous signals. ■ The data set in the register 10a by the above ■ is the AND circuit because when the synchronizing signal SYIEV is in the initial state of “0”, “0” is output from the OR circuit 59 and “1” is output from the NOT circuit 54. 50,
The signal is sent to the data buffer 12 via the OR circuit 58 and the connection bus 16, and will eventually be transmitted to the host device.

At this time, an access request signal to the data buffer 12 is generated by the synchronization signal SYNCO generated from the first strotopin signal Si-1. After checking the state of the data buffer 12, if it is accessible, the synchronization signal SYN is output in the next clock cycle.
Buffer access is performed by CI. ■ The first strobe signal causes the J-K flip-flops 32, 33, the OR circuit 31, the J-K flip-flops 36, 37, 38, etc. to generate the synchronization signal SY.
NC0, PYNC1, and SYIEV are generated.

When the synchronization signal SYIEV becomes "1", the AND circuit 51 is activated, and the data set in the register 10b is sent to the second strobe signal via the AND circuit 51, the OR circuit 58, and the connection bus 16. The signal is sent to the data buffer 12 in the same manner as described above using the timing signal generated by the timing signal. In this way, the register 10
a and 10b are selectively output. In this way, in the case of read, the input is the asynchronous signal BOEV
The output is controlled by the synchronization signal SYIEV. [2) In the case of a write■ In the case of a write that transfers data from the transfer control device 1 to the input/output device 2, the data buffer 12
The data first sent to the mustard registers 10a and 10b is the connection bus 15, the AND circuit 49, and the OR circuit 57.
It is set via etc.

At this time, when the write signal WRITE becomes "1" and the strobe-in signal Si is sent out, data sending is started.

In this case, since the initial state of the JK flip-flop 39 is "0", the asynchronous signal BOEVM is also "0",
AND circuit 43 is "0", therefore OR circuit 59 is "0".
0" is output. Therefore, the NOT circuit 54 outputs "1" and the AND circuit 50 is activated, so that the register 10
The data set in a (register 10 in Figure 7)
A) shown in a is sent to the data bus 5 via the AND circuit 50, the OR circuit 58, and the interface signal transmission circuit 41. Then, a strobe-out signal SO is sent out using the strobe-in signal Si. Therefore, data is being sent onto the data bus 5 when this strobe out signal SO is output. ■ After sending this strobe out signal SO, the J-K flip
The flop 39 operates and the asynchronous signal BOEVN becomes "
0".

As a result, the NOT circuit 54 outputs "0", the AND circuit 50 is turned off, and the AND circuit 51 is activated, so that the data set in the buffer 10b is transferred to the AND circuit 51, the OR circuit 58, and the interface. It will be sent to the data bus 5 via the signal transmission circuit 41. ■ On the other hand, the above first strobe signal S
When i is received, J-K flip is performed as described above.
Frotub 32, 33, OR circuit 31, J-K flip
Synchronous signals SYNC0, PYNC from flops 36 to 38
I and SY5V are output.

Then, the synchronization signal SYNCO is used to request access to the data buffer 12, and the synchronization signal S
YNCI accesses the buffer and outputs the proposed data (C in BFO at the beginning of FIG. 7) to the connection bus 15. At this time, the synchronizing signal SYIEV is "0", the NOT circuit 53 outputs "1", and the AND circuit 45 is activated. Thus, the clock CLK is applied to the register 10a via the AND circuit 45 and the OR circuit 55. Therefore, the data output to the connection bus 15 at this time is transferred to the AND circuit 49 (write signal WRI
TE) is set in the buffer 10a via the OR circuit 57. In this way, the synchronization signal SYNCI causes the data buffer 12 to
Write data is output sequentially from
Registers 10a and 1 according to "0" and "1" of field V
It will be selectively input to 0b. In this way, in the case of writing, although the output is controlled by the asynchronous signal BOEVM, the input control is performed by control synchronized with the clock CLK.

As explained above, according to the present invention, only the asynchronous strobe signal receiving circuit needs to be duplicated, so the strobe signal receiving circuit can be operated using the asynchronous timing signal without completely duplicating the entire timing circuit. By switching the inputs, a synchronization circuit with a simple configuration and high speed can be obtained.

Furthermore, since a plurality of registers can be provided in parallel in the interface register circuit and used by switching between them, even if the data transfer rate is increased, it can be handled without complicating the hardware.

[Brief explanation of drawings]

Fig. 1 shows an example of the interface configuration between a transfer control device and an input/output device, Fig. 2 shows an example of the interface operation, where A shows a read operation, and Fig. 3 shows a write operation. - A block diagram showing the embodiment, FIG. 4 is a detailed explanatory diagram of the transfer timing generation circuit in FIG. 3, FIG. 5 is a timing chart showing the circuit operation of FIG. 4, and FIG. A detailed explanatory diagram of the register circuit, FIG. 7 is an operational timing chart of the interface register circuit of FIG. In the figure, 10 is an interface register circuit;
11 is a transfer timing generation circuit, 12 is a data buffer, 13 is a transfer control circuit, 14 is an interface control circuit, 15 and 16 are connection buses between the data buffer 12 and the interface register circuit 10, and 17 is a channel. , 20 is an interface signal receiving circuit, 21 is an interface signal transmitting circuit, 22a and 22b are delay circuits, 23 to 25 are NOT circuits, 26 to 28 are AND circuits,
29, 30 are NAND circuits, 31 are OR circuits, 32, 39
4 is a J-K flip-flop circuit, 40 is an interface signal receiving circuit, 41 is an interface signal transmitting circuit, 42 to 51 are AND circuits, 52 to 54 are NOT circuits, and 55 to 59 are OR circuits, respectively. Figure 1 Figure 2 Figure 3 Dimensions Vertical diagram Mountain whale diagram ○ Rudder diagram Next to ship diagram

Claims (1)

[Claims] 1. In a data transfer control device having a transfer timing signal generating means for generating a transfer timing signal synchronized with the clock of the device itself based on a strobe signal and an interface register, a data transfer control device configured to be used alternately. 1 strobe signal receiving circuit and the 2nd strobe signal receiving circuit.
a strobe signal receiving circuit; a synchronization circuit that generates a timing signal synchronized with the own device's clock from the output of either of the two strobe signal receiving circuits; and a synchronization circuit that delays the strobe signal to generate a timing signal synchronized with the own device's clock. , an asynchronous timing signal generation means for generating an asynchronous timing signal, a first register and a second register connected in parallel that act as interface registers for data transmission and reception, and input side switching between these registers. A data transfer method characterized in that switching on the output side is controlled by the synchronized timing signal and the asynchronous timing signal.