JPS60226092A - Sense amplifier - Google Patents

Abstract

PURPOSE:To realize a CMOSRAM which has increased a read-out operating speed by connecting in common the gate of an MOS transistor of the current source of a single end type differential amplifier and the gate of an MOS transistor connected to the output terminal of its differential amplifier. CONSTITUTION:In case a control terminal RE and bit lines BL, -BL are ''H'', each corresponding terminal potential of MOSTs (Q4, Q1), (Q5, Q2) becomes equal, and a current flowing through an nMOSTQ1 becomes equal to a current flowing through an nMOSTQ2. At present, when the bit line -BL starts to drop to ''L'' from this state, the current flowing through the nMOSTQ1 decreases, but the current flowing through the nMOSTQ2 increases by a decreased portion of the current flowing through the nMOSTQ1, by a constant-current source constituted of an nMOSTQ3. As the current flowing through the nMOSTQ2 increases, the potential of a nodal point N2 drops due to a voltage drop by a pMOSTQ5. When the potential of the nodal point N2 drops, a resistance of a pMOSTQ4 decreases, and also, the current flowing through the nMOSTQ1 decreases, therefore, a voltage drop by the pMOSTQ4 becomes small, and the potential of an output terminal OUT rises.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) 5. The present invention relates to a sense amplifier for a synchronous CMO8RAM (complementary field effect transistor random access memory).

(Prior Art) FIG. 1 is a circuit diagram showing a main part of a conventional example of a static type CMO8RAM. Although only one column is shown in FIG. 1, memory cells (CI-Cn) are usually arranged in a plurality of columns. The memory cell is a p-channel MO8) transistor (hereinafter referred to as -pMO8'l') with a CMOB structure like CI.
Q7 and n-channel M08 transistor (hereinafter referred to as nMO8)
An inverter consisting of T and pMO8TQ11. A pair of inverters consisting of nM08TQ, , cross-over from the gate part of one to the drain part of the other is configured by multiple connections, and the two gate-drain connection nodes are nMO8TQ1t + Ql and the bit lines BL, respectively. Connected to BL. 4nMO8T
χQtt.

The gate of Qll is connected to word line WL14C and W
L, the extraction of information from the memory cell CI is controlled.

One of the bit lines BL and BL is pMO8T Qts
.

Q14 is connected to the stain source terminal VDD, and the other side is connected to a data write circuit and a sense amplifier for reading.

At 14 AM in FIG. 1, data reading is performed as follows. When the address is undefined, the precharge pulse PC is 'L'' and pMO8TQra *
Q14 is not conductive and bit line BL.

BL is precharged to "H". When the address is established and the word line WL is selected, the precharge pulse PC becomes H", pMos'rQ1s + Q1
4 is in a non-conductive state. At the same time, word dry yWL,
When nMO8T Qt1@Qtx becomes "H", one of the bit lines BL, BL starts to change to "L" according to the contents of the memory cell C1. A potential change is detected by a sense amplifier connected to the other of BL and BL, and data is output.

In this case, the conventional NAND gate G shown in FIG.
, G, are cross-connected in a latch type sense amplifier,
The potential of the bit lines BL, BL is the same as that of the NAND gate G,
, G, is exceeded before data is detected. When using the sense amplifier shown in Figure 2,
To operate RAM at cylinder speed, bit lines BL, B
It is necessary to speed up the potential change of L.

Here, in FIG. 1, the bit lines BL and BL are '
The speed of change from H'' to L'' is the memory cell Ct 17
'lnonMO8T(Qs * Qll L (Qto
It is determined by the conductance gm of the pair +Ql 2→. Therefore, nMO8T Qs = Qso - Qtl
,Q! By increasing the dimension x and the conductance gm, high-speed operation of can be achieved. However, because of the internal nature of the memory cell, the above-mentioned improvement measures are not desirable when increasing the degree of gastric integration.

This resulted in the drawback that it became difficult to increase the degree of integration of the RAM.

(Object of the Invention) An object of the present invention is to provide a sense amplifier which eliminates the above-mentioned drawbacks and enables the implementation of CMO8RAM=i, which increases the read operation speed while maintaining a high degree of integration.

(Structure of the Invention) The inventive sense amplifier includes a pair of throats configured to detect information signals contained in selected ones of the memory cells.
A sense amplifier is connected to a play of a memory cell by a trine, and includes a first MOS transistor of one conductivity type having one of the bit lines as a gate input, and a first MOS transistor of one conductivity type having the other bit line as a gate input. Type 2
MOS transistor, and the first MOS transistor. a third MOS transistor of one conductivity type connected between a common connection node between one terminal of each of the second MOS transistors and the first power supply terminal; A fourth MO of opposite conductivity type connected between the power supply terminals of
a fifth A40S transistor of an opposite conductivity type connected between the other terminal of the second MOS) transistor and the power supply terminal of g2; the first MOS transistor and the fourth Mo8) transistor; and a sixth MOS transistor of opposite conductivity type connected between the common connection node of and the second power supply terminal;
8) The gate inputs of the transistors are commonly connected to the common connection node of the second Mo8) transistor and the fifth Mo8) transistor, and the gate inputs of the third Mo8) transistor and the sixth Mo8) transistor are connected in common. The gate input is commonly connected to the control terminal for controlling the conductivity of the sense amplifier, and the other terminal of the first Mo8) transistor is connected to the output terminal.

That is, the sense amplifier of the present invention has a bit line BL
, BL, and a load connected between the same power terminal and output terminal as the Mo8) transistor for the load of the differential amplifier. The gate of the Mo8) transistor, which is the primary source of the differential amplifier, and the gate of the MOS transistor connected to the output terminal of the differential amplifier are in common. Consists of connected circuits.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, a pair of bit lines BL are configured to sense information signals contained in selected ones of the memory cells.
, a sense amplifier connected to the array of memory cells by BL, nMo8TQa whose gate input is the bit line BL, and nMo8TQI whose gate input is the bit line BL.
and nMo8'l' connected between the common connection node N1 between each source of nMo8TQx and Qa and the ground terminal GND.
Q3, pMO8TQ connected between the drain of nMo8TQ1 and power supply terminal VDD, and nMo8TQ2ty)
1ci connected between drain and 11 source terminal vDD fcpMO
8TQ5. ! :, pMO8T connected between the common connection node of nMo8TQt and nMo8TQ4 and power supply terminal vDD
1) Mo8TQ4-Qs gate input f n MOS T Q ! and pMO8TQ, the common connection node N! The gate input of nMo8TQ3 and the gate input of pMO8TQ6 are commonly connected to the control terminal REVc for controlling the conductivity of the sense amplifier, and the drain of nMo8TQt is connected to the output terminal 0UT4C.

In addition, n MOS T Q 1 and 910 dimensions and nM
It is assumed that o8TQ4 and Qll have the same dimensions, and the six pairs of transistors have the same conductance gm gold.

Next, the operation of this embodiment will be explained.

Here, control terminals R, E and bit line BL.

When BL is 'H', Mo8T(Qa, Q
l).

The corresponding terminal potentials of (Qs, Ql) are equal to ρ, the current flowing through nMo8TQ1 and nMo8
The currents flowing through TQ* will be equal. Now, when the bit line BL starts to fall to "L" from this state, nMo8
Although the current flowing through TQ1 decreases, nMo8TQs
The current flowing through nMO,5TQt due to the current source configured as shown in FIG. As the current flowing through nMo8TQz t" increases, the potential at node N2 decreases due to the voltage drop due to pMO8TQ=. When the potential at node N2 decreases, the resistance of pM-O8TQ4 decreases, and nA40S
Since the current flowing through TQt also decreases, nMo8TQ4
If the voltage drop caused by the drop is small, the potential of the output terminal (JUT) increases. Conversely, when the bit line BL goes low, the current flowing through nMo8TQ*k decreases, and the current flowing through nMo8TQ1 decreases. Power booster, node N
The potential of the output terminal OUT increases and the potential of the output terminal OUT decreases.

As explained above, in this embodiment, the bit lines BL,
When one potential of BL falls from "H" to "L", the potential of the output terminal 0tJT rises or falls, and the contents of the memory cell can be detected.

Additionally, this operation begins when the potential of one of the bit lines BL and B is lower than 9 and there is a potential difference between the bit lines BL and BL, so if the bit line is below the threshold of the circuit. This eliminates the drawback of conventional sense amplifiers that a detection operation is not performed unless the potential drops.

In addition, at times other than reading, the control terminal RE is set to 'L' to put the nMO8TQs into a non-conducting state, and the sense amplifier can be placed in a dormant state, thereby reducing power consumption.However, when the output terminal OUT is in an insufficient state, In this case, the power consumption of the circuit that uses the sense amplifier's output manually increases, so the output terminal OUT is
It is hoisted to Hn.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, the conductivity type of the MOS transistor shown in FIG.
, and the polarity of the power terminal and signal terminal are reversed, and corresponding parts are given the same symbol, and the same symbol is used.
It is shown with .

The operating principle of this embodiment is the same as that in FIG. 3, and similar effects can be obtained.

(Effects of the Invention) As described above in detail, the sense amplifier of the present invention has the following features:
The above configuration has the effect of increasing the read speed while suppressing power consumption when the 0MO8RAM is at rest.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the main part of an example of a conventional 0MO8RAM, FIG. 2 is a circuit diagram showing an example of a conventional sense amplifier, and FIG. 3 is a circuit diagram showing a first embodiment of the present invention. FIG. 4 is a circuit diagram of a second embodiment of the present invention. BL, BL, --- Bit line, Ct t C2g
Un...Memory cell, G,,G!・・・・・・
NAND gate, GNLI...Ground terminal, N1
e Nl' I N, I N2'...Node,
OUT...Output terminal, PC...Precharge pulse, Qt t Q2 * Qs j Q4
' + Qs j Qs ' *Qs~Q14...
・・n channel MO8) transistor, Qt' tQ
t '# Qs ' e Q4 w Qll # Q
s I Qt e Qs...p channel M(J
S) Transistor, BE... Control terminal, vDD'
...Power terminal, WL,, WL,, WLn...
word line. 2nd Flash oUT No. 3 oUT No. 4

Claims (1)

[Scope of Claims] A sense amplifier connected to seven arrays of memory cells by a pair of and trines so as to sense information signals contained in selected ones of the memory cells, the sense amplifier comprising: a first MOS transistor of one conductivity type having a bit line as a gate input; a second MOS transistor of one conductivity type having a gold gate input of the other bit line; a third MOS transistor of one conductivity type connected between the common connection node between one terminal of each of the second MO8 transistors and the first power supply terminal; and the other terminal of the first MOS transistor. and a fourth MOS transistor of a reverse conductivity type connected between the second power supply terminal and the second power supply terminal;
a fifth MOS transistor of an inverted quaternary voltage type connected between the other terminal of the second MOS) transistor and a second power supply terminal; the first MOS) transistor; and the fourth MOS) transistor. and a sixth MOS transistor of the opposite conductivity type connected between the common connection node of the transistor and the second power supply terminal, and the gate input of the fourth and fifth MOS transistor The gate input of the third MOS) transistor and the sixth MOS) transistor are commonly connected to the common connection node of the MOS) transistor and the fifth MOS) transistor.
(OS) is commonly connected to the gate input of the transistor and connected to a control terminal that controls the conductivity of the sense amplifier, and the first
A sense amplifier characterized in that the other terminal of a MOS) transistor is connected to an output terminal.