JPS60221816A - One chip microcontroller - Google Patents

Abstract

PURPOSE:To simplify the constitution of a titled controller by making an interruption processing circuit of the inside unnecessary without providing an input terminal of a control signal in case when a power supply voltage has been varied, by preventing the generation of malfunction of an internal operation when the power supply voltage has been varied, by the inside of a controller. CONSTITUTION:An internal circuit part consisting of a program counter 16 connected to a control bus 29, an address bus 30 and a data bus 31, a program memory 17, a ROM18, a calculating part 20, a RAM23, etc., and a two-phase clock generating circuit 15 for supplying a driving clock signal to said circuit part are provided on a semiconductor substrate. A voltage of a Vdd power source 11 from power source terminals P1, P2 of this controller is applied to the first power supply voltage detecting circuit 12 and the second power supply voltage detecting circuit 13. A state that the power supply voltage is below a voltage for operating stably the internal circuit part is detected by this circuit 12, and the generation of a clock from the circuit 15 is stopped. Also, a voltage by which the internal circuit part can hold its operating state is detected by the circuit 13, a reset signal is generated, and the generation of malfunction is prevented by the inside of the controller.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a one-chip microcontroller O-controller in which, for example, a microcomputer, a microprocessor, etc. are constructed from a one-chip semiconductor integrated circuit. This invention relates to an improved device that can internally prevent malfunctions of internal circuit elements.

[Background art of the invention and its problems] Conventionally, microcomputers, microprocessors, etc. have been constructed using one C-MO8 semiconductor integrated circuit.
A chip microcontroller has a clock generation circuit, program memory (ROM), data memory (RAM), arithmetic unit (ALU), and input/output control unit (
It is constructed by incorporating circuit elements such as Ilo), and is driven by an externally supplied power source.

By the way, in the conventional one-chip microcontroller as described above, when the power supply voltage drops, the interrupt processing signal and reset signal generated from the external power supply voltage detection circuit are used to avoid data caused by interrupt processing and prevent malfunction of the circuit. At the same time, the internal circuit element section is reset and the internal state is initialized. However, such a one-chip microcontroller inevitably requires a power supply voltage detection circuit to control the external microcontroller, and control signals such as interrupt processing signals and reset signals output from this power supply voltage detection circuit. Not only is an input terminal for inputting the information required, but also a complicated interrupt processing circuit is required internally, making the configuration of the internal circuit element section complicated.

[Purpose of the Invention] This invention has been made to improve the above-mentioned problems, and it is possible to eliminate internal circuits caused by fluctuations in the power supply voltage without providing a terminal for inputting control signals when the power supply voltage fluctuates. It is an object of the present invention to provide a one-chip microcontroller that can prevent malfunction of elements and does not require a complicated internal interrupt processing circuit.

[Summary of the Invention] That is, the one-chip microcontroller according to the present invention forms an internal circuit element portion on a semiconductor substrate, supplies a driving clock signal from a clock generation circuit to the internal circuit element portion, and operates the semiconductor device. A power supply terminal provided for the board is connected to an external snow tray, and the power supply voltage from the power supply terminal is supplied to a first power supply voltage detection circuit. A state in which the voltage is lower than the first lower limit reference voltage ■s that guarantees stable operation of the circuit element section is detected, a clock generation stop signal is generated for the clock generation circuit, and the power supply voltage from the power supply terminal is changed to the second lower limit reference voltage. of! A second lower limit reference voltage V' is supplied to the applied voltage detection circuit, and this second power supply voltage detection circuit allows the power supply voltage to be slightly higher than the minimum voltage VT for maintaining the operating state of the internal circuit element section and to ensure that the operating state is maintained. A reset signal is generated by detecting the following conditions, and the internal circuit element section is set to an initial state in response to the generation of this reset signal.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows its configuration, and this one-chip microcontroller has power terminals P1. P2, a clock control terminal p3. to which an external resistor R1 for clock frequency adjustment is connected. Equipped with p4,
Furthermore, terminal P5 for inputting the test signal 3t, terminals PAO to PA3 for data input, terminals PBO to PB3 for data input/output, and terminals PCO to PC for data output.
It has 2.

Further, this one-chip microcontroller is equipped with power supply voltage monitoring means consisting of a first power supply voltage detection circuit 12 and a second power supply voltage detection circuit 13, and also includes a built-in capacitor C1 to which the external resistor R1 is connected, and a hysteresis It has a clock generation circuit 14 consisting of an inverter 1nvl and an AND gate G1, and a two-phase lock generation circuit 15 based on the clock signal from this clock generation circuit 14.
The driving two-phase clock signals φa and φb are generated in the following manner.

And, this one-chip microcontroller is
Clock signals φa and φb from phase lock generation circuit 15
This internal circuit includes, for example, a program counter 16, a program memory (
ROM) 17, instruction decoder (IR) 18, address buffer 19, test mode control circuit 20, arithmetic unit (
ALLI) 21, result register (RR) 22, data memory (RAM) 23, address decoder 24, special counter 25, input port (PA) 26, input/output port (Pa) 27, and output port (PC) 28. , drive control signals for each block are transferred via a control bus 29, address signals are transferred via an address bus 30, and data signals are transferred via a data bus 31. Such an internal circuit is composed of a static circuit and integrated into one chip.

Here, the first power supply voltage detection circuit 12
The lowest potential VS at which the output voltage Vdd of ii can guarantee stable operation of the internal circuit (hereinafter referred to as the first lower limit reference voltage)
It detects whether or not the voltage has dropped below 1, and generates a clock generation stop signal a which becomes the #O# logic level when vdd≦■S. This clock generation stop signal a is supplied to the AND gate G1 of the clock generation circuit 13.

Further, the second power supply voltage detection circuit 13 detects the power supply voltage V
dd is the lowest potential V that can guarantee the maintenance of the internal circuit's operating state.
It detects whether the voltage has fallen below r (hereinafter referred to as the second lower limit reference voltage).
'Generate a reset signal that becomes a logic level. This reset signal is supplied to necessary blocks of the internal circuit via the control bus 2θ.

Then, the clock generation circuit 14 calculates the hysteresis width of the inverter lnvl with hysteresis, the external resistor R1
It generates a clock by OR oscillation, the frequency of which is determined by the resistance value of C1 and the capacitance value of built-in capacitor C1, and the oscillation is stopped when the clock generation stop signal a is supplied to AND gate G1. There is. The inverter lIIIVI is provided with hysteresis between the clock stop voltage and the clock start voltage.

The output clock of this clock generation circuit 14 is supplied to a two-phase lock generation circuit 15. This two-phase lock generation circuit 15 generates two non-overlapping internal clocks φa and φb from the output clock of the oscillation circuit 14. These two internal clocks φa and φb are
It is for driving each block of the internal circuit of the static circuit configuration, and is supplied to each block although not shown.

The program counter 16 counts up based on the internal clock φa, and its output is supplied to the program memory 17 as an address signal. This program memory 17 specifies the instruction content according to the address signal, and its output consists of 12 bits, and the upper 4 bits are sent to the instruction decoder 18 as the instruction content.
The lower 8 bits are supplied to the address bus 30 via the address buffer 19 as the address of the operand. In addition, the arithmetic unit 21
Together with the Galt register 22, it constitutes a so-called accumulator. Further, the count output of a special counter 25 is supplied to the data memory 23 via a special bus 32.

FIG. 2 shows a specific configuration of the inverter I nvl with hysteresis of the first power supply voltage detection circuit 12, the second power supply voltage detection circuit 13, and the clock generation circuit 14. That is, the first power supply voltage detection circuit 12
Threshold voltage VTP (H) is approximately 2.0 [V]
P-MOS gate Q1 whose threshold voltage is higher than that used in other gates, diffused resistors R2 to R4, and inverter Inv2 whose logic threshold voltage is relatively high.
, an inverter with a relatively low threshold voltage 1nv
3. Normal inverter 1nv4, Nant Gate G2,
It is composed of an RS flip 70 tube FF1 consisting of G3 and a flip-flop FF2 with a D-type set-reset, and the value of the first lower limit reference voltage VS is determined by the P-MOS
Threshold voltage Vrp due to gate Q1 and resistance R
2, R3, and this first reference voltage V
The hysteresis width of S is determined by inverters 1nv2°Inv3 with different logic thresholds.

The first power supply voltage detection circuit 12 is driven by a D-type flip 70-tube FF2 in synchronization with the clock from the clock generation circuit 14, and as a result, the minimum width of the clock is inappropriately short. It is guaranteed that this will not happen.

The second power supply voltage detection circuit 13 is composed of a P-MOS gate Q2 whose threshold voltage VTP (H) is higher than the threshold voltages used in other gates, a bias resistor R5, and an inverter lnv5. The second lower limit reference voltage Vr is set equal to the threshold voltage Vdp()l).

The above inverter with hysteresis I nVl is
It is composed of a capacitor C2, a differential voltage comparator Op1, inverters InV6 to InV8, and resistors R6 to R8, and its hysteresis width is determined by the ratio of the resistors R6 to R8.

The operation of the above configuration will be described below.

This microcontroller sets the lower limit stable operating voltage to V
If it is set to win, normal operation cannot be guaranteed when the power supply voltage V ddtfiV sin voltage or less, so the first lower limit reference voltage level at which the clock is stopped is set to VS, and the second lower limit at which the reset signal is generated is set to VS. When the reference voltage level is Vr, VS >■lin >yr
By setting , it is possible to prevent malfunctions that occur when the power supply voltage Vdd rises or when the voltage drops due to voltage fluctuations.

That is, when the power supply voltage Vdd rises, O
[V] <Vdd≦Vr (7) The second power supply voltage detection circuit 13 operates and supplies a reset signal to other necessary blocks via the program counter 16 and control bus 29, and the program Initialize the counter 16 and each block. At this time, since Vdd<VS, the first power supply voltage detection circuit 12 detects this and generates and outputs the clock generation stop signal a, and this clock generation stop signal a causes the output of the AND gate G1 to be " 0″
The clock generation circuit 14 stops clock generation by fixing the logic level to the logic level. Further, when Vr<Vdd≦VS, the reset by the second power supply voltage detection circuit 13 is released, but the first power supply voltage detection circuit 12 operates to generate and output the clock generation stop signal a. Therefore, the clock generation of the clock generation circuit 14 remains stopped.
This microcontroller maintains a state in which it starts operating. In its current state, it is held in a reset state.

Then, when vdd>Vs, the first power supply voltage detection circuit 12 detects this and stops outputting the clock generation stop signal a, so that the clock generation circuit 14 starts operating. This makes the microcontroller fully operational.

Next, when the power supply voltage Vdd drops, the power supply voltage Vd
When d drops to Vdd≦ys, the first power supply voltage detection circuit 12 detects this and generates and outputs a clock generation stop signal a, stopping the operation of the clock generation circuit 14 and stopping clock generation. Therefore, this microcontroller continues to operate. At this time, the microcontroller configures each block with a static circuit in order to reliably hold each block. After that, when Vdd>Vs, the operation starts again from that state. Then, the power supply voltage Vdd is Vdd
When the voltage drops to ≦Vr, the second power supply voltage detection circuit 13 detects this and generates and outputs a reset signal, thereby initializing the microcontroller.

Here, as shown in FIG. 2, the first power supply voltage detection circuit 12 is driven by a D-type flip-flop FF2 in synchronization with the clock from the clock generation circuit 14, so that this microcontroller can reach Vdd. If the clock suddenly becomes ■dd≦Vs while operating normally at >Vs, instead of stopping the clock unconditionally, the clock is stopped when the current instruction execution is finished and the next clock cycle is started. It is designed to stop the This results in
The minimum clock time width required for instruction execution is always secured.

Further, in the clock generation circuit 14, a hysteresis of about 20 [mV] is provided between the clock stop voltage and the clock start voltage by the inverter I nvl with hysteresis.
This prevents unexpected malfunctions even if the voltage temporarily decreases for some reason and remains close to Vs. The lower limit of guaranteed operation regarding the power supply voltage Vdd is generally the Vakin level, but the above microcontroller automatically stops the clock and maintains the state, so the appearance is set as low as the level of a jonin. It is possible to guarantee operation up to the second lower limit reference voltage Vr level.

The above embodiment will be briefly described using specific numerical values.

First, the above 1-chip microcontroller is connected to C-MO3
As a semiconductor integrated circuit, the threshold voltages of P-MOS and N-MOS are set to VTP-1[V] and VTP-1[V], respectively.
Set T to -1 [■].

In addition, the threshold voltages of P-MOS gates Q1 and Q2 in FIG.
Assume that the resistance ratio of resistors R2 and R3 is 4:3.

The first lower limit reference voltage VS at this time is approximately 3.5 [■],
The second lower limit reference voltage ■r is approximately 2.0 [V]. In addition, the minimum operating state holding voltage VT at which the reset actually works is:
Since it is approximately equal to the maximum value of the threshold voltages VTP and VTN, it is approximately 1[,V]. Further, when operating by forcibly applying a clock to the R3 terminal from the outside, the lower limit stable operating voltage V 1n is 3.0 [V], and the upper limit stable operating voltage is 6.0 [V]. Fig. 3 shows its operable range.

That is, the microcontroller in this case works perfectly in the case of external clock 3, 0 to 6.0 [V]
In addition to 2.0 to 3.5 [V] in the case of self-oscillation
During this period, the clock automatically stops and maintains the operating state at that time, so the range that can guarantee operation against unexpected drops in the power supply voltage Vdd is 2.0 to 6.0 [V]. The low voltage side can be significantly improved. In addition, when the power supply voltage dd drops to 2.0 [V], it is completely initialized, so the actual operating range is 1.0 to 6.0 [V].
[V].

In this way, this microcontroller has a power supply voltage V
Even if the voltage dd suddenly fluctuates during the rise of dd or the operating state, it can operate stably without running out of control. This is ■min<
This is due to the fact that the operation guaranteed range and the clock stop range overlap as ys, the clock stop range and the reset range overlap, and blank areas where operation maintenance cannot be guaranteed are eliminated.

Therefore, the one-chip microcontroller configured as described above does not have a terminal for inputting a control signal when the power supply voltage fluctuates, as in the past, but internally prevents malfunctions of the internal circuit due to fluctuations in the power supply voltage. Furthermore, the lower limit voltage level that guarantees operation can be set significantly lower without the need to provide a complicated internal interrupt processing circuit. This makes it extremely effective when the power supply voltage becomes unstable, especially due to radio interference from external forces (external forces) or high-frequency/high-voltage noise such as ignition noise coming to automobile electrical components. .

[Effects of the Invention] As detailed above, according to the present invention, malfunction of internal circuit elements due to fluctuations in the power supply voltage is prevented internally without providing a terminal for inputting a control signal when the power supply voltage fluctuates. Furthermore, it is possible to provide a one-chip microcontroller that does not require a complex internal interrupt processing circuit.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing an embodiment of a one-chip microcontroller according to the present invention, FIG. 2 is a circuit diagram showing a specific configuration of the above embodiment, and FIG. 3 is a block circuit diagram showing a specific configuration of the above embodiment. FIG. 3 is a diagram for explaining a range of motion. DESCRIPTION OF SYMBOLS 11...Vdd power supply, 12...1st power supply voltage detection circuit, 13...2nd power supply voltage detection circuit, 14...
Clock generation circuit, 15...2-phase lock generation circuit,
29... Control bus, 30... Address bus, 31.
...Data bus, Pl, R2...Power terminal, R3
, R4... Clock control terminal, ys... First lower limit reference voltage, ■r... Second lower limit reference voltage, V n+
in...lower limit stable operating voltage, VT...minimum guaranteed operation voltage, a...clock generation stop signal, b...reset signal. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] an internal circuit element section on a semiconductor substrate; a clock generation circuit that supplies a driving clock signal to the internal circuit element section; a power supply terminal provided on the semiconductor substrate and connected to an external power source; This I! A clock generation stop signal is sent to the clock generation circuit by detecting a state in which the power supply voltage from the power supply terminals is supplied and the power supply voltage is equal to or lower than the first lower limit reference voltage VS that guarantees stable operation of the internal circuit element section. a first power supply voltage detection circuit that generates a power supply voltage, and a second power supply voltage detection circuit that is supplied with a power supply voltage from the power supply terminal and whose power supply voltage is slightly higher than the operating state holding voltage VT of the internal circuit element section and can guarantee that the operating state is maintained. A second power supply voltage detection circuit that detects a state where the lower limit reference voltage Vr or less occurs and generates a reset signal, and means that sets the internal circuit element section to an initial state in response to generation of the reset signal. A 1-chip microcontroller with the following features: