JPS60219508A - Multiplexing detection apparatus - Google Patents

Abstract

PURPOSE:To constitute the titled apparatus so as not to exert adverse effect upon control even if there is time delay in a diagnostic circuit, by feeding back the output of an intermediate value selection circuit to the input side thereof. CONSTITUTION:A second signal change-over circuit 6 is provided so as to substitute a system, which is diagnosed as abnormality among signals S1A, S1B, S1C from detectors by a diagnostic circuit 5, with the output S2 of an intermediate value selection circuit 2. Furthermore, the operation of the second signal change- over circuit 6 is effective only when one system is abnormal and becomes ineffective, when two systems are abnormal, because the residual normal one system is selected by a change-over circuit 3 in place of the output S2 of the intermediate value selection circuit 2. For example, when the signal S1A from a detector 1A becomes abnormal, no influence is exerted on the intermediate value selection circuit 2. The second change-over circuit 6 substitutes the signal S1A with the output S2 through the diagnostic circuit 5. At this time, time delay is generated but the output S2 does not change because signals S1B, S1C are normal and this time delay exerts no effect upon control. That is, by feeding back the output S2 to the circuit 2, normal output can be maintained even if input becomes abnormal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiplex detection device suitable for extracting multiplexed detection signals.

[Technical background of the invention and its problems] In process control equipment used in plants that require high reliability, such as nuclear power plants, two detectors are used to detect plant state quantities in order to improve reliability. It is often multiplexed, such as multiplexed or triplexed.

In such cases, the most probable signal from among the signals from the multiplexed detectors is usually selected and used for control.

A commonly used signal selection method is called the intermediate value selection method, and is determined as follows for N inputs.

If N is an odd number, select input values such that (N-1)/2 are larger than a certain input value and (N-1)/2 are smaller than a certain input value.

If N is an even number, select two average values of input values such that N/2-1 are larger than a certain input value and N/2-1 are smaller than a certain input value. do.

According to the intermediate value selection method described above, if N is an odd number, (N-1)/2, N
If is an even number, the failure of N/'2-1 detectors will not affect the control at all. However, conversely speaking, the intermediate value selection method is no longer effective when the number of detectors exceeds the above-mentioned number of failures even though there are N detectors. Since there are N detectors, it is ideal that the failure of N-1 detectors does not affect the control, and the reliability can be dramatically improved. To meet this requirement, a signal diagnostic circuit and a signal switching circuit are usually used together.

Hereinafter, a conventional technique in which a signal diagnosis circuit and a signal switching circuit are used together will be explained with reference to FIG. Note that N=3 is assumed to simplify the explanation.

Detector 1 (In order to distinguish each detector, A,
Add subscripts B and C. ) from the signal SI A.

SIB and SIC are input to the intermediate value selection circuit 2, the intermediate value selection circuit output S2 is input to the switching circuit 3, and the switching circuit output S3 is input to the controller 4. Signal S of each detector/
+ A, SI B, St c are also input to the switching circuit 3 and the diagnostic circuit 5 for detecting signal abnormality, and the switching circuit 3 selects an intermediate value based on the diagnosis result from the diagnostic circuit 5. Circuit output S3 and signal S+ from detector 1
A, SI B, and Sl c are switched to provide the switching circuit output S3. The operation of the switching circuit 3 is as follows.

(1) If all of SI A, Sl a, and St c are normal, or if any one is diagnosed as abnormal...
S3:52(2), When SI A and SI B are diagnosed as abnormal...S3"5IC (3), When SI B and SI C are diagnosed as abnormal...
...S3:5IA (4), if SIC, SI A is diagnosed as abnormal.
・・・・・・S3: SIB FIG. 2 explains the operation of the above-mentioned conventional example,
- signal SIA from detector IA and detector I as an example
This shows a case where the signal SIB from B becomes abnormal.

First, in the case where SIA is detected as abnormal, the above (
According to item 1), the intermediate value selection circuit output S2 remains selected. Next, if the SIB is detected to be abnormal, Ssc is selected as the switching circuit output S3 according to paragraph (2). Since SIc is a normal signal, control SIA,
Control can continue normally even in the case of a failure in two SIB series.

However, the above explanation is an ideal case, and in reality, it takes a certain amount of time for the diagnostic circuit 5 to detect a signal abnormality, and it is impossible to detect it at the same time as the signal becomes abnormal. Can not. Furthermore, the shorter the time required for this detection, the higher the possibility of false detection due to noise or the like, so it is common to intentionally create a time delay using a filter or the like.

The operation when the diagnostic circuit 5 has a time delay as described above will be explained based on FIG.

First, when the SIA becomes abnormal, no signal switching is required, so even if the diagnostic circuit has a time delay, there is no effect. However, when SIB becomes abnormal, the switching circuit 3 intermediate value selection circuit output S2 is selected during the period from when SIc becomes abnormal until the diagnostic circuit 5 detects it as abnormal (indicated by T in the figure). remains as is, and the intermediate value selection circuit output S2
is no longer a normal signal because the two series of inputs are abnormal. Therefore, during the time delay T, an abnormal signal is input to the controller 4, and normal control cannot be performed. Further, when the diagnostic circuit 5 detects the SIB as abnormal, the above (
Since the switching circuit 3 selects S1c due to 2), the signal input to the controller 4 undergoes a sudden change, giving a bump to the process, which has an adverse effect on control. Depending on the target process, such bumps can cause serious problems, and with conventional technology, even if the intermediate value selection method is combined with a signal diagnostic circuit and a signal switching circuit, reliability cannot necessarily be improved. I couldn't.

[Object of the Invention] It is an object of the present invention to provide a multiplex detection device in which the time delay of the diagnostic circuit does not adversely affect control, except for the drawbacks of the prior art described above.

[Summary of the Invention] For this reason, the present invention extracts detection signals from multiplexed detectors via an intermediate value selection circuit, and also detects signals when the multiplexed detection signals are determined to be abnormal by a signal diagnostic circuit. A further feature is that the abnormal signal is replaced with the output of the intermediate value selection circuit.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on FIG. 4. In the figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and the difference from the conventional configuration shown in FIG. 1 is that a second signal switching circuit 6 is provided, and Signal SIA from detector 1.

Among SIB and SIC, the series diagnosed as abnormal by the diagnostic circuit 5 is replaced with the intermediate value selection circuit output S2.

With the configuration shown in FIG. 4, the second signal switching circuit 6 operates as follows.

(1) If SIA is diagnosed as abnormal... Replace SIA with S2 (2) If SIB is diagnosed as abnormal... Replace SOB with S2 (3) SIc is abnormal If diagnosed as... Replace SIC with S2 Note that the operation of the second signal switching circuit 6 is effective only in the case of an abnormality in one system, and in the case of an abnormality in two systems, the operation is the same as that of the conventional configuration example. Similarly, the normal remaining 1 is used instead of the intermediate value selection circuit output S2.
Since the series is selected by the switching circuit 3, it becomes invalid.

FIG. 5 explains the operation of one embodiment of the present invention shown in FIG.
A case where signal SIB from A and detector IB becomes abnormal is shown.

First, if the SIA becomes abnormal, it does not affect the intermediate value selection circuit output S2, as described above. On the other hand, the second
The switching circuit 6 replaces SIA with the intermediate value selection circuit output S2 according to (1). Naturally, this replacement is the diagnostic circuit 5
As mentioned above, there will be a time delay.

However, the intermediate value selection circuit output S2 does not change because SIB and S1c remain normal, and this time delay has no effect on control.

Next, when SIB becomes abnormal, the first switching circuit 3 selects the remaining normal signal S+c instead of the intermediate value selection circuit output S2. in this case.

As described above, during the delay time T of the diagnostic circuit 5, the intermediate value selection circuit output S2 remains selected by the first switching circuit 3; Due to the operation of the circuit, its own output is fed back instead of SIA, so even if SIB becomes abnormal, the intermediate value selection circuit output s2 does not change (remains at a normal value), so the controller 4, a normal signal is always input. That is, the most important point of the present invention is that by feeding back to the intermediate value selection circuit 2, the intermediate value selection circuit 2 is used as a kind of storage element that continues to output a normal value even if the input becomes abnormal. The point is that there is.

FIG. 6 is a diagram for explaining the storage operation of the intermediate value selection circuit 2. In order to provide the intermediate value selection circuit 2 with storage operation, its own output is fed back as one input. This is controlled by the second switching circuit 6.
This corresponds to the case where the intermediate value selection circuit output S2 is selected instead of A. That is, the outputs of the two intermediate value selection circuits are SI
B and SIC, and the intermediate value selection circuit output is 52.

The operation of this circuit is expressed as follows.

(1) When SI B<S2<SIC, s2 does not change because S2 becomes the intermediate value itself.

(2) When S2≧SIB 52=51b.

(3) When 32≦S+c 52=S1c.

Therefore, the movement of S2 is as shown in FIG.

That is, S2 exists only between SIB and SIc, and moves to maintain the status quo as much as possible. If each signal is normal, SsB umbrella S + c, but s2 is also SIB or S
It changes according to the movement of Ic. However, if one of them becomes abnormal and becomes 5IBf:SIC, the value immediately before the abnormality is held as much as possible.

Figure 8 shows S2 for various movements of SIB and SIc.
(1) in FIG. 8 is a case in which SIB is abnormal and decreases, and Sac subsequently changes in a decreasing direction. (II) is a case where SIB is abnormal and decreases, and then S+c changes to increase. (III) SIB is abnormal and increases.

This is a case where Ssc changes in a decreasing direction after that. (IV
) is a case where 51a increases due to an abnormality and s1c subsequently changes in the increasing direction. In other words, in the circuit shown in FIG. 6, the output will never change if only one of the two inputs changes, and the output will not change even if the two inputs make different changes.

This is a circuit in which the output changes only when two human forces make similar changes. It can be said that J.

Therefore, from the above, the output S2 of the intermediate value selection circuit is
As shown in FIG. 5, it can be seen that even if SIB becomes abnormal, it becomes equal to Slc and does not become abnormal.

By the way, in the embodiment described above.

It has been explained that in the case of a two-series failure, the first switching circuit 3 selects the remaining normal l-series instead of the intermediate value selection circuit output S2, but in this case, the first switching circuit 3 is not necessarily necessary. It can also be omitted. That is, the second
The first switching circuit can be omitted by operating the switching circuit 6 as follows.

(1) If SEA is diagnosed as abnormal... Replace SIA with Sl (2) If SIB is diagnosed as abnormal... Replace SIrs with Sl (3) S t c If it is diagnosed as abnormal...
・Replace SIC with Sl ('l) If S I A #S I B is diagnosed as abnormal... Replace 5trs with Sl et al. (5) If SIB, 51 C is diagnosed as abnormal ...
...Replace S1c with SIA (6) If Ss C and SI A are diagnosed as abnormal...
...replace SIA with SIB, and for the sake of simplification, all of the explanations above assume that the number N of multiplexed detectors is N=3, but it goes without saying that it can be applied in exactly the same way when N≧4. .

On the other hand, when N=2, the present invention can be applied by configuring as shown in FIG. 9, for example. That is, in the configuration shown in FIG. 9, if 1, for example, SIA becomes abnormal, no abnormality occurs in the intermediate value selection circuit output S2. Therefore, there is no problem even if the first switching circuit 3 selects the intermediate value selection circuit output S2 during the delay time of the first diagnosis result 5, and process bumps can be reliably prevented. Furthermore, in this case, since feedback is provided to the intermediate value selection circuit 2 from the beginning, the second switching circuit 6 is unnecessary.

However, in this case, the intermediate value selection circuit output S2 is not necessarily the accurate intermediate value ((S I A + S s B )/2).

However, in terms of time, the signal from the detector 1 usually fluctuates due to noise, etc., and the average value of the time distribution taken by the intermediate value selection circuit output S2 and (51A+
The average values of the time distributions taken by Ss B)/2 are equal. Therefore, 52=(SI A, Sl a)/2. Here, 11H represents the time average. In this sense, it can be said that the intermediate value selection circuit output S2 is similar to (SIA+S+a)/2.

[Effects of the Invention] As described above, according to the present invention, since the output of the intermediate value selection circuit is fed back to the input side, it functions as a kind of memory element that outputs a normal value even if an input error occurs. A highly reliable multiplex detection device that does not adversely affect control even if there is a time delay in one diagnostic circuit can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional multiplex detection device. 2 and 3 are time charts for explaining the operation of FIG. 1, FIG. 4 is a block diagram of a multiplexing detection device according to an embodiment of the present invention, and FIG. 5 is an operation of FIG. 4. Figure 6 is a block diagram showing the basic circuit of the present invention, and Figure 7 is a time chart 1-1 for explaining the operation of Figure 6. :Morning→ is a time chart for explaining the operation of FIG. 6, and FIG. 9 is a plotter diagram of a multiplex detection device showing the configuration of another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Detector, 2...Intermediate value selection circuit, 3...First switching circuit, 4...Controller, 5...Diagnostic circuit. 6...Second switching circuit. (7317) Agent Patent Attorney Nori Chika Ri (
(and 1 other person) Figure 1 Figure 2 Fees 岨斞1) Matezu Akito Figure 3 Oφ″fA Oh Nakayama Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] In a multiplexed detection device that includes a signal diagnostic circuit that determines whether a detection signal from a multiplexed detector is normal or abnormal, and extracts a normal detection signal via an intermediate value selection circuit, the output of the intermediate value selection circuit is A multiplex detection device characterized in that feedback is provided to the input side.