JPS60216634A - Synchronous controller - Google Patents

Abstract

PURPOSE:To detect a tail ridge of a synchronizing window of a reference station with high accuracy at a simple circuit by converting a signal detected from a timing error detecting circuit into a control signal at a transmission timing control circuit and applying the signal to a synchronizing burst generating circuit. CONSTITUTION:The synchronizing burst of a reference station demodulated from a demodulation circuit 12 is given to a timing error detection circuit 13. A transmission timing error detected from the timing error detection circuit 13 is given to a control circuit 14 in the transmission timing. A control signal is given to a synchronizing burst generating circuit 6 from the transmission timing control circuit 14. As a result, a reception timing 106 of a burst identification code in the reference station synchronizing burst 104 and a measuring code added to the tail end of the reference station synchronizing burst 104 are controlled always so that the time difference with the timing 107 cut off at the tail ridge 103 of the synchronizing window 101 of the reference station.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a synchronous control device for a satellite switch time division multiple access communication system. The present invention relates to a synchronization control device for a time division multiple access communication frame produced by a matrix switch circuit of a communication satellite by a reference station providing a time reference to an earth station -i in a satellite switch time division multiple access communication system.

[Explanation of conventional technology]

Satellite Switch Time Division Multiple Access (SS-TDMA)
This communication method is one of the important methods for future large-capacity satellite communications, and the synchronization control to the time division multiple access frame created by the matrix switch circuit (MSM) of the reference station in the satellite switch time division multiple access communication method is based on this method. This is an important basic technology. Furthermore, the most important matter in the above synchronization control is how accurately the time reference of the time division multiple access frame created by the matrix switch circuit is detected. Conventionally, the time reference of the time division multiple access frame created by the matrix switch circuit is detected using a measurement code (METRI G) in which the trailing edge of a special reference station synchronization window for the reference station to perform synchronization control is added to the rear of the reference station synchronization burst. ) is known to be detected in an analog or digital manner.

However, conventional methods have had drawbacks such as insufficient detection accuracy and improved detection accuracy significantly increases the amount of hardware.

[Purpose of the invention]

The object of the present invention is to eliminate these drawbacks and to provide a synchronization control 11 device that provides the necessary and sufficient accuracy of detection of the time reference of a time division multiple access frame with a relatively simple circuit.

[Features of the invention]

The first invention provides a demodulating means for demodulating a measurement code added to the rear part of a reference station synchronization burst cut out by the rear part of a reference station synchronization window created by a matrix scan on a communication satellite, and In the synchronization control device for a satellite switch time division multiple access communication system, the synchronization control device includes means for detecting an error between the timing of the measurement code and a reference value, and a transmission timing control means for controlling the transmission timing based on the output of the means. The detection means includes a serial-to-parallel converter that converts the serial measurement code from the demodulator into a parallel signal, and a correlation detector that detects the correlation of errors in the parallel data converted by the serial-to-parallel converter in units of several bits. a threshold setting means for setting a threshold value of the correlation detection means; and a transmission timing control means for counting the time from the starting point of the measurement code until the detection output of the correlation detection means is generated. The present invention is characterized in that a necessary and sufficient detection accuracy of the time reference of a time division multiple access frame is obtained by a relatively simple circuit.

The second invention performs one-stage correlation detection in the first invention, but the present invention performs two-stage correlation detection to further improve the detection accuracy and reduce jitter in the data obtained by the first-stage correlation detection. (Explanation by Examples) Examples of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of a satellite switch time division multiple access communication system to which the synchronous control device of the present invention is applied. 1st
In the figure, ■ indicates the satellite-mounted receiver, 2 indicates the matrix switch circuit, 3 indicates the 11J-mounted transmitter, 4 indicates the multi-beam antenna, 5 indicates the earth station, and A, B, C, and D indicate the spot beam zones. , - four spot beam zones A as an example.

Each earth station in B, C, and D5. 54 are used to perform predetermined time division multiple access communication using the matrix switch circuit 2. Earth stations 51-54 in spot beam zones A, B, C, D are each connected to receiver 1 on fgj M via multi-beam antenna 4. Receiver 1
The output of is connected to a matrix switch circuit 2, and after predetermined switching is performed, it is connected to a transmitter 3.

FIG. 2 is a diagram showing an example of a connection mode of the matrix switch circuit 2 that switches and connects each spot beam zone A to D in the time division multiple access communication system shown in FIG. 1. In FIG. 2, in the first time slot of the time division multiple access frame, the signal transmitted from spot beam zone B is received in all spot beam zones 8 to D, and in the last time slot of the time division multiple access frame, the signal transmitted from spot beam zone B is received by the spot beam zone B. From zone C to spot beam zone A, from spot beam zone D to spot beam zone B,
From spot beam zone A to spot beam zone C, from spot beam zone B to spot beam zone D
Indicates that it will be sent to. Note that in this example, the reference station is located in spot beam zone B.

FIG. 3 shows the return window to the local station (the time slot in which the signal passes through the matrix switch circuit 2 is called a window) when the satellite is viewed from the subo-nod beam zone B in the connection mode shown in FIG. 101 is a reference station synchronization window, and 102 is a slave station synchronization window and a data window.

FIG. 4 is a block diagram of a satellite switch time division multiple access communication system including a synchronization control device in a reference station. In FIG. 4, synchronous burst generation circuits 6 to 5
The reference station synchronous hearth) 104 shown in the figure is connected to the modulation circuit 7, and the PSK (Phase 5
The modulated signal is sent to the transmitter circuit 8.
1ffl(, is transmitted to the satellite 9 via .

In the communication satellite 9, the signal is connected via the receiver 1 to the matrix switch circuit 2, and the signal is switched and connected by the matrix switch circuit 2, and is transmitted from the transmitter Ia3 to the earth station 5. The earth station 5 is connected to a demodulation circuit 12 in a synchronous control device 11 via a reception circuit 10.

Here, the feature of the present invention is the timing error detection portion surrounded by a dashed line. That is, the demodulation circuit 12
The reference station synchronization burst demodulated from the reference station is connected to the timing error detection circuit 13. Timing error detection circuit 13
The transmission timing error detected from the transmission timing error is connected to the transmission timing control circuit 14.

A control signal from the transmission timing control circuit 14 is connected to the synchronous burst generation circuit 6.

The operation of the synchronization control device having such a configuration will be explained. The reference station synchronization parse number 04 shown in FIG. 5 generated by the synchronization burst generation circuit 6 is subjected to PSK modulation on the intermediate frequency signal carrier wave by the modulation circuit 7, and is transmitted to the communication satellite 9 via the transmission circuit 8. In the communication satellite 9, the signal is transmitted via the receiver a1, the matrix switch circuit 2, and the transmitter 3 to the earth station 5. At the earth station 5, the reference station synchronous burst 104 enters the demodulation circuit 12 via the reception circuit 10, and the transmission timing error of the demodulated reference station synchronous burst 104 is detected by the timing error detection circuit 13, and the synchronous burst transmission timing is determined based on the result. The control circuit 14 correctly controls the transmission timing of the reference station synchronization burst.

FIG. 5 is a diagram showing the normal positional relationship of the reference station synchronization burst in the reference station synchronization window, and the timing is controlled so that the reference station synchronization burst 104 is in the relationship as shown in FIG. 5 in the reference station synchronization window 101. That is, reception timing 1 of the burst identification code (Llnique word) in the reference station synchronization burst 104
06 and the timing 107 at which the measurement code added to the rear of the reference station synchronization burst 104 is cut off at the trailing edge 103 of the reference station synchronization window 101 is constantly controlled so that the time difference is a predetermined value.

As described above, the reference station in the satellite switch time division multiple access communication system uses the reference station synchronization burst 104 to synchronize with the time division multiple access frame generated by the matrix switch circuit 2 of the satellite, and other slave stations use the synchronization control transmitted by the reference station. The illuminating reference station synchronization burst is received as a time reference for the time division multiple access frame.

A feature of the present invention is that it provides a method for the reference station to accurately detect the trailing edge of the reference station synchronization window 101 using a relatively simple circuit using the measurement code of the W$ station synchronization burst 104. The contents will be explained in detail with reference to FIG.

FIG. 6 is a block diagram of the timing error detection circuit of the synchronous control device of the present invention. In FIG. 6, the measurement codes of channel P and channel Q (in the case of 4-phase PSK modulation method) are logic "0" when normal G is received.
It is assumed that the timing error detection circuit 13 is interfaced with the timing error detection circuit 13. The measurement code for channel P is input to the input terminal 51 of the timing error detection circuit 13, and the measurement code for channel Q is input to the input terminal 5 of the timing error detection circuit 13.
2 is input. The measurement codes of channels P and Q that are manually input to the timing error detection circuit 13 are subjected to coincidence detection bit by bit from the beginning of the measurement codes by the OR gate 15. If both channel P and channel Q are received normally, exclusive or game 5
The output of exclusive OR gate 15 becomes logic "0", and if one or both of channel P and channel Q are received in error, the output of exclusive OR gate 15 becomes logic "1".

Here, the purpose of detecting a match between the measurement codes of channel P and channel Q using exclusive OR game 5 is to use the randomness of the received code to This is to make the trailing edge of the reference station synchronization window clear. therefore,
In the case of the two-phase PSK modulation method, the measurement code corresponding to the channel Q is not input. The measurement code whose coincidence is detected in this way is opened by the measurement gate 1-105 (the gate width is equal to the length of the n1 measurement code) shown in FIG. 5, which is manually input to the input terminal 53 of this circuit. The signal passes through an AND gate 16 and is supplied to a serial-to-parallel conversion circuit 17. On the other hand, the rise detection circuit 2 detects the rise of the needle measurement gate 105.
3, and the timing counter circuit 24 starts counting.

The serial/parallel conversion circuit 17 shifts the measurement code bit by bit, and outputs the number of error bits within a range of, for example, 8 bits for each symbol. The range of bits within which the error Bisoto number is to be viewed can be arbitrarily set depending on how many bits of the output bits of the serial-to-parallel conversion circuit 17 are to be viewed at the same time. The output of the serial-to-parallel conversion circuit 17 is input to the correlation detection circuit 18, where when the number of error bits within 8 bits becomes larger than the value set by the threshold setting port B19, the output signal is input to the next stage of the serial-to-parallel conversion circuit. It is supplied to the conversion circuit 2o. Similarly, the number of error bits within the appropriately set bit number range is compared in the correlation detection circuit 21 with the value set by the threshold setting circuit 22, and the number of error bits within the range of the number of bits set appropriately is compared with the value set by the threshold setting circuit 22, and it is determined that the number of error bits is larger than the set threshold. The timing counter circuit 24 outputs a signal at certain times, and the timing counter circuit 24 stops counting when the signal rises. The count value of the timing 91 number circuit 24 at this time represents the timings 106 to 107 shown in FIG. 5 by the number of symbols.

Therefore, this value is outputted to the output terminals 541 to 54ffi and supplied to the next stage transmission timing control circuit 14 shown in FIG. 4, where it is compared with a specified value and the number of symbols corresponding to the error is set as transmission timing control information. Will be using it. Although the transmission timing control circuit 14 performs two stages of correlation detection on the number of error codes of the received measurement codes, timing errors can also be detected by one stage of correlation detection. However, in the present invention, two-stage correlation detection is performed for the purpose of increasing detection accuracy, and a second-stage correlation detection circuit 21 is provided for the purpose of compressing the jitter of data obtained by the first-stage correlation detection.

By doing this, as described above, it is possible to detect the transmission timing error of the WYJA station synchronization burst with sufficient accuracy for practical use using a relatively simple circuit. If it is desired to further improve the detection accuracy, the objective can be achieved by averaging or integrating the detected values over several time division multiple access frames to several tens of time division multiple access frames.

〔Effect of the invention〕

As explained above, the present invention is a method for a reference station to perform synchronization control on time division multiple access frames created by a satellite matrix switch circuit, which is the most important technology in the satellite switch time division multiple access communication system. In synchronization with a reference station serving as a time reference, there is an excellent effect in that the trailing edge of the int can be detected with a predetermined accuracy using a relatively simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a satellite switch time division multiple access communication system to which the synchronous control device of the present invention is applied. FIG. 2 is a diagram showing a connection mode using a matrix switch circuit of a satellite. FIG. 3 is a diagram showing the local station return window seen from the B beam zone in FIG. 2. FIG. 4 is a block diagram of a satellite switch time division multiple access communication system in which the synchronous control device of the present invention is used. FIG. 5 is a diagram showing a state in which the reference station synchronization burst is transmitted at normal timing during the reference station synchronization win. FIG. 6 is a block diagram of the timing error detection circuit of the synchronous control device of the present invention. DESCRIPTION OF SYMBOLS 1... Onboard receiver, 2... Matrix switch circuit, 3... Onboard transmitter, 4... Multi-beam antenna, 5... Earth station, 6... Synchronous burst generation circuit,
7... Modulation circuit, 8... Transmission circuit, 9... Communication satellite, 10... Receiving circuit, 11... Synchronization control device, 1
2... Demodulation circuit, 13... Timing error detection circuit, 14... Transmission timing control circuit, I5... Exclusive OR gate, 16... AND gate, 1
7.20...Series parallel modulation circuit, 1B, 21...
Correlation detection UBB, 19.22...threshold setting circuit,
23... Rise detection circuit, 24... Timing counting circuit, 101... Reference station synchronization window, 103...
- Trailing edge of reference station synchronization window, 104... Reference station synchronization burst, 105... Measurement gate, 106...
Reception timing, 107...timing at which the measurement code is cut off at the trailing edge of the reference station synchronization window. Patent Applicant NEC Corporation Agent Patent Attorney Nao Ide Kotozume 1 Mouth M5 Diagram

Claims (2)

[Claims] (1) demodulation means for demodulating the measurement code added to the rear of the reference station synchronization burst cut off by the trailing edge of the reference station synchronization window created by the matrix switch on the communication satellite; In a synchronization control device for a satellite switch time division multiple access communication system, which includes means for detecting an error with a reference value, and a transmission evening/timing control means for controlling transmission timing based on the output of the means, the detecting means is , a serial-to-parallel conversion means for converting the serial measurement code from the demodulation means into a parallel signal; a correlation detection means for detecting the correlation of errors in the parallel data converted by the serial-to-parallel conversion means in units of several focus points; threshold setting means for setting a threshold value of the correlation detection means; and a counter for counting the time from the starting point of the measurement code until the detection output of the correlation detection means is generated and outputting it to the transmission timing control means. A synchronous control device comprising means. (2) means for demodulating the measurement code added to the rear of the reference station synchronization burst cut off by the trailing edge of the reference station synchronization window created by the matrix sinch on the communication satellite; and a means for demodulating the timing of the measurement code from this demodulation means In a synchronous control device for a satellite switch time division multiple access communication system, which includes means for detecting an error with a reference value, and a transmission timing control means for controlling transmission timing based on the output of this means, the means for detecting the above-mentioned A first serial-parallel converter converts the serial measurement code from the demodulator into a parallel signal, and a first serial-parallel converter detects the correlation of errors in the parallel data converted by the first serial-parallel converter in units of several bits. a first threshold setting means for setting a threshold of the first correlation detecting means; and a second serial-to-parallel converter for converting the output of the first correlation detecting means into parallel. means, a second correlation detection means for further performing correlation detection on the correlation detection signal converted by the second serial-to-parallel conversion means, and a second correlation detection means for setting a threshold value of the second correlation detection means. Synchronization characterized by comprising a threshold setting means, and a counting means for counting the time from the starting point of the measurement code until the detection output of the correlation detection means is generated and outputting it to the transmission timing control means. Control device.