JPS60209785A - Screen shifter for display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a display device that superimposes and displays the contents of a plurality of image memories. This relates to a technique for moving in a vertical direction or the like.

Conventional technology and problems When displaying multiple figures, characters, etc. on a screen and moving one of them in the horizontal or vertical direction of the screen independently of the other figures, conventionally, after the movement, The contents of the image memory were rewritten according to the display information corresponding to the screen. However, since it takes a relatively long time to rewrite the image memory, with this method, the screen display may be interrupted, making it difficult to move the figure smoothly.

Purpose of the Invention The present invention improves these conventional drawbacks, and
The purpose is to be able to move only a specific figure etc. smoothly and independently of other figures etc.

Structure of the Invention The gist of the present invention is to provide a display device that obtains a video signal by superimposing the outputs of a plurality of image memories each having a storage area larger than the display area of one screen, which corresponds to each image memory. Then, the contents of the register in which the screen shift amount is set, and the display address of the CRT controller that synchronizes and cyclically accesses the storage information of the plurality of image memories are added to the corresponding image memory. The screen shifter of a display device is provided with an adder that is input manually as an address signal. Therefore, if you change the contents of the register corresponding to the image memory in which the figure, etc. you want to move is written at a predetermined period, and the contents of other registers are fixed, only the image memory in which the figure, etc. you want to move, is written. will be accessed from an address that is shifted by the amount of change in other image memory and registers, so it is possible to move only a specific figure, etc. independently of the others, and the operation required to do so changes the contents of the register. It has the advantage that it can be done in an extremely short time. Therefore, smooth movement is possible.

Embodiment of the Invention FIG. 1 is a block diagram of main parts of an embodiment of the invention. In the figure, a CRT controller 5 has image memories 1 to 4.
Display address a, read signal S.

Generates the read clock C for the parallel-serial converters 6 to 9, and includes a register 50 for setting the number of horizontal bytes of the display area and a register for setting the maximum number of horizontal bytes for the image memories 1 to 4. 51, a counter 52 for generating a display address a, a register 53 for setting the precent value of the counter 52, and a control section 54. The control unit 54 outputs a clock d that causes the counter 52 to count up, and also generates a timing signal e that causes the counter 52 to precent the precent value set in the register 53. Further, when the counter 52 is amplified to count the maximum number of horizontal bytes of the display area (for example, 64), the value obtained by adding the value obtained by subtracting the contents of the register 50 from the contents of the register 51 to the count value is set in the register 53. and sends a timing signal e to pre-centre the value of the register 53 to the counter 52,
Continue count amplification processing using clock d. Also, if the value of the counter 52 is the maximum value of the display area (for example, 64
When the number X 48 ) is reached, the leading value of the display (for example, 1) is set in the counter 52 via the register 53, and control is executed to return the display address to the initial value. Display address a' of CRT controller 5 is applied to full adders 10-13, read signals are applied to multiplexers 14-17, and read clock C is applied to parallel-serial converters 6-13.
Added error to 9.

The registers 18 to 21 store values corresponding to the screen shift amount, and are set by the microcomputer 23 via the data bus 22. Registers 18-21
The output of is added to the other input of full adders 10-13. The full adders 10 to 13 add the contents of the register 18 and the display address a to the multiplexer 14.
Enter ~17. In addition to read signals, the read/write signals f and write h from the microcomputer 23 are input to the multiplexers 14 to 17, and the input is selected by the switching signal g output from the microcomputer 23. The images are then output to the image memories 1-4. That is,
When accessing with the CRT controller 5, the outputs of the full adders 10 to 13 and the read signal Suga image memories 1 to 4 are used.
When the image memories 1 to 4 are accessed by the microcomputer 23, the read/write signal f
and data h are input to image memories 1-4.

Image memories 1 to 4 are memories for writing figures to be displayed, and have storage areas larger than the display area for one screen. For example, set the number of horizontal dots on the screen to 512 (6
4 hides), and the number of vertical dots is 384 (4 B bytes), the display area for one screen is 64 x 48 hides, but a larger storage area should be provided to account for movement. It is.

FIG. 2 shows a state in which a total of xn addresses of image memories 1 to 4 are arranged in correspondence with the display screen. In addition, in Fig. 2, (1), (64), (m), (mx47
+1), (mX47+64), (mx(n-1)),
(mxn) indicates an address value.

If the contents of registers 18 to 21 are all O and the first value of the display address a of the CRT controller 5 is 1, a total of 64 x 48 bytes of area surrounded by the broken line P in FIG. 2 will be displayed on the CRT screen. The display area moves as the contents of the registers 18 to 21 increase. The outputs of the image memories 1-4 are converted into serial signals by parallel-serial converters 6-9, combined by an OR circuit 24, and output as video signals to C and RT (not shown).

When the CRT controller 5 outputs the display address a from address 1) to address (64), it then outputs the display address a from address (m+1) to address (m+64), as indicated by the broken line in FIG. Area P (
If the address signal a is set to output an address signal a that accesses an area equal to the size of the display area, for example, the shapes of ○, △2, and ☆ are displayed on the CRT as shown in Figure 3(a). When displaying on the screen, for example, as shown in FIG. A mouth figure is stored in P and a star figure is stored in area P of the image memory 4 at corresponding positions in the display area.

If you want to move only the ○ figure horizontally to the right by 8 dots in 1 second, change the contents of register 18 by 1.
It increases at a rate of 1 per second, and other registers 19 to 2
The contents of 1 are fixed. In this way, the first address where only image memory 1 is accessed will be shifted to the right by 1 every second, making it possible to move only the ○ shape in the horizontal direction independently of other shapes. . Also,
If only the ◯ figure is to be moved vertically downward at a rate of 1 dot per second, for example, the contents of the register 18 may be increased by m every second. Similarly, if only the ○ figure is to be moved to the lower right by 8 dots in the horizontal right direction and 1 dot in the vertical downward direction per second, the contents of the register 18 may be increased by m+l every second. If it is desired to move only other figures independently, the contents of registers 19-21 may be increased.

Note that if the contents of registers 18 to 21 are set so that the display area is approximately in the center of image memories 1 to 4, the figure can be moved horizontally to the left or upwards by subtracting the contents of registers 18 to 21. can be moved to.

Although the embodiment of FIG. 1 relates to a graphic display, the invention is also applicable to character displays. In this case, for example, the image memory 4 may be replaced with a character memory and a character generator may be added separately.

As described in detail, according to the present invention, a register in which the screen shift tSt is set corresponds to each image memory, and the contents of the register and the storage information of the plurality of image memories are synchronized. This device is equipped with an adder that adds the display address of the CRT controller that is cyclically accessed and inputs the result as an address signal to the corresponding image memory, and corresponds to the image memory in which the figure, etc. to be moved is written. By changing the contents of the register at a predetermined period and fixing the contents of other registers, only the image memory in which the figure you want to move is written will be separated from the other image memory at an address shifted by the amount of register change. It is possible to move only a specific figure, etc. independently of the others, and the operation required for this is only to change the contents of the register, so it has the advantage that it can be carried out in an extremely short time. Therefore, smooth movement is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, FIG. 2 is an explanatory diagram of image memories 1 to 4, and FIG. 3 is an explanatory diagram of the operation of the present invention. 1 to 4 are image memories, 5 is a CRT controller, 6 to 9
is a parallel serial converter, 10 to 13 are full adders,
18 to 21 are registers, and 23 is a microcomputer. Patent Applicant Fanasoku Co., Ltd. Representative Patent Attorney Gogo Tamamushi Two Outside the Department Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a display device that obtains a video signal by superimposing the respective outputs of a plurality of image memories each having a storage area larger than a display area for one screen, there is provided a register in which a screen shift m is set corresponding to each image memory. , an adder that adds the contents of the register and a display address of a CRT controller that synchronizes and cyclically accesses the storage information of the plurality of image memories and inputs the result to the corresponding image memory as an address signal. A screen shifter for a display device, characterized in that: