JPS60203054A - Mounting confirmation of circuit to be controlled - Google Patents
Mounting confirmation of circuit to be controlledInfo
- Publication number
- JPS60203054A JPS60203054A JP5915084A JP5915084A JPS60203054A JP S60203054 A JPS60203054 A JP S60203054A JP 5915084 A JP5915084 A JP 5915084A JP 5915084 A JP5915084 A JP 5915084A JP S60203054 A JPS60203054 A JP S60203054A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- controlled
- circuit
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/08—Indicating faults in circuits or apparatus
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は制御回路に汎用■０ボートを介して接続される
被制御回路の実装／非実装を検出する方式、さらに詳し
く云えば電子交換機における加入者回路の実装／非実装
を確認するに適した被制御回路実装確認方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for detecting implementation/non-implementation of a controlled circuit connected to a control circuit via a general-purpose This invention relates to a controlled circuit implementation confirmation method suitable for confirming implementation.
上記成子交換ト幾における加入者回路等では、同一種類
の回路が多数実装されてしる。A large number of circuits of the same type are installed in the subscriber circuits and the like in the above-mentioned Nariko exchange network.
このような装置にお−では、中央処理装置は加入者回路
対応にデータを持ち、必−要な時にそのデータを参照し
て被制御対象となる回路の実装／非実装を確認するのが
通例であった。In such equipment, the central processing unit usually has data corresponding to subscriber circuits, and refers to that data when necessary to check whether the circuit to be controlled is installed or not. Met.
この場合、回路の挿抜のたびに対応するデータの書換え
をする必要があり、装置の保守や増設手順が煩雑になる
欠点があった。In this case, it is necessary to rewrite the corresponding data each time a circuit is inserted or removed, which has the disadvantage of complicating maintenance and expansion procedures for the device.
この実装検出をハードウェア的に実施するものとして、
被検出対象回路に河等かの信号折返回路を設けるとか、
被検出対象回路に実装／非実装を意味する信号線を追加
するものがあるが、そのための専用回路または入出力端
子などが増加し、コストアップの要因となっていた。As a hardware implementation of this implementation detection,
For example, installing a signal return circuit such as a river in the circuit to be detected.
Some devices add a signal line to indicate whether the circuit to be detected is mounted or not, but this increases the number of dedicated circuits or input/output terminals, which increases costs.
本発明の目的は被制御回路に特別の回路や信量線を付加
する必要のな力、安価で簡便に被制御回路の実装状態を
確認することのできる方式を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method that can easily and inexpensively check the mounting state of a controlled circuit without the need to add a special circuit or signal line to the controlled circuit.
前記目的を達成するために本発明による被制御回路実装
確認方式は中央処理装置に接続され、中央処理装置から
の制御信号を開閉制御し、その出力が外部接続用端子に
接続された３レベルの出力ゲートと前記外部接続用端子
てその入力が接続された入力ゲートとを含む入出力ボー
トと、前記入出力ボートに挿抜可能で、挿入をしたとき
、前記外部接続用端子に接続され、前記中央処理装置に
制御される被制御回路基板複数個からなり、前記被制御
回路が制御されて力ないとき、前記出力ゲートを高イン
ピーダンス状態に制御し、前記入力ゲートの出力によっ
て被制御回路基板が実装されてＡるか否かを判断するよ
うに構成しである。In order to achieve the above object, the controlled circuit implementation confirmation method according to the present invention is a three-level circuit connected to a central processing unit, which controls the opening and closing of control signals from the central processing unit, and whose output is connected to an external connection terminal. an input/output board including an output gate and an input gate to which the external connection terminal is connected; and an input/output board that can be inserted into and removed from the input/output board, and when inserted, is connected to the external connection terminal and the center It is composed of a plurality of controlled circuit boards controlled by a processing device, and when the controlled circuit is controlled and is inactive, the output gate is controlled to a high impedance state, and the controlled circuit board is mounted by the output of the input gate. The configuration is such that it is determined whether or not the result is A.
以下、図面を参照して本発明をさらに詳しく説明する。Hereinafter, the present invention will be explained in more detail with reference to the drawings.
第１図は本発明による被制御回路実装確認方式の実施例
を示す回路ブロック図である。図におＡて、００は中央
処理装置であり、汎用ＩＯポートＰＯＥ、Ｔは中央処理
装置ＣＣの入出力命令により作動子る。被制御回路基板
０ＫＴｊ （ｊ＝１．２．３・・川 ）は汎用■０ボー
トＰＯＲＴの出力レベルによって動作するように構成さ
れている。FIG. 1 is a circuit block diagram showing an embodiment of the controlled circuit implementation confirmation method according to the present invention. In the figure, 00 is a central processing unit, and general-purpose IO ports POE and T are activated by input/output commands from the central processing unit CC. The controlled circuit board 0KTj (j=1.2.3...kawa) is configured to operate according to the output level of the general-purpose ■0 port PORT.
第２図は第１図の汎用ＩＯボートＰＯＲＴと破制御回路
基板ＯＫＴの詳細を示す回路図であツブＦＦと、フリッ
プフロップＦＦの出力に接続され、０．１および高イン
ピーダンス状態の３値を取り得る出力ゲートＧ１と、出
力ゲートＧ！の出力が接続された外部接続用端子Ａと、
この外部接続用端子人に入力が接続された入力ゲートと
、抵抗Ｒ１とを含み構成されている。Figure 2 is a circuit diagram showing the details of the general-purpose IO boat PORT and failure control circuit board OKT in Figure 1.They are connected to the outputs of the knob FF and flip-flop FF, and are connected to the outputs of the 0.1 and high impedance states. Possible output gate G1 and output gate G! External connection terminal A to which the output of is connected,
It is configured to include an input gate whose input is connected to this external connection terminal, and a resistor R1.
中央処理装置Ｃｏはその出力命令によってフリップ７０
ツブＦＦ’を自由に書換可ｎ目であり、また、出力ゲー
トＧｌの制御信号ＥＮを制御して端子Ａの入出力モード
を指定できる。The central processing unit Co performs flip 70 according to its output command.
The n-th knob FF' can be freely rewritten, and the input/output mode of the terminal A can be specified by controlling the control signal EN of the output gate Gl.
一方、被制御回路基板ＯＫＴはここでは簡単のため発光
ダイオードの点滅回路としており、発光ダイオードＬＥ
Ｄ、発光ダイオード駆動ゲートＧ３および抵抗Ｒ２とを
含み構成される。On the other hand, the controlled circuit board OKT is here assumed to be a light-emitting diode blinking circuit for simplicity, and the light-emitting diode LE
D, a light emitting diode drive gate G3, and a resistor R2.
汎用ＩＯボー１−ＰＯＲ，Ｔｂよび被ｌｂｌ制御回路基
板ＯＫＴに設けられた抵抗Ｒ１とＲ２の値は出力ゲート
の駆動能力に見合込、かつ出力ゲートＧｔが高インピー
ダンスのとき、すなわち汎用入出カポ−） Ｐ ＯＥ
Ｔが入力モードのとき、被制御回路基板ＯＫＴが接続さ
れてｂれば入点の信号レベルｘ＝１．被制御回路基板Ｏ
ＫＴが接続されていなければＡ点の信号レベルＸ＝Ｏと
なるように設定される。The values of the resistors R1 and R2 provided on the general-purpose IO board 1-POR, Tb and the lbl control circuit board OKT are determined based on the driving ability of the output gate, and when the output gate Gt is high impedance, that is, when the general-purpose input/output capacitor is ) P OE
When T is in the input mode, if the controlled circuit board OKT is connected and b, the input signal level x=1. Controlled circuit board O
If KT is not connected, the signal level at point A is set to X=O.
汎用入出カポ−）ＰＯＲＴは通常出力モードに設定され
、中央処理装置ＣＣは被′１１ｉｌ制御回路基板０ＫＴ
ｊに搭載された発光ダイオードＬＥＤの点滅制御を行な
う。General-purpose input/output capo) PORT is set to normal output mode, and the central processing unit CC is connected to the '11il control circuit board 0KT.
Controls the blinking of the light emitting diode LED mounted on j.
中央処理装置００が被制御回路基板０ＫＴｊの有無の判
定を必要とする場合、対応する汎用入出力ボートＰＯＲ
Ｔを入力モードに切換え、入力ゲートＧ２の出力信号２
を読み取れば上述の条件より容易に被制御回路基板０Ｋ
Ｔｊが接続されてしるか否かを判断できる。この判定は
破制御回路基板の制御をしてｂない期１１］、すなわち
発光ダイオードが点灯して１．６ ｆｚ １４期間に行
なえば、出力ゲートＧｌが高インピーダンスであるので
ゲートＧ３の入力レベルは１″に保たれるため発光ダイ
オードの点滅に影・啓を与えることはなｌＡ。When the central processing unit 00 needs to determine the presence or absence of the controlled circuit board 0KTj, the corresponding general-purpose input/output board POR
Switch T to input mode, output signal 2 of input gate G2
If you read the above conditions, you can easily set the controlled circuit board to 0K.
It can be determined whether Tj is connected or not. If this judgment is made during period 11] when the control circuit board is not controlled, that is, during period 1.6 fz 14 after the light emitting diode is turned on, the input level of gate G3 will be Since it is kept at 1", it does not give any shadow or illumination to the blinking of the light emitting diode.
本発明において、汎用入出力ボートＰ ＯＲＴが使用さ
れてｂるが、このボートには現在市販されており、自由
に入出力モードを設定し得る、いｂ ゆるプログラマブ
ル■０ボート等が利用できる。In the present invention, a general-purpose input/output boat PORT is used, but any programmable 0 boat, etc., which is currently commercially available and whose input/output mode can be set freely, can be used.
本発明は以上、詳しく説明したように制御用出力ボート
を実装検出用入力ポートとして併用しているので、被制
御回路１１１１１ Ｋ ％別な回路や端子を追加するこ
となく、容易に被制御側回路の有無を確認できる効果が
ある。As described in detail above, the present invention uses the control output port as an input port for mounting detection, so the controlled circuit can be easily connected to the controlled circuit without adding any other circuit or terminal. This has the effect of confirming the presence or absence of
このことは、例えば６子交喚機の加入者回路に通用すれ
ば引き抜かれてｂる加入者回路へ着信することを防止で
き、したがって加入者データを変Ｗ干るととなく加入者
回路を挿抜しうることになり、採寸性向上に大きな効果
があることは明らかである。For example, if this goes through the subscriber circuit of a 6-wire telephone, it can prevent calls from being pulled out and arriving at the subscriber circuit, and therefore, changing the subscriber data will inevitably cause the subscriber circuit to be disconnected. It is clear that this has a great effect on improving the ease of measurement since it can be inserted and removed.
第１図は本発明による被制御回路実装確認方式の実施例
を示すブロック図、第２図は第１図の汎用入出力ボート
と被制御回路基板の詳細を示す回路図である。
Ｃｏ・・・中央処理装置
ＰＯＲＴ・・・入出力ポート
ＯＫ Ｔ・・・被制御回路基板（′ｍ制御回路）Ｇ１・
・・出力ゲート（３レベル）
Ｇ２・・・入力ゲート Ｇ３・・・ゲートＬＥＤ・・・
発光ダイオード Ｒ１，Ｒ２・・・抵抗特許出願人 日
本電気株式会社
代理人 弁理士 井 ノ ロ 壽FIG. 1 is a block diagram showing an embodiment of the controlled circuit mounting confirmation method according to the present invention, and FIG. 2 is a circuit diagram showing details of the general-purpose input/output board and the controlled circuit board of FIG. 1. Co... Central processing unit PORT... Input/output port OK T... Controlled circuit board ('m control circuit) G1.
...Output gate (3 levels) G2...Input gate G3...Gate LED...
Light emitting diode R1, R2...resistance Patent applicant Hisashi Inoro, agent for NEC Corporation, patent attorney
Claims (1)
を開閉制御し、その出力が外部接続用端子に接続された
３レベルの出力ゲートと前記外部接続用端子にその入力
が接続された入力ゲートとを含む入出力ボートと、前記
入出力ボートに挿抜ｆＴｒ能で、挿入をしたとき、前記
外部接続用端子に接続され、前記中央処理装置に制御さ
れる被制御回路基板複数個からなり、被制御回路が制御
されてい々ｂとき、前記出力ゲートを高インピーダンス
状態に切換え、前記入力ゲートの出力によって被制御回
路基板が実装されてｈるか否かを判断するように構成し
たことを特徴とする被制御回路′）ｌ装確認方式。A three-level output gate that is connected to the central processing unit, controls the opening and closing of control signals from the central processing unit, and whose output is connected to an external connection terminal; and an input gate whose input is connected to the external connection terminal. an input/output board including an input/output board, and a plurality of controlled circuit boards which are connected to the external connection terminal when inserted into the input/output board and controlled by the central processing unit, When the control circuit is being controlled, the output gate is switched to a high impedance state, and it is determined based on the output of the input gate whether or not the controlled circuit board is mounted. Controlled circuit') l installation confirmation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5915084A JPS60203054A (en) | 1984-03-27 | 1984-03-27 | Mounting confirmation of circuit to be controlled |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5915084A JPS60203054A (en) | 1984-03-27 | 1984-03-27 | Mounting confirmation of circuit to be controlled |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60203054A true JPS60203054A (en) | 1985-10-14 |
Family
ID=13105024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5915084A Pending JPS60203054A (en) | 1984-03-27 | 1984-03-27 | Mounting confirmation of circuit to be controlled |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60203054A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4945297A (en) * | 1987-05-19 | 1990-07-31 | Automobiles Peugeot | Electronic device forming a bidirectional interface for controlling a load switching power element |
| US6363137B1 (en) | 1998-04-01 | 2002-03-26 | Sharp Kabushiki Kaisha | Information terminal apparatus |
-
1984
- 1984-03-27 JP JP5915084A patent/JPS60203054A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4945297A (en) * | 1987-05-19 | 1990-07-31 | Automobiles Peugeot | Electronic device forming a bidirectional interface for controlling a load switching power element |
| US6363137B1 (en) | 1998-04-01 | 2002-03-26 | Sharp Kabushiki Kaisha | Information terminal apparatus |
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