JPS6020276A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To shorten execution time of signal processor instruction (SIGP instruction) by moving start of the next instruction executing of the microprogram computer which requests processing to a service processor to the time as early as possible. CONSTITUTION:Writing of control bits 3 and 4 of ''0''- and ''1''-system microprogram computers is possible only by self-system microprogram mu0 and mu1 through SIGP BSY bit writing signal lines 9 and 10, and they can be read only by other- system microprogram mu0 and mu1 through reading lines 11 and 12. Write/read of control bits 5, 6 and 7, 8 are executed by the service processor SVP. Interruption-cause indication registers 18 and 19 are set through interruption-indication writing signal conductors 20 and 21 from the service processor SVP, and are read by the microprogram which system requests processing to the service processor SVP.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention relates to a multiprocessor system, and in particular, the present invention relates to a multiprocessor system in which a signal processor instruction (hereinafter referred to as 5IG) is sent to a service processor.
It is called P command. ), the present invention relates to a multiprocessor system that is improved so that when a process is requested using a microprogram computer, the start time of the next instruction execution in the requested microprogram computer is brought forward.

(b) Technical Background A multiprocessor system consisting of two microprogram computers and a service processor is in practical use. In this system, 5 IGP instructions are used for information processing between two microprogram computers and these and a service processor. When using these 5 IGP instructions, it is strongly desired that any microprogram computer be able to move on to executing the next instruction within the shortest possible time from the perspective of improving processing speed.

However, in conventional multiprocessor systems, due to system configuration constraints, when a 5IGP instruction is issued from the own microprogram computer that makes up the system, the next instruction cannot be executed until the service processor completes processing. It has been a long time since there has been a demand for the development of technical means to solve this problem.

(c) Prior art and problems In a conventional multiprocessor system, means for preventing contention when two microprogram computers issue 5IGP instructions to a service processor and request the service processor to control a relative computer. 5 IGP instruction control bits called CPU BSY bits are used.

However, the CPU BSY bit is set so that when the microprogram computer uses the 5IGP instruction to request processing from the service processor, the service processor sets the CPU BSY bit on the system opposite to the system that is proceeding with the processing. It is configured.

Therefore, the microprogram computer in the system on the other side can move on to executing the next instruction at the appropriate time before the service processor's processing has finished, but the microprogram computer in the system that is proceeding with the process can wait until the service processor's processing has finished. Until then, the next command cannot be executed, and the user is forced to wait until the above-mentioned end arrives.

Purpose of the Invention The present invention was devised in view of the above-mentioned drawbacks of conventional systems, and its purpose is to enable a microprogram computer that has requested a service processor to start executing the next instruction. An object of the present invention is to provide a multiprocessor system in which the execution time of a 5IGP instruction can be shortened by moving it to an earlier time and the system performance can be improved.

g) Structure of the Invention In order to achieve this object, the system of the present invention uses two microprogram computers and a multifunctional system that uses signal processor instructions (hereinafter referred to as 5icp instructions) for information processing between these computers and a service processor. A 5IGP instruction control system in which the priority between the two microprogram computers can be written only by the microprogram of its own system, and read only by the microprogram of another system.
In a multi-processor system using the (SIGP BSY bit), each scroll saw is provided with 5 IGP instruction control bits CPU BSYO and CPU BSYI that can be read/written by the service processor and read only by its own microprogram. If the system that executes the process is the θ system when the microprogram of the computer that is given priority requests processing to the service processor using the 5IGP instruction, the CPUs of both systems
Set BSYO, and if it is l system, CPU BSY of both systems
Set I, and the CPU set at the end of the above processing.
A CPU BSY bit on/off control means that turns off the BSY bit and a microprogram that turns off the 5I for the 0 system.
When a microprogram requests the above service processor to perform a process when executing a GP instruction, refer to CPU BSYO.When a microprogram requests the above service processor to perform a process when executing a 5IGP instruction for system 1, refer to CPU B'SYI. If the reference bit is on, the service processor is not requested to process the 5 IGP instruction, and if the reference focus is off, the service processor is requested to process the 5 IGP instruction. , means for returning a response signal to a system that has issued a processing request from the service processor to the service processor prior to the start of processing by the service processor, and causing the system that responds to the response signal to execute the next instruction. It is constructed with means.

(F) Embodiments of the Invention The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a multiprocessor system implementing the invention. In this figure, the circuit to the left of the dashed-dotted line represents a 0'' system microprogram computer, and the circuit to the right thereof represents an l'' system microprogram computer. and,
μ0 is a “0” type microprogram, μm is “1”
This is a system microprogram. SVP is the number-vis processor. 1 is a “0” type control register, and 2 is a “0” type control register.
1" system control register. Control bits 3 and 4 in control register 1.2 are 5 of the 5fGP instruction control bits.
IGP BSY bit, control bits 5.6 and 7
, 8 is CPU BSY of 5 IGP instruction control focus
O bit and CPU BSYI bit. Control bits 3 and 4 are written to the own microprogram μ via the 5IGP BSY focus write signal lines 9 and 10, respectively.
02 μm, while their readout is only possible by other microprograms μm, μ0 via the 5IGP BSY bit read lines 11.12. Also, control bits 5, 7 and 6, 8
can be written/read by the service processor SvP via CPU BSY bit write signal line 13.14 and CPU BSY bit read signal line 15.16, respectively, while reading control bits 5, 7 and 6.8 is CPtJ BSY bit read signal line 17
．． This is done only by the own microprogram via 18.

The 5IGP BSY bit is used as a means to prevent conflicts between 5IGP instructions issued to each other or to itself between two microprogram computers, and the CPU BSY bits 5°7, 6, and 8 are 2 This means is used for conflict and control processing when one microprogram computer issues 5IGP instructions to the service processor SVP and requests the service processor SvP to control the other computer.

18 and 19 are "0" series and "1" series interrupt cause display registers, respectively. These registers are 8-bit registers, and are input via interrupt cause display write signal lines 20 and 21 from the service processor svp. cent,
Also, via the interrupt cause display readout signal lines 22 and 23,
It is configured to be read by the microprogram of the system that issued the processing request to the service processor SvP.

Note that the 5 IGP commands in the system of the present invention are the same as the conventional ones: sense order (sub-instruction, the same applies hereinafter), external call order, emergency signal order, start order, and stop order. stop)
order, restart order, initial program reset
reset ) order, program reset (prog
rao+reset) order, stop-situation memory (s
top and 5tore 5tatus) order, initial microprogram load (initial m
icroprogram 1oad) order, initial C
PU reset (initial CPU reset
) order, and CPU reset (CPU reset
) consists of orders.

Next, the features realized in the system of the present invention having the above-described configuration will be explained using the flowcharts shown in FIGS. 2 and 3.

Assume that the multiprocessor system described above is in an operating state and microprogram processing as shown in FIG. 2 is started (step Sl).

Then, it is determined in step S whether the issued 5IGP command is for the own system or for another system.
It is done in 2. In this flowchart, for convenience, the own system is assumed to be the 0'' system, and the other system is assumed to be the ``1'' system.

Then, if the determination is affirmative (Y), that is, the 5 IGP command has been issued to the own system, it is determined in step S3 whether or not CPU BSYO is turned on. If CPU BSYO = 1, the condition code CC = 2, that is, it is displayed that it is in use, and the process ends, but if CPU BSYO - 0, the order type is determined (step s4) and the order is 5t
art, restart, 5ense, or emer
If the order is a gency call, its own microprogram starts its processing (step S5), and if the order is invalid,
In step s6, condition code CC is CC=1,
In other words, the order is considered invalid and the processing is terminated.

Further, if the determination in step S2 indicates that it is a different system, the process advances to step S7, and if it is shown that cPUBSY1=1, CC=2 and the process ends there, as in step S2.

If the determination in step S7 indicates that CPU BSY1=0, the order type determination in step s8 is performed, and the order is determined to be 3ense+externa.
If the order is ``l_call'' or an emergency call, the microprogram of another system enters its processing (step S9), and if the order is invalid, the process enters step s6 in the same way as the own system's processing.

In this manner, when orders for the service processor are generated from both systems, the priority is determined using the 5IGP B·sY Bift in step 310. In this way, the system of microprograms given priority will receive a console request (CNS).
L_REQ) is turned on and interrupts the service processor SVP (step 511). On the other hand, the microprogram is executed in step S12 if the service processor SvP accepts the request within a predetermined time or if a service processor error (SVP ER=1) occurs. Determine whether it occurs.

During this determination, the service processor SvP
(It may time out or SVP E
When RI is reached, the process advances to step S13, where the condition code CC is set to CG=1, indicating that the process cannot be continued, and the process ends.

On the other hand, there is an acceptance by the service processor SVP within a predetermined time, that is, ACPT=1 (this means that the service processor SVP in the service processor processing flow in FIG.
This corresponds to ACPT-1 in step 330 where an interrupt is made to vP, the interrupt is accepted, and an indication thereof is displayed. ), the system that has been allowed to process up to this flowchart step, that is, the system that has requested the service processor to process, for example, its own microprogram, registers the interrupt cause display register (CNSLC1?) in step 314.
) 18 is 0 or not, and if it is 0, loop L1 is repeated.

On the other hand, as described above, the service processor svp that has accepted the interrupt sets ACPT=1 in step S30 and checks whether the system on which the post-processing is executed is the "0'system" or the "1" system. Judge by.

If the determination indicates that it is “0”, step 53
2T: Determine whether CPU BSYO is 1 or o. If it is 1, set CN5LCR=IC and interrupt the microprogram. On the microprogram side, as described above, in step 314, CN5
Since it is determined whether LCR=0 or not, when an interrupt to the microprogram occurs as described above,
The flow of FIG. 2 proceeds to step S15, where the determination is affirmative (Y), and the step S167-CC=2°5IGP BSY=0 is entered, and the flow of FIG. 2 ends.

Conversely, if CPU BSYO=O, in step S33 the CPU BSYO of both systems is set to 1, and then in step 334 the CPU BSYO is sent to CN5LCR-1B.

Then, in step S35, command execution begins, and after the command is finished (Y in step S36), the CPUs of both systems
BSYO is set to 0 (step 537) and the process ends.

Since CN5LCR=IB is set in step S34 while such processing is proceeding, the determination on the microprogram side as to whether or not CN5LCR-○ is negative (≠0), and the determination in step 515 is negative (≠0). Also, the result is negative (N), and the process proceeds to step 317.

Since the determination in step 517 is affirmative, in step 31B, CC-0<order accepted), 5IG
By setting P BSY = 0, the process can be ended and the next instruction can be executed.

Therefore, as is clear from the above, according to the present invention, even if the system that requests processing to the service processor SvP is the own system, the next instruction can be processed without waiting for the processing of the service processor SvP to be completed. can enter. As a result, the execution time of the 51cp instruction is reduced, resulting in improved system performance.

Moreover, such effects can also be obtained in other systems.

In this case, the difference from the own system is that the determination in step s31 is "1" system, and the determination in step S3B is CPU
This is done for BSYI and sent to both systems (7) CPU BSY1=1 in step S39. Further, steps S41 to s43 in FIG. 3 correspond to steps 335 to s37.

In addition, in the above explanation, the “0” system was considered as the own system, but when the “1” system becomes the own system, the “0” system becomes the other system, and accordingly, the self system that appeared in various places in the above explanation The system λ and Qin are interchangeable.

(G) Effects of the Invention As described above, according to the present invention, ■ When a service processor is requested to execute a 5IGF instruction, even if the executing system is its own system, the service processor Processing of the next instruction can be started without waiting for the completion of processing, 1) Therefore, the execution time of the 5 IGP instruction is shortened, and 2) system performance is improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a multiprocessor system implementing the present invention, FIG. 2 is a diagram showing a processing flowchart of a microprogram used to explain the operation of the system, and FIG.
The figure is a diagram showing a processing flowchart of the service processor used to explain the operation of the system of FIG. 1. In the figure, 1 and 2 are control registers, μ0 is a 6o" series microprogram, stone 1 is a "1" series microprogram,
svP is service processor, 3゜4 is 5IGP BS
Y bits, 5 and 6 are CPU S Y O bits, 7,
8 is the CPU BSY1 bit, and 18.19 is an interrupt cause display register. -414- Figure 3

Claims (1)

[Claims] A multiprocessor system that uses signal processor instructions (hereinafter referred to as 5IGP instructions) for information processing between two microprogram computers and a service processor, in which the priority between the two microprogram computers is determined by In a multiprocessor system using a 5IGP instruction control bit (SIGP BSY bit) that can only be written by a microprogram in its own system and read only by a microprogram in another system, reading/writing can be performed by the above service processor. A control register in which each scroll saw is equipped with 5 ICP instruction control bits CPU BSYO and CPU BSYI that can be read only by its own micro program, and a micro program of a micro program computer given priority is 5 IG.
When a process is requested to the above service processor using the P instruction, if the system that executes the process is the 0 system, the CP of both systems
Cent U BSYO, if it is 1 system, CPU B of both systems
Cent SYI and CP set at the end of the above process
A CPU BSY bit on/off control means for turning off the U BSY focus, a CPU BSYO when the microprogram requests the service processor to execute the 5IGP instruction for the 0 system, and a 5rcp instruction for the 1 system. When requesting processing from the above service processor in the execution of If so, means for requesting the service processor to process the 5IGP command, and means for returning a response signal to the system that issued the processing request from the service processor to the service processor prior to the start of processing by the service processor. and a means for causing a system that responds to the response signal to execute the next instruction.