JPS60200288A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display device used when displaying images such as characters from a so-called microphone-enabled computer on, for example, an NT8C monitor receiver.

Background technology and its problems M, t! In fNTac type monitor reception m's,
The 1IIIi surface is formed in an interlaced manner.

When using such a monitor receiver to display images such as characters from a so-called microcomputer, the output video random access memory (V-RAM) of the micro:yy computer is read out using a predetermined tie. In synchronization with this timing, an NTfiC synchronization signal generation circuit is driven to generate horizontal (H) and vertical (V) synchronization signals.

Here, the above-mentioned V-RAM has only one field,
When the same image is displayed in the first and second fields of interlacing, that is, when two scanning lines form one pixel, the generation of the above synchronization signal is caused by the tinging of the 11th and 2nd fields. Either is fine, V −1(,
The interlace may be reset by arbitrary tying of every other signal (vertical synchronization signal) related to the end of reading of one field from the read control circuits A and M.

In response to this, there was a demand for increasing the accuracy of the image from the microcomputer mentioned above and displaying the amount of 1 mg per stroke fIw. 70lh@- has V-RAM
From then on, a pattern corresponding to interlacing is performed, and it is necessary to generate a synchronization signal based on the 111% second field. Conventionally, synchronization signals have been generated using the following devices.

In FIG. 1, video data to be displayed such as characters is supplied from the central processing circuit (CPU) [1) of the microphone 1 computer to the V-RAM+21 and written to a desired address. This V-RAM (23) is successively outputted by an address signal generated from a control circuit (3) in response to, for example, NTSC interlacing, and the sum is taken out from an output terminal (4).

Further, a signal related to the end of reading one field from the control circuit (3) and a bit signal corresponding to the switching of the first and second fields in the read address signal are supplied to the gate circuit (5). For example, a signal related to the end of the continuation of the second field is taken out. This signal is supplied, for example, to a reset terminal of a NTSC synchronization signal generation circuit 463.

As a result, a duty and horizontal synchronization signal of the NTSC system is generated and taken out to the output terminal (7). Furthermore, this horizontal synchronization signal is supplied to a phase transverse waveform generator (8), and the detected output is supplied to a variable frequency oscillator (VCO) [IGK] through a low-pass filter (9). A signal with a frequency corresponding to the pixel clock of the above-mentioned V-RAM (2) is generated from this vCOαa, and this signal is sent to the control circuit 13.
) K is supplied. Then, this control circuit (3) divides the signal to 1 according to the above-mentioned NTSC system interlacing.
An address signal is formed corresponding to the on-screen position of the frame. Furthermore, a signal corresponding to the horizontal synchronizing signal is formed in the control circuit (3)K, and this signal is supplied to the phase detector (8)K, so that a so-called phase lock is applied.

In this manner, images such as characters are continuously displayed and a synchronization signal is generated. In this case, the synchronization signal generation circuit is reset at the timing of the end of the second field (start of g, x field) from the control circuit, so the synchronization signal generation circuit is 1% of the synchronization signal is matched with the second field, and a good display can be obtained in row 5.

However, in this device f, the synchronization signal generation circuit i63 extracts the tie at the end of the s #i 2 field.
Extraction circuit (game) to reset 1! ! l road (5
)) is required. In addition, the control circuit (3) requires a special circuit that generates addresses for one frame, and since this control circuit (3) is used as a reference, the accuracy of the operation must be extremely high. There were other problems.

OBJECTS OF THE INVENTION In view of these points, the present invention is intended to provide a good display with a simple configuration.

SUMMARY OF THE INVENTION The present invention provides a display device for displaying images from a memory on an interlaced monitor receiver, in which a circuit for controlling successive loading of the memory is separated from a circuit for generating an interlaced synchronization signal. This is a display device that waits for resetting with a vertical synchronization signal, and according to this, it is possible to perform a good display with a simple configuration.

In the embodiment shown in FIG. 2, the synchronization signal generation circuit (6) is free-running, and the vertical synchronization signal from this generation circuit (61) is transmitted to the control circuit (61).
3) is supplied to the reset terminal. Therefore, this control circuit (3) is set to KIJ for each vertical synchronizing signal, and an address signal corresponding to the position on the screen of one field is formed. The signal corresponding to the first or second field of the interlace from the second button support signal generation circuit (6) is
V-RAM (pitch corresponding to switching of the first and second fields in the successive address signal supplied to 21) K is inserted.

Therefore, in this device, the control circuit (3) is driven in synchronization with the synchronization signal from the generation circuit (6), and the field address signal is generated from the control circuit (3). By switching the memory area of V-RAM+2J with the field switching signal from , interlaces matching the 11th and 2nd fields of the synchronization signal are successively output.

Claims (1)

[Claims] In a display device configured to display video data from a mesori on an interlaced monitor receiver, the circuit that controls reading of the memory is reset with a vertical synchronization signal from the circuit that generates the interlaced synchronization signal. A display device characterized by: