JPS60194810A - Frequency mixing circuit - Google Patents

Frequency mixing circuit

Info

Publication number
JPS60194810A
JPS60194810A JP59051446A JP5144684A JPS60194810A JP S60194810 A JPS60194810 A JP S60194810A JP 59051446 A JP59051446 A JP 59051446A JP 5144684 A JP5144684 A JP 5144684A JP S60194810 A JPS60194810 A JP S60194810A
Authority
JP
Japan
Prior art keywords
transistors
common
transistor
resistor
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59051446A
Other languages
Japanese (ja)
Other versions
JPH0152924B2 (en
Inventor
Akira Usui
晶 臼井
Kazuhiko Kubo
一彦 久保
Hiroyuki Nagai
裕之 永井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59051446A priority Critical patent/JPS60194810A/en
Publication of JPS60194810A publication Critical patent/JPS60194810A/en
Publication of JPH0152924B2 publication Critical patent/JPH0152924B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1433Balanced arrangements with transistors using bipolar transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1458Double balanced arrangements, i.e. where both input signals are differential
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041Functional aspects of demodulators
    • H03D2200/0084Lowering the supply voltage and saving power
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041Functional aspects of demodulators
    • H03D2200/0088Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products

Abstract

PURPOSE:To obtain a means improving the conversion gain and a ternary distortion at a constant current value by constituting the circuit that a current balance of double balance form is unbalanced so as to supply much power to an output terminal. CONSTITUTION:A resistor 17 is connected between a common collector of transistors (TR) 8, 10 of a double balance type mixing circuit and a power terminal and an intermediate frequency output is applied to an output terminal C from the common collector of the TRs 8, 10. A current of 1.7mA is obtained at the common collector of the TRs 8, 10 when a current value I of a constant current source 7 is 3mA, and improvement of 66dB of the ternary distortion and 6dB of the conversion gain is attained in comparison with a conventional circuit.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、テレビジョンチューナー回路や0ATVコン
バーター、衛星放送受信機等に用いることのできる、高
周波領域における集積回路を用いた周波数混合回路に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a frequency mixing circuit using an integrated circuit in the high frequency range, which can be used in television tuner circuits, 0ATV converters, satellite broadcast receivers, etc. .

従来例の構成とその問題点 従来の周波数混合回路の一例を第1図に示す。Conventional configuration and its problems An example of a conventional frequency mixing circuit is shown in FIG.

図の端子Aは局部発振器信号、端子Bは高周波信°号の
おのおの入力端子、端子Cは中間周波数信号の出力端子
である。端子Bよシ与えられた高周波信号には基準電位
v1 を与えておき、これをトランジスタ1のベースに
供給し、さらに抵抗2を通してトランジスタ30ベース
にも加える。トランジスタ3のベースは、4によって高
周波成分が軽減され直流電位が加れられることになる。
Terminal A in the figure is a local oscillator signal, terminal B is an input terminal for a high frequency signal, and terminal C is an output terminal for an intermediate frequency signal. A reference potential v1 is applied to the high frequency signal applied to the terminal B, which is supplied to the base of the transistor 1, and further applied to the base of the transistor 30 through the resistor 2. The base of the transistor 3 has a high frequency component reduced by the transistor 4, and a DC potential is applied to the base of the transistor 3.

トランジスタ1,3のエミッタは抵抗5,6を介して、
互いに結合し、その結合点から定電流源7が接続されて
いる。高周波信号はそれぞれトランジスタ1.3にて増
幅される。トランジスタ1,3のコレクタは、それぞれ
トランジスタ8,9の共通エミッタとトランジスタ10
.11の共通エミッタに接続される。トランジスタ、8
,9,10.11は、トランジスタ8,11のベース間
、トランジスタ9,1Qのベース間がそれぞれ接続され
ている0 トランジスタ8.11の共通ベースには、容量12を介
して端子Aより局部発振信号が加えられるとともに、抵
抗13を通して基準電位源14の基準電位v2が与えら
れる。またトランジスタ9゜1oの共通ベースは抵抗1
5を介して基準電位源14に接続されるとともに、容量
16を介して接地されている。トランジスタ8,10の
共通コレクタは電源端子に接続される。またトランジス
タ9.11の共通コレクタは抵抗17を介して電源端子
に接続されている。
The emitters of transistors 1 and 3 are connected via resistors 5 and 6,
They are coupled to each other, and a constant current source 7 is connected from the coupling point. The high frequency signals are each amplified by transistors 1.3. The collectors of transistors 1 and 3 are connected to the common emitters of transistors 8 and 9 and transistor 10, respectively.
.. 11 common emitters. transistor, 8
, 9, 10.11 are connected between the bases of transistors 8 and 11, and between the bases of transistors 9 and 1Q. Local oscillation is connected to the common base of transistors 8.11 from terminal A via capacitor 12. At the same time as the signal is applied, the reference potential v2 of the reference potential source 14 is applied through the resistor 13. Also, the common base of transistor 9゜1o is resistor 1
It is connected to a reference potential source 14 via a capacitor 5 and grounded via a capacitor 16. The common collectors of transistors 8 and 10 are connected to a power supply terminal. Further, the common collectors of the transistors 9 and 11 are connected to a power supply terminal via a resistor 17.

このようにしてダブルバランス型の周波数混合回路を構
成し、トランジスタ11と9の共通コレクタより周波数
混合信号を出力端子Cに供給しているものである。
In this way, a double-balanced frequency mixing circuit is constructed, and a frequency mixing signal is supplied to the output terminal C from the common collector of the transistors 11 and 9.

ところで第1図の構成でトランジスタ8,11の共通ベ
ースの電位をVD、vEl トランジスタ9゜1oの共
通ベースの電位をVF1 トランジスタ1のベース電位
をvGl トランジスタ3のベース電位をvHとして各
点の直流電位を考えてみると、抵抗2による電位降下で
vG>vHであり、局部発振信号が加わるためVD、v
E〉VFとなる。これは、容量16が集積回路内の容量
として、せいぜい数pF Lか構成できないために高周
波成分の減衰が十分確保できないために生ずる現象であ
る。
By the way, in the configuration shown in Fig. 1, the potential of the common base of transistors 8 and 11 is VD, vEl, the potential of the common base of transistor 9゜1o is VF1, the base potential of transistor 1 is vGl, and the base potential of transistor 3 is vH, and the DC current at each point is Considering the potential drop due to resistor 2, vG>vH, and since the local oscillation signal is added, VD, v
E〉VF. This is a phenomenon that occurs because the capacitor 16 cannot be configured as a capacitor of several pFL at most in an integrated circuit, and therefore sufficient attenuation of high frequency components cannot be ensured.

VG )VH,VD、VE>VF (D ような電位差
ヲ生じた場合には、トランジスタ8,10の共通コレク
タに流れ込む電流は、トランジスタ9,11の共通コレ
クタに流れる電流よシ犬きくなシ、いまたとえば、抵抗
13.15として3.3にΩ、抵抗5.6として100
Ω、抵抗2に6.6にΩのものを用い、電源電圧Vcc
=12Vのときに定電流源7にI = 3 mA流しだ
ときには、トランジスタ8゜10の共通コレクタには1
.7rnA、)ランジスタ9.11の共通コレクタには
1.3mAという値がおのおの得られた。
VG) VH, VD, VE>VF (D) If such a potential difference occurs, the current flowing into the common collector of transistors 8 and 10 will be much smaller than the current flowing into the common collector of transistors 9 and 11. For example, if the resistance is 13.15, it will be 3.3Ω, and if the resistance is 5.6, it will be 100Ω.
Ω, resistor 2 and 6.6 Ω are used, and the power supply voltage Vcc
When I = 3 mA flows into constant current source 7 when voltage = 12 V, 1 is applied to the common collector of transistors 8゜10.
.. 7rnA,) A value of 1.3 mA was obtained in the common collector of transistor 9.11.

このため、出力端子Cには負荷抵抗17と1.3mAで
得られる変換利得、3次歪しか確保できず、回路が完全
にバランスして1.5mA流したときに比べて、変換利
得で3dB、3次歪(インターセプトポイント)でも3
dB劣化するという欠点があった。
Therefore, the output terminal C can only secure the conversion gain and third-order distortion obtained with the load resistor 17 and 1.3 mA, and the conversion gain is 3 dB compared to when the circuit is perfectly balanced and 1.5 mA flows. , even the third-order distortion (intercept point) is 3.
It had the disadvantage of dB deterioration.

発明の目的 本発明は定電源源の値を同一にした場合に、変換利得、
3.次歪を改善する手段を提供することを目的とする。
Purpose of the Invention The present invention provides conversion gain,
3. The purpose of this invention is to provide a means for improving second-order distortion.

発明の構成 本発明による周波数混合回路は、高周波入力信号を2つ
に分け、そのうちの一方をダブルバランス型回路を構成
する2つの高周波増幅トランジスタの一方のベースに供
給し、他方を第1の抵抗を介して他方の高周波増幅トラ
ンジスタのベースに供給し、この他方の高周波増幅トラ
ンジスタのベースを第1の容量を介して接地するととも
に、上記ダブルバランス型回路を構成する第1〜第4の
トランジスタのうち第1.第2のトランジスタのエミッ
タを共通に接続し、第3.第4のトランジスタのエミッ
タも共通に接続し、第1.第2のトランジスタの共通エ
ミッタを上記一方の高周波増幅トランジスタのコレクタ
に、第3.第4のトランジスタの共通エミッタを上記他
方の高周波増幅トランジスタのコレクタにおのおの接続
し、局部発振信号を第1.第4のトランジスタの共通べ
−1− 至詩に供給し、この共通ベースを第2の抵抗を介して基
準電位源に接続し、第2.第3のトランジスタの共通ベ
ースを第2の容量を介して接地するとともに第3の抵抗
を介して上記基準電位源に接続し、かつ第2.第4のト
ランジスタのコレクタを共通に接続して電源端子に接続
し、第1.第3のトランジスタのコレクタを共通に接続
して負荷抵抗を介して上記電源端子に接続し、この負荷
抵抗と共通コレクタの接続点より中間周波出力信号を得
るようにしたものであり、より大きいパワーの中間周波
出力信号を得ることができ、変換利得、3次歪ともに大
幅な改善がはかれるものである。
Structure of the Invention The frequency mixing circuit according to the present invention divides a high frequency input signal into two, supplies one of them to the base of two high frequency amplification transistors forming a double-balanced circuit, and supplies the other to the base of the first resistor. is supplied to the base of the other high-frequency amplification transistor through the first capacitor, and the base of the other high-frequency amplification transistor is grounded through the first capacitor. The first of these. The emitters of the second transistors are connected in common, and the third . The emitters of the fourth transistor are also connected in common, and the emitters of the fourth transistor are also connected in common. The common emitter of the second transistor is connected to the collector of one of the high frequency amplification transistors, and the third. The common emitter of the fourth transistor is connected to the collector of the other high frequency amplification transistor, respectively, and the local oscillation signal is transmitted to the first... A common base of a fourth transistor is connected to a reference potential source through a second resistor, and a common base of a fourth transistor is connected to a reference potential source through a second resistor. The common bases of the third transistors are grounded via a second capacitor and connected to the reference potential source via a third resistor, and the common bases of the third transistors are connected to the reference potential source via a third resistor. The collectors of the fourth transistors are connected in common and connected to the power supply terminal, and the collectors of the fourth transistors are connected in common to the power supply terminal. The collectors of the third transistors are connected in common and connected to the above power supply terminal via a load resistor, and an intermediate frequency output signal is obtained from the connection point between the load resistor and the common collector, which provides greater power. It is possible to obtain an intermediate frequency output signal of 1,000,000, and significantly improve both conversion gain and third-order distortion.

実施例の説明 本発明の一実施例の構成を第2図に示す。Description of examples The configuration of one embodiment of the present invention is shown in FIG.

図において17の抵抗を挿入した位置以外は第1図と同
等構成になっているので、重複する説明の部分は省略す
る。4上記抵抗17はトランジスタ8.10の共通コレ
クタと電源端子の間に接続されており、中間周波数出力
はトランジスタ8,1゜の共通コレクタより出力端子C
に供給されるものである。トランジスタ8,100共通
コレクタには第1図にて説明したように、定電流源7の
電流値工として3mAのとき、1.7mAが得られ、第
1図の例に比べて変換利得で6dB、3次歪(インター
セプトポイント)でもedBの改善が得られた。これは
、回路を完全にバランスさせたとき(1,5mA流した
とき)に比べても3dBの改善が得られるもので、集積
回路等で、電流をできるだけ制限する必要のあるときに
は特に有効な手段であるといえる。
In the figure, the configuration is the same as that in FIG. 1 except for the position where the resistor 17 is inserted, so redundant explanations will be omitted. 4 The resistor 17 is connected between the common collector of the transistors 8 and 10 and the power supply terminal, and the intermediate frequency output is connected from the common collector of the transistors 8 and 1 to the output terminal C.
It is supplied to As explained in Fig. 1, the common collector of the transistors 8 and 100 obtains 1.7 mA when the current value of the constant current source 7 is 3 mA, and the conversion gain is 6 dB compared to the example shown in Fig. 1. , an improvement in edB was also obtained for third-order distortion (intercept point). This is an improvement of 3 dB compared to when the circuit is completely balanced (when 1.5 mA flows), and is an especially effective method when it is necessary to limit the current as much as possible in integrated circuits, etc. You can say that.

発明の効果 このように、本発明によれば、ダブルバランス型の電流
バランスをアンバランスにして出力端子に多くのパワー
を供給できる構成にすることにより、定電流値において
変換利得、3次歪に対して有利な条件を確保できるもの
である。
Effects of the Invention As described above, according to the present invention, by making the current balance of the double-balanced type unbalanced so that more power can be supplied to the output terminal, the conversion gain and third-order distortion can be reduced at a constant current value. This means that favorable conditions can be secured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例における周波数混合回路の回路図、第2
図は本発明の一実施例における周波数混合回路の回路図
である。 A・・・・・・局部発振信号入力端子、B・・印・高周
波信号入力端子、C・・・・・・周波数混合出力端子、
1,3゜8.9,10.11・・・・・・ダブルバラン
ス型混合回路を構成するトランジスタ、2,5,6,1
3゜15.1γ・・・・・・ダブルバランス型混合回路
を構成する抵抗、4,16・・・・・・接地容量、7・
・・・・定電流源、14・・・・・・基準電位源。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
Figure 1 is a circuit diagram of a conventional frequency mixing circuit;
The figure is a circuit diagram of a frequency mixing circuit in one embodiment of the present invention. A: Local oscillation signal input terminal, B: High frequency signal input terminal, C: Frequency mixing output terminal,
1, 3゜8.9, 10.11... Transistor constituting a double balanced mixed circuit, 2, 5, 6, 1
3゜15.1γ...Resistance configuring the double-balanced mixed circuit, 4,16...Grounding capacitance, 7.
... Constant current source, 14... Reference potential source. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

【特許請求の範囲】[Claims] 高周波入力信号を2つに分け、そのうちの一方をダブル
バランス型回路を構成する2つの高周波増幅トランジス
タの一方のベースに供給し、他方を第1の抵抗を介して
他方の高周波増幅トランジスタのベースに供給し、この
他方の高周波増幅トランジスタのベースを第1の容量を
介して接地し、上記ダブルバランス型回路を構成する第
1〜第4のトランジスタのうち第1.第2のトランジス
タのエミッタ、第3.第4のトランジスタのエミッタを
それぞれ共通に接続し、第1.第2のトランジスタの共
通エミッタを上記一方の高周波増幅トランジスタのコレ
クタに、第3.第4のトランジスタの共通エミッタを上
記他方の高周波増幅トランジスタのコレクタにおのおの
接続し、局部発振信号を上記第1.第4のトランジスタ
の共通ベースに供給し、この共通ベースを第2の抵抗を
介して基準電位源に接続し、第2.第3のトランジスタ
の共通ベースを第2の容量を介して接地するとともに第
3の抵抗を介して上記基準電位源に接続し、上記第2.
第4のトランジスタのコレクタを共通に接続して電源端
子に、第1.第3のトランジスタのコレクタを共通に接
続して負荷抵抗を介して上記電源端子におのおの接続し
、この負荷抵抗と共通コレクタの接続点より中間周波出
力信号を得るようにしたことを特徴とする周波数混合回
路0
The high-frequency input signal is divided into two parts, one of which is supplied to the base of two high-frequency amplification transistors forming a double-balanced circuit, and the other is supplied to the base of the other high-frequency amplification transistor via the first resistor. and the base of the other high-frequency amplification transistor is grounded via the first capacitor, and the first to fourth transistors constituting the double-balanced circuit are connected to the base of the other high-frequency amplification transistor. the emitter of the second transistor, the third . The emitters of the fourth transistors are connected in common, and the emitters of the first and second transistors are connected in common. The common emitter of the second transistor is connected to the collector of one of the high frequency amplification transistors, and the third. The common emitter of the fourth transistor is connected to the collector of the other high frequency amplification transistor, respectively, and the local oscillation signal is transmitted to the first... a common base of a fourth transistor, the common base being connected to a reference potential source via a second resistor; The common bases of the third transistors are grounded via a second capacitor and connected to the reference potential source via a third resistor, and the common bases of the third transistors are grounded via a second capacitor and connected to the reference potential source via a third resistor.
The collectors of the fourth transistors are commonly connected to the power supply terminal. A frequency characterized in that the collectors of the third transistors are connected in common and each is connected to the power supply terminal through a load resistor, and an intermediate frequency output signal is obtained from a connection point between the load resistor and the common collector. Mixed circuit 0
JP59051446A 1984-03-16 1984-03-16 Frequency mixing circuit Granted JPS60194810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59051446A JPS60194810A (en) 1984-03-16 1984-03-16 Frequency mixing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59051446A JPS60194810A (en) 1984-03-16 1984-03-16 Frequency mixing circuit

Publications (2)

Publication Number Publication Date
JPS60194810A true JPS60194810A (en) 1985-10-03
JPH0152924B2 JPH0152924B2 (en) 1989-11-10

Family

ID=12887155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59051446A Granted JPS60194810A (en) 1984-03-16 1984-03-16 Frequency mixing circuit

Country Status (1)

Country Link
JP (1) JPS60194810A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0391305A (en) * 1989-09-04 1991-04-16 Hitachi Ltd Frequency converter and tuner circuit using the same
EP0584870A1 (en) * 1992-08-26 1994-03-02 Koninklijke Philips Electronics N.V. Transformer circuit, double-balanced mixer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0391305A (en) * 1989-09-04 1991-04-16 Hitachi Ltd Frequency converter and tuner circuit using the same
EP0584870A1 (en) * 1992-08-26 1994-03-02 Koninklijke Philips Electronics N.V. Transformer circuit, double-balanced mixer
FR2695272A1 (en) * 1992-08-26 1994-03-04 Philips Composants Mixer circuit for radio or television signals.

Also Published As

Publication number Publication date
JPH0152924B2 (en) 1989-11-10

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