JPS60194490A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Technical Field 1] This invention is directed to displaying characters and patterns such as 1-Yarakuta in color on a display screen. The present invention relates to a display controller capable of processing various image data. [Prior Art] In recent video game consoles and other graphics display devices, a display roller capable of displaying moving images and still images together is often used. However, still image display in conventional display controllers is performed by suitably combining several preset patterns. -, but there is a problem that it is not possible to draw 11 static cars of 2M in this unity. J
, /:, Graphic display smell

When drawing a static image, a process is often performed to set a rectangular area on the display screen and fill in this area, but in conventional display controllers,
(The size of the preset 11〆1 nokta pattern is about 8 x 8 dots [-, so above]) The rear settings are only 8 dots 1 to 1 C horizontally and vertically. There was a drawback that it was not possible to do this, and it ended up being rough.Also, the setting of the fill 1 notch rear became rough,
The static image that is drawn becomes rough, and when using a conventional display controller like this, the static image becomes rough.
The drawback was that the expressive ability of F-pictures was not sufficient. Furthermore, when performing the sample crushing process described in 1), there was a vacancy that would place a heavy burden on software processing on the C1) IJ side, which controls the display component t-+-. [Object of the invention] This invention is based on the above-mentioned circumstances! Since it has been updated, its purpose can be summarized as (1, fill 1 - rear settings can be finely tuned, and the CPU
Side rough 1 to treatment 0j14 1. -, < 1 generation reduction l ↓ It is far enough to provide 1 - 1000 yen for 100 yen. [Features of the invention ff+! [In order to achieve the first goal, this invention is based on the static 11 car data "Rear Door" in which the 7J color code that specifies the color for each drive 1 on the still rain is stored. , an image data storage circuit that displays a still image on the display surface 1 based on each color code in this still image data area, and a color code transferred from the outside. When the color-1-code in the fill-in register (2) can be transferred to the image data area of the image data area, the transfer destination 1-1 is determined by the range based on the coordinates on the image 11'. X-5) - A range storage means and a transfer range storage means which sequentially converts the transfer range stored in the storage position to the storage position of each color code in the still image data area. Creates color code position data, and sequentially transfers the color code in the color register to the storage location corresponding to the color code position data. The feature is that it is equipped with a means for transferring data. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. Fig. 1 shows a schematic configuration of an embodiment of the invention. is dip 1 noi 1 nt "1-la" (hereinafter abbreviated as \lDP),
Based on the image data in the VRAM (video RAM) 2), moving images and still images are displayed on the R1 display device 3.
? +). J-k, VDPll, 1: Various types supplied from CPU (central processing unit) 4] 1 for cloak and image data
It is necessary to rewrite the contents of VRAM2 or transfer part of the contents of \/RΔM2 to the outside for each 1L. 5 is Cr tl , 1ζ・
There is a memory in which the progera 11 to be used and each inserted image data are stored. Next, regarding the name components of VDPl (explanation), image data processing circuit 10 LL, CR'-r corresponding to the screen scanning speed of display 1 and mouth 13, \/RA
Still image data in M2, 1. 1 and 1-)k",
The same i! required for scanning the screen to the CR display device 3. l i1
i 53 SY N C is output. In this case, Shizuka 11
Image data 31. and video T-Y specify the color for the drive 1 of the display image 1-, respectively.
The image-1 data processing circuit 10 is composed of 2, 4 or (1-bit data).
．． The color palette 12 reads out the color code corresponding to the color code 7 and outputs it to the color code 1-12.
It is supplied to the RT display H interval 3. 1 Also, the image data processing circuit 10 (from the CP IJ 4 to the interface 13
Both 1ψ-f-ta supplied via
2, and \/F<
When accessing 8M2 (at the time of writing, J: and reading), the signal S1 is supplied to the command processing circuit 15 to know that it is being accessed.
]. :]? command processing circuit CP 1. Based on various commands supplied from J4 via interface 13, predetermined procedures 41 are executed in advance.
Yes, rewrite static data in VRAM2)
This is a circuit that transfers both static and I-data to the outside. When the command processing circuit 15 is supplied with the signal S1 from the image data processing circuit 10, access to the RAM 2 is prohibited. Here, the still image display according to this embodiment will be explained. This fruit/+l! In example i, a plurality of still image display nodes are set (13), and roughly divided into 8×8 or F3 In the pattern mode, you can individually specify the colors for all the drums 1 to 1 that make up both sides] and in the map mode. In this case, Pagoon ■E-
181. is almost the same as the conventional disb 1 no 1 nt 1-1-ra processing, so the explanation thereof will be omitted. ,,Dra 1 to 7
We will only explain the Tsupu mode. In this example, the 4 scale notes GIV, GV, GVI, and G are set to 'A'.
) Vl, here, the correspondence between the still image data in VRAM2 and the display position in each mode 1-1) Like, 256
The screen configuration is as follows: rear 2
It is stored in a. The color code in the G IV [- code is composed of 4 bits, and this color code is stored in the static data area 2a in the order shown in FIG. (2 for each address). In this C, + IV mode, ta color -1- code is 4
Since it is a bit, one color (up to three colors can be specified) per dot.The size of the still image data 9-c] rear 2a is reduced to 2/1576 bytes as shown in the figure. The first area 2C in the V RAM 2 is an area where various data necessary for video display can be stored, and the main area 2b is a spare area i'' (in this case, spare area 21) which is not normally used. υ1 is assigned to the contiguous address of the image data area 2a, and the
τ" There is a J: Una・)C that can store the color code for displaying 11 cars. q) G V T, Need This G V T-do is 51
The screen is composed of 2 x 192 dots, and one of all dots is static 1 as in the G IV mode.
1-stroke data] is stored in the rear 2a. Moreover, the color code 1J in the GV earth card is composed of 2 bits, and this color code is 4117! Each I is stored. In addition, the content of still 1L image data area i"18
9 requires 24576 bytes as in G TV mode. In the IJ and GV modes, the number of dots in the χ axis direction is G TV T, and the number of dots in the needle is 10-, which is 2-8, but the number of dots in the color code is 1.
'2. Since the color code is 2 bits, there are 4 [1 up to 4t] for 1 dont.
It is possible to decide. In addition, 1 rear 2 in VRAM2
b and 2c are the same as GIV'E-do. ■GVI Mortoko (D G Vl Mortoko Figure 4 (A) 1.:
', Show'i, ): 'J1. x, 512 x 192 dots double-sided configuration, I C, 1 J, color code G
Same as IV mode: 4-pin T-IM is configured. As a result, the size of still image data 1-rear 2a is 49152 bytes, which is twice that of G TV T-do (see figure (b)). Data ■
The arrangement order of the color 2]-cards in the rear 2a is 1" as shown in Figure 11 (c). ■GV mode In this GVI mode, the color 1-dore is 8 pips 1.
-, and as a result, 256 colors can be specified for one dot on the display image 1. In addition, the screen configuration is shown in Figure 5 (a), 256 x 192
The contents of still image data T) No. 20 are 49152 bytes, same as G Vl”l-.
It becomes. So, the same still image f'-ta area 2 F
The arrangement order of the NoJrah codes in + is stored in the 51st "2+ (c), one at a time, one at a time, and - (
There is. The above-mentioned -1 block processing circuit 1 [5] only performs the transfer of the color code in the still 1V image data [rear 2a] and the command λ in the dot map t-dots GIV to GW. The command processing circuit 15 is controlled by (, Y). Next, the details of the command processing circuit 15 will be explained. FIG. In this example, 20 is a command register that stores the cloak data output by CP tJ4.
A group of high-speed bead move instructions that perform rewriting at high speed, and a group of transfer σ when transferring and rewriting data.
data that already exists at the destination,
And, 71 a. It is divided into a logical A pe 1 no 1- command group l which performs logical arithmetic such as to (not) or exclusive Δa, and the upper one bit of command data becomes command specified data. ). (7) If the [-1 logical operation 1 instruction is specified, the lower /11 bit of the command data to be I134 is
Specify whether to perform +811 calculation (and, or, etc.) 7
5J, ). ] The command designation data of the 1/1 bit of the land 1 register 2 is 1x'
After being decoded by the micro 7 [1-gram ROM (hereinafter referred to as μ-program [1-gram RO])
Mdo #+ -4'> 22, Jump Hunt Roller 2
3 and Jζ and is supplied to the high speed move detection circuit 24. The μB[1gram ROM 22 stores multiple microprograms that correspond to various types of -l cloaks.
1 output of cloak decoder 21@. The selected microprogram 1 is the program counter 25.
Corresponding to the count up of the count output OT2, the μ instruction is read out sequentially and the μ instruction>'TRl-da (
(hereinafter referred to as μID) 26. This μ13-11) 2 C; l; t II p I-1 gram [')
The instruction read from M22 is sent to program counter 2.
Analyze according to the count up of the count output OT1 of 5, and calculate the analysis result and convert it into a 1-no register circuit (hereinafter ΔRC
In addition to supplying the analysis result to 27 (abbreviated as I)
Various 1lill #signals (, )MPl, JMP2, j:UVΔS) are appropriately created and output. in this case,
Karan 1 ~ Output OT1 is ternary, OT2 is hexadecimal, and i15? 1, the count output OT2 is 4r so that it is incremented by 1 every time the count output (lrl goes around).In other words, for one instruction read from the μ program ROM 22, the analysis process of μ1D26 requires 3 steps. The terminal CK of the program counter 25 is a clock input terminal, and the terminal CK of the program counter 25 is a clock input terminal.
is a ret terminal, PS is a preset terminal, and C is a % btf child during counting. 28 is a VRAM access=1 controller, which performs the processing described below. Now, the command output from μB [1 gram ROM 22 is
Assuming that the instruction requires access to VRAM2, μID14-26 receives the signal VA S OW VRAM t///I゛□7. : + Supply to n-ra 28. Then, the VRAN4 controller 28 is
Check whether signal 81 is output when Buddhist bow VR3 is supplied with illumination (?+<'c Wow, image data processing circuit 1
0 is in the process of passing \/RΔM2 j7), and if the signal qS1 is output, the signal S3 is
Supply 1) to terminal C of the gram counter 25 and interrupt the 1+ count operation of the gram counter 25! Ru1
As a result, the μrD26 is unable to move on to the instruction analysis process and enters a standby state for 3 steps.-1)
, signal S1 is output (if not, VRAM accretor) controller 28 outputs signal S3, and as a result,
//I D 26 immediately performs instruction analysis processing 1. By moving two times, access to y, \/1 ΔM2 is executed. In this way, VRAMA/) ps]n1~[-1
The -1 controller 28 performs the function of 1) to avoid access conflicts between the -1 and 1-nd parallel circuit 15 and the image fα1j data processing circuit 10. Next, the jump controller 1-1-controller 23 is used to input jump destination addresses of λ1 to various jump commands in the microphone program, and internally includes a jump destination address for selecting the jump destination. In this case, the Noritub flop FF1 [1 is for each detection signal output from the 17 result discriminating circuit 55 (see FIG. 7) in the RC27. <->;<: 0
>, , ~::25Fi>, <512> (The meaning of these detection signals is 1 cm), which will be explained later), and the signal JMP1, and the flip-7 day FF2 is jinf', <>, <0″
The reset signal path G of F[1, 2 is omitted from the illustration in order to avoid the troublesome point 1 in the explanation. ).Then, the controller 23 generates the output signal of the digit 1 destination based on the value of the status count output OT2 of the flip flop FFI and 2 and the output signal of the command data 1-der 21. Then, this jump destination address is output to PS of the program counter 25.When the jump destination address is supplied to the terminal PS, the program counter 25 immediately outputs it as a count output OT2. The processing of the microphone 1-1 program inside moves to the instruction l\ at the jump destination address.The high-speed move detection circuit 2/I processes it in the current n4 port based on the ml-/node decoder 2]0 output signal. It is detected whether the command belongs to the group 1 of high-speed move instructions, and if it is detected that the command is a high-speed move instruction, the signal S2 is converted into an image γ.
- data processing circuit 101\output 5. Then, while the signal S2 is being supplied to the image data processing circuit 10 (
Jii 111 person show f1 soku becomes prohibited 11 state. this is,
In the high-speed move command, the command processing Ti1
1 circuit 15'1 also uses the time slot l-1 allocated to video processing of the image data processing circuit 10,
\/Aku I to RΔM2! This is because it is necessary to Next, the logical A performance decoder 30 decodes the data in the lower 4 bits of the command register 20 (data specifying the type of deduction in 13 for the logical operation command), and decodes the data. The result is supplied to 101) 28 I-/In in ΔRC27 (see FIG. 7, 17-). The L-OP controller 40 performs a logical operation specified by the signal supplied from the L-OP decoder 30, and the details of the operation will be described later. 3'1 is a mode register, in which data specifying which of the above-mentioned dot maps GrV''-G■ is written by CI)tJ/I, and the written data is written to the ARC27. 32 is Argy 1
This is a 1-1 non-star register, and is an 8-position register as shown in FIG. 8(a). The second . Third
Data specifying the direction (for this direction, i9 iil'r "j") when transferring or rewriting the color code in the VRAM 2 is written to the pin 1. 33 is a command processing circuit. This is a flag 1 register consisting of various flags indicating the processing status of 15, etc. in CP LJ 4. The functions of the flags will be described later), etc. 37 is a flag li control circuit, which outputs a count (O-r 2).
, △RC27 output signal and CP .Next, there is -) in △RC27 and theory 1'! l'Ile. ARC27 is shown in Figure 7'! IJ, sea urchin, a large number of 1 nojisutas 40.~51 (these registers/)l; Therefore, the address shifter 52 that shifts the sensor I data and the addition/subtraction 0 circuit 5'i3 that performs addition and subtraction of each scale data, etc.) J error: 1-1 data bit shift 1~ Whether the calculation unity of the addition/subtraction circuit 53 is fl or 0, such as data thick 5/l,
2! It consists of the above-mentioned IOP controller 40, a ringing result discriminating circuit 55 which detects whether the ring is ``i6'' or ``512,'' and supplies this detection result T to the dithump controller 23. Then, △17G27 is (E Fi IJ S
56 to other components in the command processing circuit 15 and (f CP 1.
l (1', IB IJ S 57 for internal data exchange 1-1. Also, \/ 1iBUS58 is V
It is a data bus for RAM, and VΔ13 US! '
i 9 C, t, V F; There is a dead address bus for ΔM. Next, I will explain 1. - The operation of this embodiment according to its configuration will be explained. Note that in this embodiment, various movements IY to 1 and =1 cloak are not set, but Jl! Ming no 1
1+"th n8 avoidance (In order to avoid this, I will only explain the above-described mantle that is related to the gist of this invention. ■CI) IJ =! 1) T-1 cloak processing circuit 151 [Input/output 1. : In the case of a high-speed move operation in which the color code is transferred to a predetermined block in the reno 72a as still image data in bytes (i.e., in the case of coloring). , 1: , Color-1 in high-speed move motion
-Outline of dot turn 3'A (Jtsui? i11 light. Fig. 9 (
B) ~ (C) C GIV (GW)E F, GV mo respectively
F. Figure 1 shows the correspondence between the coordinates of the dots on the display screen in the 0■L-dore and the color code that specifies the color of the nameplate. 11 still image data] - 7 corresponding to 1 byte of rear 2a.As shown in this figure, in GIV (GVI) mode, 1 byte is 2
dot] ~ minute, in GV mode, 1 byte equals 4 dots, G
The number is specified by the Vll earth code, and the color for one dot is specified by the 11 by 1- code. Therefore, in this high-speed move operation, the color code is transferred at the byte ψ position.
yo-) [J, and as a result of -2, GTV(GV[I
In E mode, 2 dots are printed at a time, and in GV mode, 4 dots are printed at 1 time. T, :I, T, G In Vll mode, one dot is converted to one square)'A is output). Also, if the 1 byte worth of data to be transferred is
For example, when performing 10 transfers (JL, in the area shown by solid diagonal lines and M in Figure 10). Transfer J, sea urchin, as shown in the figure with dashed lines] - y (Still 11 image data IT IJ', 1) 2a
The transfer of l\ is lj! c.
I try not to fall.) It should be noted that FIG. Now, FIG. 11 shows a node corresponding to the processing process of the high-speed 11-b described above. The operation 21- in this case will be explained below with reference to this flowchart. First, CI]U4 specifies -1 and 17 as the transfer destination in step CP1. The first method for specifying this area is
To explain with reference to Fig. 2 (display screen shown), first, the χ, y coordinates of white P, which is the base ring, are expressed as 1 nosisters DX, D.
Yl each? Listen to it. Next, the number of dots in the χ direction and the number of dots in the y direction are written into registers NX and NY, respectively. At this time, the argument register 32 (FIG. 8 (A)
)'s 2nd pin]・(hereinafter referred to as DIRX pin) is “
If you put 1 no in 0゛, ]nojis<t N
, the number of dots is 11, l) in the +χ direction.
If the TRX bit is set to 1'', the number of dots written to register NX will be taken for one χh direction.
Similarly, the number of drivers written into register NY is the third hit of argument register 32 (hereinafter DI).
If the RY bit (referred to as l-) is set to 0'', it will be traced in the +-y direction (downward in the drawing) and the DIRY bit will be set to 1'.
. If set to , it will be taken in the -y direction. That is,
DI RX hit and DTRY pit contents 22 - 7 pa, Lil1 whether to II OII or 1"
It is possible to select one of the T-leafs 1 and 1f of the T-leafs 1 to q) based on '. Next, CPl) 4 is ': 1 cloak 1 nosister 2 (1f
;: Two! 1; Commands corresponding to the operations (hereinafter,
This nondo is called lIMMV: If 1g1
l Spe+! +I N4ovOVDl) to V
RAM) 13 Input (Sfutsubu S, P1),. Coni 1 cloak register 20] nd is ;J <) included;
1, the flag control circuit 3/I sets the CF flag in the flag 1 register 33 to l! 21 cloak l j
- Indicate that V inclusion has been completed by η1 to c p L, I /I.
Ra1! (Tt/SP2>. In this case, 0 [flag is set to [-sa11-(while CPU=1 is new command 4,]], T t'! to Norand register 2. Therefore, = 1 cloak processing circuit 1 F'i 1. Move to J block SP3 and transfer the contents of 1 nozzle F)
(transfer to
G;1. In Snop SF) 4, CPU
/I outputs NoJler 1-doday-/I (8t atto), and sells this column m:1-de as 1nosister CL.
Transfer to R''!j-.In this case, CPU=1 is output
The color of i is 8 bits.hl I
'), as mentioned above,
+'t, Gv" [-Door 1; Contains 1.4 dots worth of color code.1) I,: Therefore, the specified range on the static screen is the same (?3). Fill? IP)
In the second case, the CPU 4 outputs each color included in the color "1-1" data as the color 1 of fil-.
- It is necessary to set it to - mode. Next, when moving to C and Sn2, the contents of No. 1 CLR are changed to No. 1 No. 1. , forwarded to the OR, and then transferred to the VRA
M2)' 774! The process moves on to step SP'7. L,, (TTE, S: l horn SP7 (Jru
AM Access processing will be explained below. Now, assume that GIV-E-do is not selected in one warp, and the R6 mark (χ, y) on the display screen shows the command processing time V.
Consider the case where the color code in register 10R of 815 is to be inverted. In this case, first, the j' address in the still image data area 2a that corresponds to 3.1 to (〒!(χ,■)) is excluded. 'Cl:l
, Figure 2 (A) l: In the order shown, 4
The color 1-code of the bit is from at 1 nos 0 to l1ll' of the still image data area 2a! The address corresponding to the coordinates (χ, y) is determined by the formula: V Xl 28Lx /2 (1). Therefore, the data in one register (corresponding to the y coordinate) to the 7-bit position, and the data in register [)
Shift 1-pit to the 10-position side, undo the 2-1 bit, and synthesize the data after these gits to get the coordinates (7, V) 11 and the corresponding address. can be created. Similarly, address lockout (,1,877 can be obtained by the following formula: V XI 28+x //I ...... (2) (G
V i--de) 25- V X256 (x /2 ...... (3) ('
(G Vl mode) ■ × 256 + Data in Regis/) DXA to those who do Hecino 1 to 2
The bits 2-' and 2-2 are shifted to the hand position side, and the address data is created.1 Similarly, in the GVT mode, as shown in equation (3), the register The data in DY is shifted by 1 bit to the 10th digit side, and the data in register DXA is shifted by 1 bit.
Shifting to the lower side, the ``'at'' of 2-1 is ignored, thereby making the atto 1 nos data 1 - 1 C. Also, G■
In mode (well, (4) As you can see from 1℃, the data in 1 no register DY is shifted 1 to the 8-pi l-, 1- position side.
-C, the data in one register DXA is directly combined with this shifted data to create -C address data. Wow,'? In this embodiment, the address shifter 52 shown in FIG.
is going on. In other words, the AT 1 nozzle controller 52 determines the number of shifts of the data in the register DXA based on the 1--D designation j' in the 1-D register 31, and shifts the data by this number of shifts. After downsizing, V
A f(1, J S 59 (7) T” mal A
Output to I (F; tp1~). Also, when in address shift 'i 5241G Vl mode or GVW mode, the notator in 1 nojista DY is changed to /7)ttVA1
11 no S! 'i 9 no l I & flllll△11(
8 bits), resulting in an increase of 8 tons), GIV, 11.1 of the G Vt-code.
(set the data in the register DY to 1 bit 1 to 1 bit), and set it to the lowest pin 1 with V A 131J,
Below S 59 (when outputting to the highest pitch 1 of 1°l side A1-): /) C;
lΔB (J S 59 soil 11'/side △) is output to 1 (as a result, it is shifted up by 7 bits)
. On the other hand, ffi 6 l'l ni "J' /l I'
I) 26 +, 1. , Detects that the processing in SF3 is \/ RAM 2 7 and 1 no processing C, ■ [C △ Maku 1! Sue 1nt f
The signal VAS is output to the 1-ra 28. This conclusion q2, \
/RΔN11 Anono 1, the controller 28 sends the signal S1
It is checked whether the command processing 191 r815 and the image face data processing circuit 10 access conflict is avoided. If the signal S1 is not output (or the signal S1 stops), ΔRC271 will set the node in the register CIR to VDI3.
This outputs the color code (1 byte) in the register LOR to the address in the coordinate (χ.
can be transferred. 1 point, 2 dots in GIV, G Vl mode, 4 dots in GV mode.
The data for 1 to 1 bit, G VIT, - (in case of J, 1 bit worth of /J error) - is transferred at this time. The above is the processing in Snob IS P7.Next, , as shown in FIG. 11 (1 step S[)8, the value is subtracted by 1 from the contents of the register N×, and the result of this subtraction is assigned to the register NXA again.
It corresponds to the number of dots of color code to be transferred at a time, and therefore G IV. 2 for GvI'U need, Q V E -1' r l
:I, '1. GVl [1 and 4i in t-do,). Then, in this Stella 1sP8, (the operation shown in FIG. 7) is applied to the branch 0 circuit 53. ′?
I1. In addition/subtraction/stop circuit 5):3, based on the data specifying the second in the mode register 31, the
Determine 11t1 of 1, 1 of 1 and register NX
From the 11th step of A, the second step (1. ma/, T, this Stella IS r) (', 1, performing the performance in J) is t9 on the 1 horizontal line - C1 C1 Udo 91 color The code is still transferred and shows 1 r7. Then, moving to step 51)9, μI 112 F
'+ outputs the signal JMPI and also outputs the signal JMPI and also outputs the signal
- The roller 23 outputs a detection signal from the calculation result ψ discrimination path j L5 and determines whether there is -C.
In the case of YESJ (Jump controllers 1 to 11-La 23 are internal 7 lip 71-1 knob FF1 to Sera 1 to 71 (
Step SP10). In this case, step sP9
The judgment at rYF:Sl means that the transfer of the (, shi, hr in one horizontal line) has been completed.Next, in step SP12, the I no register r)XA is Add 2 or subtract 1 to the contents and assign this calculation result to 1 nosister 1) XA again. In this case, the value of 2 (, IF - J: is different, G ■, G Vl
In mode 2.0V-E-FF 1. lt 4, GW
'[- is 1 and 1-( is present. Also, whether to perform addition or subtraction is arg]
It is determined by the contents of the TRX bit 1- (see Figure 8 (a)), and if the DI F< ing. In this step SP12 (l performance 1v
Ii! iq1 corresponds to the χ coordinate of the next transfer destination of the color code in one noister 10R. This calculation process is performed as shown in FIG.
Based on this, the value of 2 is determined and addition or subtraction is determined. Next, moving to step 73P13, μIF) 26 is
Output 3 J N4p 1 and also
0- The roller 23 makes a predetermined determination based on the valley detection signal of the stop/stop/T discriminating circuit 5. At this time, the DIRX bit is set to '(1') (when the display screen is moved to the right R direction, data transfer 4 and II). case), when the mode is GrV, G■, it is determined whether < 25) f'+ , :> No. 47 is output from the operation cohesion determining circuit 55. In this case, the addition/subtraction circuit 53 The output signal is the bending, stretching and binding of step SP12, *h i', +
, corresponding to the contents of register DXA.
Therefore, the judgment of step SPI 3 is 1 no register I)
Determine whether the content of No J in OR
? /- The χ mark of the next transfer destination of the code is displayed at I1 on the display screen.
side tJt:t JL 14 (, 2, in this case, 1 general i! 1i This is done by the processing)
1-, ;-, "L-do transfer 4r wa I C Iyo nishi tail. 61, !, 2, 1 If NEET is GV or GVI, for the same reason as above, jiii Q 10 It is fully determined whether the <512> signal is output from the T discrimination circuit 55. On the other hand, if D T f< When performing transfer), the <-> signal (negative detection 18
Determine whether the number) is being output. So, if ・ri-〉shinfu is output, it means that the next transfer destination χP1 of the color code in register 10R is displayed on the left side of both sides of the display (J is 1). 0, in this case too, do not change the color code.
: I'm trying to do it. - Then, the judgment result in step SPI 3 is r
'l' F S , in the case of l, the jump controller 23 selects the internal knob 7 [] horn F' 1 (Stella 7' SP 1 'I). Next, move to the short SPI 5. , determine whether there is a flip 7 [1 Tsubu 1 [1 Tsuba [? Tsu 1-za 41τ], and
Fsl's dinner party moved to step SF"'16, r N
In the case of 0.1 (return to L step SP7. The processing in step SP15 is
Row 5231. There are four rows, top and n. Rye 1 straw,
Jump controller 231; 7 units inside L 1] 1-
It is determined whether 1 to 1 FF1 has been set to cell 1 or not, and if it has been set, the destination address is output. As a result, the count output 012 is incremented as expected, Il/[17/U1. , R
r) From M22, the instruction for the next step ('?l I Twal-, , the processing in step SPI 6) is read out. In the case, the count output OT2 at the current 1.1 point of the jet roller 231J and the ]mant i'
"" - supplied from da 21] cloak j゛ - JL4
(In this case, the destination address is 11,
Atto 1 nos corresponding to step SP4), (“ no ji 11
Program the destination address for all 25 pre-1s!
・71-Supplied to legitimate child PS. As a result of J-, the process moves from Stella 1 SPI 5 to SP4. Then, “, the determination at step SPl 5 is r N O,
, 1, the processing of the command processing circuit 15 cycles through the bases SP7 to SP15. In this circular loop, since the contents of register DXA are sequentially incremented (or decremented) by 1 and = 33-1 in the process of step SP12, both data registers 77
2a contains the C set in step SP4.
The color code from P IJ 4 is 1° from the display surface.
i 7'j (or to the left) by scanning (on the actual display screen, it looks like J, which was instantly transferred). On the other hand, when the determination at step SP15 is rYEsJ and the process moves to step SPI6, the contents of registers DX and NX are transferred to one register DXΔ and NXA, respectively. The process in step 5P16 is the same as the process in step SP3, and the process in step 1. -), step 5P1
6, the contents of registers DXA and NX are returned to their original values. Then, moving to step SPI 7,
Subtract 1 from the contents of register NY and assign this curved extension frame to register NY again. This operation is performed by the addition/subtraction circuit 53 as in the case described above. Next, when the process moves to step 5P18, the μID26 is
3 Output J M P 2, and also jump ] nt 3
4--Ra 23 is written in another edition R85 Fi (C)) Is the Shinshu output?
Check to see if the force at 17 is <;-)k at 10'' If the <0> signal is output at 3° every 1 no,
Internal 7-lip [-1] 2 to 1! (Step 5P19). In this case, step 5P17
The result of the performance is r r)-1.
The color code transfer ends [,I,: means 1-ru,. Next, moving to step S l]20, 1 nosister [
) Add 1 to the contents of Y or G41 decrease the pupil), but the selection of addition or decrease is determined by In other words, if the DIRY bit is 0°, then the addition ε? ' Ka (F <C'h, 1) I R'l/
If Gotsu 1 is "1", the tightening will be reduced (t1/I:F). In addition, 1 person 1 growth of 1 nojis'll'l Y
Transfer - 1, Vl'to (corresponds to the reed, so this step S P 2 n smell - (is then transferred over color -
The y-coordinate of the transfer destination of the first code is determined. Here, we will explain how to transfer data according to the contents of DrRX bit [-1[1117Y bit].
In l[, Y bits are (0, O), (0, 1), (1゜1>
, (1,0>, the data transfer direction f!1 is -H, and the part surrounded by the dashed line l in the figure (
31. Indicates the transfer destination area (display screen compatible area). In this case, each area shown in (a) to (d) of the figure corresponds to areas (1) to (2) shown in FIG. 12, respectively. Now, step 5P20 has 1. Jruy! As soon as the P standard σ output is completed, the processing of the command processing circuit 15 proceeds to step S.
l) Move to 21 1. In this metsub 5P21, II I D 2 fi outputs the signal JMP2, and j
If the controller 23 is outputting a -co signal from the calculation circuit ε:5, that is, if the result of the calculation τ7 in step 20 is negative. Read the judgment to see if it is correct. If the signal is outputted, the slip FF1 switch is turned FF2 (step SP22). In this case, the accumulation result set in step 20 becomes 0 if the y-coordinate of the next transfer destination extends beyond the top edge of the display screen. The Atonzo process 51 input to 7"5P23 is set to end the operation without performing this transfer. Also, the trunk unity that is 1” in step 20 is i′!i,
-, if D I R"1/Pitsu I. Move.1゛Fritsubfu 1-1
Determine whether Tsubu FF2 has been deleted, [Y]-81
If r N 0.1, the process moves to step SP2/I, and if r N 0.1, the process returns to step S25. (Second status l5P23
The processing is performed in the diVlmpcomputer i~1]-ra2go3to4'':. The flip-flop F r 2 /r
'If it has been reset, STETSU f S P 5
The destination address corresponding to /It is supplied to the preset terminal PS of the program counter 25.
171 corresponding to the J address of 1 gram 11 is supplied to S. And 7 r
The count output of lgram/J counter 25) O-"2 is"
17'', the flag control = 37- The control circuit 34 resets the CIF flag (see Figure 8 (b)).
Atlino (Slut 5P24), a series of color T-shirts
The 1-word transfer operation ends (step 5P25). On the other hand, when the CF horn is reset, the CPU 4
Detection of completion of cloak Li M M V processing 1
Furthermore, the command register 20 changes to a state in which a new command can be imported. In this way, when the process according to flow 1'7-1- shown in FIG. 11 is performed, the color code in the register LOR is transferred to any one of 1J shown in FIG. 13 (a) to (d). Transferred to the set transfer destination area in order.ft
the law of nature. J5, -1. In the process described above, the yrrb mark of the next transfer destination protrudes from one edge of the display screen.
, Umu 111 (content of 1 nojista DY is 192Ll)
In the above case), bl is set to 1 so that the transfer of this color code is performed normally. (This is because, as mentioned earlier, the data area 2b in VRAM2 is located next to the image data area 2a, so
Data that protrudes from the bottom edge of both sides of the display should be stored in this area 38.
- I'll transfer it within 2 hours.) This is because I'm in Lno. Also, as is clear from the above explanation, (2-1
According to the Mantodo IMMV, if you specify the color code transfer destination and transfer direction for the command processing circuit 15, the rest will be automatically executed as desired. It is C. to execute. ■ When performing the filling process, perform a logical operation 1-1 between the color code that is transferred and the color code that already exists at the transfer 57, and Yotsu - C obtained t new color - 1 - roll the code;
An overview of the card transfer will be explained below. The color code transfer in this instruction is
Unlike, by transferring A11゛I to By1 (j, /, <
<Bit order (to be exact, 2 bits, 4 bits, 8 bits)
i) Transfer any one of ~ as a transfer unit (in other words, a color code unit). 1. /Therefore, in each of the t-dos G IV to G Vl, transfers to the areas indicated by solid diagonal lines in Fig. 10 are also accepted, as shown by dashed diagonal lines. Transfer to 1). Now, Figure 1/I is the above-mentioned condo l-MMV (+-o
gical MovOV l) p [o \/ RA
This is a sheet showing part of the processing process of M). (shown in this figure) [1-41/-
7 [-1-butr-1- step SP5 and step S
(interposed between P7) is 1 coach yard. Mar
This is (the processing of other parts of the 211nd l-MMV is shown in FIG. 11) [almost the same as the cordierate, but
In step 5 ( ) 5, the output from CI'-' U 4 is as shown in Figure '15 (a), (b), and (c).
Noi! The diagonally lined area shown in this figure is the part where the color code is stored, but the figure (a) shows the GIV (GVr). Mode, (1:] ) L'l: G V 'E F, (A
> indicates the case of GVI mode. Also, C.P.
The data output from tJ4 is shown in Figure 15 (A) to (C).
This cloak is shown in Figure 1. M
This is because MV performs filling in units of 1 or more. Next, we will explain the processing in each step 5P30 to 5P32. First, step S P 301 is a register l-, OR
The color code within is transferred to the data shifter 54, and the previous KL: l' Schiller 1-code is shifted up to the data shifter 54. In this case, the number of shifts from 1 to UP is determined by the selected mode and the contents to the 1 register DX. The shift 1 to up operations and the shift up function will be described below. Now, if we assume that t' rj is to be filled in in G rV (G Vl) 7th card, in the still 1st image data T area 2a in this upper card, the 2nd
Since the color codes are stored in the order shown in Figure (c), when transferring the color code to the upper 4 bits of each address in the still image data area 2a, the CP
The data output by jJ 4 (see Figure 15 (a)) is
Beep] - Transfer must be done after upshifting. Then, the decision as to whether or not to perform a 1-up is determined by the χ coordinate of the transfer destination; '1', that is, if the χ coordinate is an even number, shift -7
``Tsubu'' and avoid upshifting when the number is odd. :F: Whether the number is even or odd can be determined by the least significant bit to the register Dx. Therefore, the data shifter 5) 4 shown in FIG. 7 determines the number of shifts based on the mode designation register j3 in the mode I register 31, and also shifts based on the contents of the lower bit of the register DXA. Determine whether or not. J: Go to GV mode [Furushizu 1 and both data areas 2]
Color codes are stored in a in the order shown in FIG. 3(c), and four color codes are stored in one address. In this case, the storage positions of the color codes in 1 at 1 node are shown in Fig. 16, q, a, h, c, r.
l, if you want to transfer to location a, register IOR
It is necessary to shift up the color code (see Fig. 15 ([1)) by 6 bits, and when transferring to position C, shift up by 4 bits and 2 bits respectively. There is a need. Then, which of the coordinates of the transfer destination corresponds to the position 42-1 can be determined by the contents of the lower two pits of the register DX. ,
0,1). Each island of (1, O) and (1, 1) is 4:/F? i
Corresponds to l, 11°c, d. However, 1 data sheet 1I54 is the mode register 31 in the mode register 31, and the lower 2 bits 1 to 1 of the register DXA contents 1□
The number of shifts is determined based on 23'4. On the other hand, since the color code in the G earth code is composed of 8 bits, the data output from the CPtJ (Fig. 15 (c)) is directly transferred to the still image data area 2.
Since it is sufficient to transfer it to the corresponding knot 1 node in a, there is no need to move it up. The color codes shifted from 1 to 1 by the data shifter 54 are again assigned to the 1 register I-OR. The above is the processing in Stella fS P 30. Next, in step S P311.7, a process is performed to read data in the static (1-image data J rear 2a) corresponding to the coordinates of the transfer destination.
(1, L, the address shifter 52 creates address data for addressing the still image data area 2a in the same manner as the slide SP7 shown in the #N1 diagram L) ((1)
2-(/I) formula), and Fig. 6 (S shown μr I
) 26 outputs the Shintan VΔS to the VRAM access controller 28 to avoid access conflict between the command processing circuit IF5 and the image data processing circuit 10. If the signal S1 is not output and there is no worry about access conflict, the color code (1
bytes) are read out to VDV3US581:. Next, the process in step 5P32 will be explained.
Ru. In this suit Tsubu 5P32, 10P]
The column m:1-code whose unit/IO is being read out on VDF3US5B (the color code that already exists at the transfer destination) and the color stored in the 1-no register t-OR A logical operation is performed with the code, and the stem connection is assigned to the register t-OR. In this case, the type of logical operation performed by the I OPI unit 40 is set in advance as nondo, or, not, exclusive or, etc.; I-OP whether no calculations are performed
It is determined by the output signal of the digital camera 30. ':4:
Ta. When performing the above-mentioned logical operation, the LOP coat 40 masks data other than the coordinates of the transfer destination out of the data of the VD BIJS 580 so as not to destroy it. Here, regarding this masking process, G V 'E
This will be explained using the - code as an example. Now shown in Figure 16! Let's think about IJ when transferring the color code (2 pits) from CP IJ 4 into 1ia. In this case, the color 1-code is shifted up by 6 bits by the action of the data shifter 54, so the contents of the register LOR at the end of the process of step 5P30 are It is as shown in FIG. Then, in step 5P32,
A logical operation is performed between this register l-OR and the data on the VORUS58, but in this case, the arcs at positions b to d are not the data to be transferred, so care must be taken not to destroy them. Must be Nishina IJ. Therefore, LOP] Nitsu 1-40
masks the Do bit or the θ5 bit of register LOR, and then masks the register 1. OR and Vr)
[Calculation is performed with the data on 3US58.] death! ,: Therefore, the contents of the DO pits 1 to D5 of the register LOR at the time when the process of step SP32 is completed are the color codes b to d shown in the same figure, which are transferred as they are. Which bit of the register LOR is to be masked is determined by the mode designation data in the mode register 31 and the contents of the lower two bits to DX. This process is performed in substantially the same way in QIV (GVI) mode, but masking @immediate is not performed in GvK mode. This is because the color code in the 0M mode consists of 8 bits. Then, when the process of step 5P32 is completed,
The process moves to step SP7 shown in FIG. 11, and the color code in the register 46-raster 10R is transferred to the corresponding atto 1 node in the static register 11-both data 1 rear 2a. Perform the same process as the above process. However, step SP8. SP12 (-j constant 1. to 2
(7) ffiha, G TV ~G W T'-F (
7) It"J' t+N A'; both T and 6 are 1. This is because the color code transfer according to the command l-M MV is always performed at the 1 dot Ili position. This J, uni, τ1nd IMM\/ k,'d'3
In case C, since the color code is transferred in a dot-like manner, there are no restrictions on specifying the transfer destination area (filling area), and it is possible to specify the area in detail. In addition, since logical operations can be performed between the dots that already exist at the transfer destination, the dot color after transfer is influenced by the dot color before transfer, and This makes it possible to reduce the effect of the scale display. For example, without changing the design of the already existing static 1F picture,
You can change only the color scheme of these 11 still images, or change only the design of a specific color by 4! [Efficacy of the Invention] As explained above, according to this invention, color can be applied to each dot on a still image. an image data processing circuit that displays 11 still images on a display screen based on each color code in the still image data 1-rear; A fill-in register in which the color code transferred from the outside is stored, and a transfer destination area when the color code in this fill-in register is transferred to the still image data area are based on the coordinates on the still image. (Transfer range storage means stored by range and transfer destination 1 stored in this transfer range storage means)
The rear is sequentially converted to the storage position of each color=1-code in the still image data area to create color hood position data, and the front i! [! and a color code transfer means for sequentially transferring the color codes in the filling register.
C, it is possible to set the fill area in detail, and 1) it significantly reduces the software processing burden on the CPU side! I can do that. In addition, a predetermined logical operation is performed between the color code transferred by the color code transfer stage f (J) and the color code that already exists at the transfer destination of this color code. , this !ii?'E' is equipped with a logical operation means for storing a new color code obtained as J to the transfer destination, the color of the dots changes extremely variously at the time of transfer, so it is not just a simple Filling-) It is possible to create a new display effect that is different from the filling.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, and FIGS. 2 to 5 show a display screen and a VRAM for explaining image modes GrV to G in the same embodiment, respectively.
2, and FIG. 6 is a conceptual diagram of the command processing circuit 1 shown in FIG.
FIG. 7 is a block diagram showing the configuration of the operation and register circuit 27 shown in FIG.
Figures (a) and (b) are respectively argi: L meat register 32
Figures 9(a) to 9(c) are explanatory diagrams showing the relationship between the coordinates on the display screen and the color code in each display mode, and Figure 10 is the color code. FIG. 11 is a flowchart showing the processing process of the command HMMV in the same embodiment.
Fig. 2 is an explanatory diagram showing a method of specifying a transfer destination area in the same embodiment, Figs. 15(a) to 15(c) show a part of the processing process of the command IMMV, respectively. This figure is a diagram for explaining the operation of the data shifter 54 shown in FIG. 7, and FIG. 17 is a diagram for explaining the operation of the LOP unit 710 shown in FIG. 7. 2a...Still image data area, 10...
- Image data processing circuit, 28... VRAM access controller (color code transfer means), 32...
...Argie 50- Comment register (transfer range storage means), 40...
・LOP connit (logical operator means), 52...
・Address chic (color 11-code transfer means), 54・
...Data shifter (Data Gino i, 1 stage), 1'
)
...Register (1 register for fill 17). Applicant Co., Ltd. Ne1 Asu ni 1-51-'gugo 10m-11>-- Cli-ichi-ka->-Otsu-11-11>- JP-A-Sho GO-194490 (19 ) To Madness Figure 15 P7 Figure 17 + VOS

Claims (1)

[Claims] (1,) Each dragon on a still IL image!・The still image data area in which each specified color code is stored, and each color code within this still image data area is displayed as a still image on the display screen. If the image data to be transferred to the 9-channel logic circuit and the color code to be transferred from the outside are IF! When transferring the stored filling register 1) and the /J learn register in the filling register of ξ to the still image data area, the transfer jX destination - 1 - rear on the still image A transfer range storage means which stores a range based on the coordinates and a transfer destination stored in this transfer range storage means stores the storage position of each color code in the image data ``si''. Create color code position data by sequentially converting to (J, Store corresponding to the color code position data 4; 1. ii'/'\ Sequentially transfer the color codes in the filling register Color m: 1-
Display controller 1-〇-ra with the code transfer means (-＾rito i!i m). - a still image data area in which a code is stored; an image data processing circuit that displays a still image on a display surface based on each color code in the still image data area;
2 registers for filling in which the color code transferred from the outside is hidden, and 1 register for filling in)
Transfer 1 RA'-de to the static 1 into the 1-car data 1-rear! A transfer range storage means stores the transfer destination area according to a range based on the PII mark of the static IL image l-, and this transfer range storage means stores the transfer destination area of the static IL image l- when the transfer destination area is Then, the storage position of each color code is converted sequentially into the two data areas to create a color-1-to position data, and the color code lf device data is converted to the storage position corresponding to the color code lf device data in the one register for filling. Color”-
46 colors] - the color code transferred by the color code transfer means, the color code transferred by the color code transfer unit IJ, and the destination of this color code? Performs a predetermined logic tifin with the color load existing in l'r, and stores the new code obtained by this operation to the transfer destination. Ll l! '
Display consoles 1 to 1-1- characterized by i.
La. (3,) Is the color code transfer page ``Q'' external?
- Number of bits in 1 at 1 node of data area J, less/, 1
If not, shift the color needle to the corresponding bit position IIJ! A display controller according to item 2 of the range of special vehicles, characterized in that it is equipped with data shifting means of 1j.