JPS6019222A - Clock generating circuit - Google Patents
Clock generating circuitInfo
- Publication number
- JPS6019222A JPS6019222A JP58127205A JP12720583A JPS6019222A JP S6019222 A JPS6019222 A JP S6019222A JP 58127205 A JP58127205 A JP 58127205A JP 12720583 A JP12720583 A JP 12720583A JP S6019222 A JPS6019222 A JP S6019222A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- power supply
- supply voltage
- circuit
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、マイクロコンピュータにクロック信号を供給
するクロック発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock generation circuit that supplies a clock signal to a microcomputer.
マイクロコンピュータの最大動作クロック周波数と電源
電圧とは、一般に第1図に特性線1で示すような関係に
ある。例えば、動作電源電圧範囲が3〜6■であシ、標
準電圧が5■のマイクロコンピュータでは、標準5V、
最低値3V、最高値6Vの電源環境で使用する場合(第
1図で、Vz=3V、V2=5V、’Va=6V)、
入7Jりo ツクの周波数は、使用電源電圧の最低値(
ここでは3V)でもそのマイクロコンピュータが正常に
動作し得るように、使用電源電圧の最低値における該マ
イクロコイピユータの最大動作クロック周波数f1′以
下に設定される。。The maximum operating clock frequency and power supply voltage of a microcomputer generally have a relationship as shown by characteristic line 1 in FIG. For example, in a microcomputer with an operating power supply voltage range of 3 to 6 cm and a standard voltage of 5 V, the standard voltage is 5 V,
When using in a power environment with a minimum value of 3V and a maximum value of 6V (in Figure 1, Vz = 3V, V2 = 5V, 'Va = 6V),
The frequency of input 7J is the lowest value of the power supply voltage used (
Here, the maximum operating clock frequency f1' of the microcomputer at the lowest value of the power supply voltage used is set to be lower than the maximum operating clock frequency f1' so that the microcomputer can operate normally even at 3V. .
上記のようにして設定されたクロック周波数は。The clock frequency set as above is.
特性線2で示す如く、電源電圧にかかわらず一定であり
、標準の使用状態(ここでは5V)での最大動作クロッ
ク周波数(第1図のf2)よシかなり低い値(−桁程度
)である。そこで、マイクロコンビーータの処理速度は
、使用電源電圧の最低値によシ決定される遅い値(動作
電源電圧範囲でMシ得る最低値)になる。このように、
マイクロコンピュータの電源電圧にかかわらず周波数が
一定のクロック?発生する従来のクロック発生回路を用
いたのでは、マイクロコンピュータはその電源電圧で定
まる最大の処理速度よシはるかに低い処理速度で作動せ
ざる全得ない。As shown by characteristic line 2, it is constant regardless of the power supply voltage, and is a much lower value (about a minus digit) than the maximum operating clock frequency (f2 in Figure 1) under standard usage conditions (5V in this case). . Therefore, the processing speed of the microconbeater becomes a slow value determined by the lowest value of the power supply voltage used (the lowest value that can be obtained in the operating power supply voltage range). in this way,
A clock whose frequency is constant regardless of the microcomputer power supply voltage? If a conventional clock generating circuit is used, the microcomputer is forced to operate at a much lower processing speed than the maximum processing speed determined by its power supply voltage.
本発明の目的は、マイクロコンピュータの最高処理速度
近傍でそのマイクロコンピータ全作動させるマイクロコ
ンピュータ用のクロック発生回路の提供にある。SUMMARY OF THE INVENTION An object of the present invention is to provide a clock generation circuit for a microcomputer that fully operates the microcomputer at near its maximum processing speed.
本発明によるクロック発生回路は、マイクロコンピュー
タに加えられる電源電圧を検出する第1の回路と、前記
電源電圧に対応して定まる前記マイクロコンビーータの
最大動作クロック周波数に近似していてしかもこの周波
数よシやや低い周波数のタロツク信号金前記第1の回路
の出力に応じて生ずる第2の回路と金備えて構成される
。A clock generation circuit according to the present invention includes a first circuit for detecting a power supply voltage applied to a microcomputer, and a clock generating circuit that has a frequency close to the maximum operating clock frequency of the microcomputer that is determined in accordance with the power supply voltage, and A second circuit is constructed in which a tarokk signal of a slightly lower frequency is generated in response to the output of the first circuit.
次に図面全参照して本発明の詳細な説明する。The present invention will now be described in detail with reference to all the drawings.
第2図は本発明の一実施例を示すブロック図である。1
1は電源電圧入力端子、21は電源電圧入力端子11か
らの電源電圧の値全ディジタル信号14に変換するA/
D変換器である。22は発振器であり、所定の周波数の
クロック12全出力する。23は分周器であシ、クロツ
ク12七分周して複数の異なる周波数のクロック信号1
3を出力する。24は、データセレクタであシ、ディジ
タル信号14に応じクロック信号13の中の一つ全選択
し、マイクロコンピュータ25ヘクロソク1H号15と
して与える。FIG. 2 is a block diagram showing one embodiment of the present invention. 1
1 is a power supply voltage input terminal; 21 is an A/V converter that converts the value of the power supply voltage from the power supply voltage input terminal 11 into an all-digital signal 14;
It is a D converter. 22 is an oscillator, which outputs all clocks 12 of a predetermined frequency. 23 is a frequency divider, which divides the clock 12 by seven to generate clock signals 1 with different frequencies.
Outputs 3. 24 is a data selector which selects all one of the clock signals 13 in response to the digital signal 14 and supplies it to the microcomputer 25 as the clock signal 1H 15.
第3図は第2図の実施例における電源電圧とり段状に特
性線lに沿って変化する(特性線lはマイクロコンピュ
ータ1の最大動作クロック周波数全示す)。従来のクロ
ック発生回路の特性線2に比べ、本実施例の特性線3は
、大部分の電源電圧範囲で上側にある。従って、マイク
ロコンピュータ25は、標準′電圧V2全含む大部分の
電源電圧範囲で、電源電圧における最大動作クロック周
波数に近い値で動作させる事が出来、非常に高り処理速
度で作動する事が可能となる。FIG. 3 shows that the power supply voltage in the embodiment of FIG. 2 changes stepwise along a characteristic line 1 (the characteristic line 1 indicates the entire maximum operating clock frequency of the microcomputer 1). Compared to the characteristic line 2 of the conventional clock generation circuit, the characteristic line 3 of this embodiment is on the upper side over most of the power supply voltage range. Therefore, the microcomputer 25 can operate at a value close to the maximum operating clock frequency at the power supply voltage over most of the power supply voltage range, including the entire standard voltage V2, and can operate at extremely high processing speeds. becomes.
以上説明したように1本発明によれば、マイクo コア
ヒュータの最高処理速度近傍でそのマイクo コア
ヒユータラ作動させるマイクロコンビ、−タ用クロック
発生回路が提供できる。As explained above, according to the present invention, when the microphone o core is near the maximum processing speed of the microphone o core
It is possible to provide a clock generation circuit for a microcombiner and a heater operated by a heater.
第1図は従来のマイクロコンビニーり用クロック発生回
路におけるマイクロコニ/ピユータの電源電圧に対する
クロック周波数の特性金示す図、第2図は本発明の一実
施例を示すブロック図、第3図は第2図の実施例におけ
るマイクロコンピュータの電源電圧に対するクロック周
波数の特性を第1図の従来例と対比して示す図である。
l・・団・一般的なマイクロコニピユータニおケル電源
電圧に対する最大動作クロック周波数を示す特性線、2
・・・・−・従来のクロック発生回路におけるマイクロ
コンピュータの電源電圧に対するクロック周波数を示す
特性線、3・・・・・・本発明の実施例におけるマイク
ロコンビー−りの電源電圧に対するクロック周波数を示
す特性線、21・・・・・・A/D変換器、22・・・
自発振器、23・・団・分周器、24・・・・・・デー
タセレクタ、25・・・用マイクロコンピュータ。
屹5片」罠FfL(V)
第 1 図
4
范2 図
応3 VFig. 1 is a diagram showing the characteristics of the clock frequency with respect to the power supply voltage of the microcontroller/computer in a conventional microconvenience store clock generation circuit, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is 2 is a diagram showing the characteristics of the clock frequency with respect to the power supply voltage of the microcomputer in the embodiment of FIG. 2 in comparison with the conventional example of FIG. 1; FIG. Characteristic line showing the maximum operating clock frequency with respect to the power supply voltage of a typical microcontroller, 2
...Characteristic line showing the clock frequency with respect to the power supply voltage of the microcomputer in the conventional clock generation circuit, 3...... Showing the clock frequency with respect to the power supply voltage of the microcomputer in the embodiment of the present invention Characteristic line, 21... A/D converter, 22...
Self-oscillator, 23... group frequency divider, 24... data selector, 25... microcomputer. FfL (V) 1st Figure 4 2 Figures 3 V
Claims (2)
検出する第1の回路と、前記電源電圧に対応して定まる
前記マイクロコンピュータの最大動作クロック周波数に
近似していてしかもこの周波数よυやや低い周波数のク
ロック値号全前記第1の回路の出力に応じて生ずる第2
の回路とを備えるクロック発生回路。(1) A first circuit that detects all power supply voltages applied to the microcomputer, and a clock whose frequency is close to, but slightly lower than, the maximum operating clock frequency of the microcomputer determined in accordance with the power supply voltage. The second value generated in response to the output of the first circuit
A clock generation circuit comprising a circuit.
路において、前記第1の回路は前記電源電圧の大きさ全
ディジタル4ぎ号に変換するアナログ・ディジタル変換
器からなシ、前記第2の回路は、一定周波数の1a号を
発生する発振器と。 その一定周波数倍母金分周して周波数が互いに異なる複
数のパルス45号を生ずる分周器と、前記ディジタル倶
号に応じた周波数の前記ノ(ルス僅号を前記クロック信
号とじて選択する回路とからなるタロツク発生回路。(2) In the clock generation circuit according to claim 1, the first circuit does not include an analog-to-digital converter that converts the magnitude of the power supply voltage into an all-digital 4-digit signal; The circuit is an oscillator that generates No. 1a of a constant frequency. a frequency divider that multiplies the constant frequency by the base metal and generates a plurality of pulse numbers 45 having different frequencies; and a circuit that selects the pulse number 45 having a frequency corresponding to the digital number as the clock signal. Tarock generation circuit consisting of.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58127205A JPS6019222A (en) | 1983-07-13 | 1983-07-13 | Clock generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58127205A JPS6019222A (en) | 1983-07-13 | 1983-07-13 | Clock generating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6019222A true JPS6019222A (en) | 1985-01-31 |
Family
ID=14954316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58127205A Pending JPS6019222A (en) | 1983-07-13 | 1983-07-13 | Clock generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6019222A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0291335A2 (en) * | 1987-05-14 | 1988-11-17 | Sony Corporation | Generating clock pulses |
JPH0254317A (en) * | 1988-08-19 | 1990-02-23 | Asahi Optical Co Ltd | Controller for cpu working speed of electronically controlled camera |
EP0537137A1 (en) * | 1987-10-27 | 1993-04-21 | Velox Computer Technology, Inc. | Computer element performance enchancer |
US6424184B1 (en) | 1996-09-25 | 2002-07-23 | Matsushita Electric Industrial Co., Ltd. | Frequency-voltage conversion circuit, delay amount judgement circuit, system having frequency-voltage conversion circuit, method of adjusting input/output characteristics of frequency-voltage conversion circuit, and apparatus for automatically adjusting input |
-
1983
- 1983-07-13 JP JP58127205A patent/JPS6019222A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0291335A2 (en) * | 1987-05-14 | 1988-11-17 | Sony Corporation | Generating clock pulses |
US5167031A (en) * | 1987-05-14 | 1992-11-24 | Sony Corporation | Variable frequency clock pulse generator for microcomputer |
EP0537137A1 (en) * | 1987-10-27 | 1993-04-21 | Velox Computer Technology, Inc. | Computer element performance enchancer |
JPH0254317A (en) * | 1988-08-19 | 1990-02-23 | Asahi Optical Co Ltd | Controller for cpu working speed of electronically controlled camera |
JPH0547849B2 (en) * | 1988-08-19 | 1993-07-19 | Asahi Optical Co Ltd | |
US6424184B1 (en) | 1996-09-25 | 2002-07-23 | Matsushita Electric Industrial Co., Ltd. | Frequency-voltage conversion circuit, delay amount judgement circuit, system having frequency-voltage conversion circuit, method of adjusting input/output characteristics of frequency-voltage conversion circuit, and apparatus for automatically adjusting input |
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