JPS601849A - Connecting method of electronic part - Google Patents

Connecting method of electronic part

Info

Publication number
JPS601849A
JPS601849A JP58109845A JP10984583A JPS601849A JP S601849 A JPS601849 A JP S601849A JP 58109845 A JP58109845 A JP 58109845A JP 10984583 A JP10984583 A JP 10984583A JP S601849 A JPS601849 A JP S601849A
Authority
JP
Japan
Prior art keywords
holes
tape
substrate
forming surface
coated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58109845A
Other languages
Japanese (ja)
Inventor
Yukihiro Inoue
幸弘 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP58109845A priority Critical patent/JPS601849A/en
Publication of JPS601849A publication Critical patent/JPS601849A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/29076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Abstract

PURPOSE:To enable to connect at low temperature and to obtain suitable connection irrespective of the quality of a substrate wiring material by interposing an insulating layer formed with through holes at the parts corresponding to pads between a pad forming surface and a substrate, and interposing a conductive adhesive in the holes of the layer. CONSTITUTION:An acrylic photocurable resin tape 8 is coated on the pad forming surface of an LSI wafer 1 having aluminum pads 2. Then, through holes 9 are formed at the parts opposed to the pads 2 of the tape 8, and conductive adhesive 7 is filled and coated by printing means in the holes 9. It is cut at the part designated by an arrow, a photocurable resin tape 8 is formed on the pad forming surface, thereby obtaining an LSI chip filled and coated with the adhesive 7 in the holes 9 of the tape 8. The tape surface of the chip 1 thus obtained is matched to the wiring forming surface of a substrate 6, the adhesive 7 and the wirings 5 are further positioned, pressed, and heated to be cured.

Description

【発明の詳細な説明】 く技術分野〉 本発明はＬＳＩチップなどの電子部品の接続方法に関し
、特に基板上の配線パターンとの接続において、接続温
度を下げることができるとともに基板材料及び配線材料
の材質に関係なく適正な接続が得られる新規な電子部品
の接続方法に関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a method for connecting electronic components such as LSI chips, and in particular, in connection with wiring patterns on a substrate, it is possible to lower the connection temperature and reduce the temperature of the substrate material and wiring material. The present invention relates to a novel method for connecting electronic components that allows proper connections to be made regardless of the material.

〈従来技術〉 従来性なわれている電子部品（ＬＳＩ）と基板との一般
的な接続方法は、たとえば、第１図に示す様にＬＳＩチ
ップ１のアルミパッド２にバリアーメタル３を形成し、
その上に半田バンプもしくはＡｕバンプ４を形成し、こ
のバンプを介して基板６の配線５に接続している。<Prior Art> A conventional general method of connecting an electronic component (LSI) and a board is, for example, as shown in FIG. 1, forming a barrier metal 3 on an aluminum pad 2 of an LSI chip 1.
A solder bump or an Au bump 4 is formed thereon, and connected to the wiring 5 of the substrate 6 via this bump.

しかしながら、前者の半田バンプによる接続の際はおよ
そ２５０℃で加熱し、又後者のＡｕバンプによるときは
およそ４５０℃で加熱する必要があり、いづれの方法も
相当の高温がＬＳＩチップ１と基板６に加わる。このた
め、基板材料は耐熱性のものに限定されるという問題と
ともに、カーボン等のように金属の共晶結合による接続
ができないような材料にて形成された基板配線には上記
従来の接続方法を採用することができないという問題が
あった。However, the former connection using solder bumps requires heating at approximately 250°C, and the latter connection using Au bumps requires heating at approximately 450°C. join. For this reason, there is the problem that the board material is limited to heat-resistant ones, and the above conventional connection method cannot be used for board wiring formed of materials such as carbon that cannot be connected by eutectic bonding of metals. There was a problem that they could not be hired.

〈目　的〉 それゆえ、本発明は低温下の接続が可能であり、しかも
基板配線材料の材質に関係なく適正な接続が得られる新
規な電子部品の接続方法を提供するものである。<Purpose> Therefore, the present invention provides a novel method for connecting electronic components that allows connection at low temperatures and provides a proper connection regardless of the material of the board wiring material.

〈実施例〉 以下図にもとづいて本発明の詳細な説明する。<Example> The present invention will be explained in detail below based on the drawings.

第２図は本発明方法によって基板に電子部品を取イｑた
図である。FIG. 2 is a diagram showing an electronic component mounted on a board by the method of the present invention.

図において、１はＬＳＩチップ、２は該チップのアルミ
パッド、５は基板６に形成した配線である０ ８はＬＳＩチップ１のパッド形成面と基板６の配線形成
面との間に介在させた絶縁層、たとえばアクリル系の光
硬化性樹脂テープである。このテープはＬＳＩチップｌ
のアルミパッド２に対向する部分に透孔が形成され、そ
の中に銀ペースト等の導電性接着剤７が注入塗布されて
いて、この接着剤７にてＬＳＩチップのアルミパッド２
と基板の配線５とが電気的に結合されている。In the figure, 1 is the LSI chip, 2 is the aluminum pad of the chip, 5 is the wiring formed on the substrate 6, and 08 is the wiring formed between the pad formation surface of the LSI chip 1 and the wiring formation surface of the substrate 6. The insulating layer is, for example, an acrylic photocurable resin tape. This tape is an LSI chip
A through hole is formed in a portion facing the aluminum pad 2 of the LSI chip, and a conductive adhesive 7 such as silver paste is injected into the hole, and this adhesive 7 is used to connect the aluminum pad 2 of the LSI chip.
and the wiring 5 of the board are electrically coupled.

第３図は接続手順を示すもので、この図により今少し詳
細に説明する。FIG. 3 shows the connection procedure, and will be explained in more detail with reference to this figure.

まず、アルミパッド２を具えたＬＳＩウェハー１（図■
）のパッド形成面にアクリル系の光硬化性樹脂テープ８
をコートする（図■）。次にテープ８のアルミパッド２
に対向する部分をフォトエツチング方式にて透孔９を形
成しく図０）、その透孔９に印刷手段にて導電性接着剤
（銀ペースト）７を注入塗布する（因■）。そして、矢
印の部分でカッティングして（図■）、パッド形成面に
光硬化性樹脂テープ８を形成し、このテープ８の透孔９
に導電性接着剤７を注入塗布してなるＬＳＩチップ１を
得る（図の）。First, LSI wafer 1 equipped with aluminum pad 2 (Figure ■
) Acrylic photocurable resin tape 8 on the pad forming surface
Coat (Figure ■). Next, aluminum pad 2 of tape 8
A through-hole 9 is formed in a portion facing the wafer by photo-etching (Fig. 0), and a conductive adhesive (silver paste) 7 is injected into the through-hole 9 using a printing means (I). Then, by cutting at the arrowed part (Fig.
An LSI chip 1 (as shown in the figure) is obtained by injecting and coating a conductive adhesive 7 on the substrate.

こうして得られたＬＳＩチップ１のテープ面を基板８の
配線形成面に合わせ、さらに導電性接着剤７の部分と配
線５とを位置合わせしたのち、２０に９／、Ｉで加圧し
た状態で＋５０°Ｃの算囲気の中に１時間程度置いて硬
化させる。After aligning the tape surface of the LSI chip 1 obtained in this way with the wiring formation surface of the substrate 8, and further aligning the conductive adhesive 7 and the wiring 5, pressurize with 20 to 9/I. Leave it in an ambient atmosphere at +50°C for about 1 hour to harden.

このようにして従来よりもかなり低い温度下で基板と電
子部品を接続することかでき、同時に光硬化性樹脂テー
プ８に５ｔａｎｄ　ｏｆｆの役目を兼ねさせることがで
きる。In this way, it is possible to connect the board and electronic components at a temperature considerably lower than in the past, and at the same time, the photocurable resin tape 8 can also serve as a 5-and-off tape.

〈効　果〉 以上の様に本発明によれば、電子部品のバンド形成面と
基板との間に、該パッドに対応する部分に透孔を形成し
てなる絶縁層を介在させ、且つ該絶縁層の透孔に導電性
接着剤を介在させることにより、１）８記基板に電子部
品を接続するようにしたから、低温下で接続することが
できる。このため熱による基板の変形を防止することが
できる。また導電性接着剤を用いているのでどのような
基板配線側斜であっても電子部品を接続することができ
る。<Effects> As described above, according to the present invention, an insulating layer having through holes formed in the portions corresponding to the pads is interposed between the band forming surface of the electronic component and the substrate, and the insulating layer is By interposing a conductive adhesive in the through-holes of the layer, 1) electronic components can be connected to the substrate No. 8, so that the connection can be made at low temperatures. Therefore, deformation of the substrate due to heat can be prevented. Furthermore, since a conductive adhesive is used, electronic components can be connected regardless of the orientation of the board wiring.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の接続方法を示す図、第２図は本発明方法
による接続状態を示す図、第３図０〜Ｏは本発明方法に
よる接続手順を示す図である。 １はＬＳＩチップ、２はアルミパッド、５は配線、６は
基板、７は導電性接着剤、８は光硬化性樹脂テープ、９
は透孔。 代理人　弁理士　福　士　愛　彦（他２名）第３図 第１図 の ■　′FIG. 1 is a diagram showing a conventional connection method, FIG. 2 is a diagram showing a connection state according to the method of the present invention, and FIG. 3 0 to O are diagrams showing a connection procedure according to the method of the present invention. 1 is an LSI chip, 2 is an aluminum pad, 5 is a wiring, 6 is a substrate, 7 is a conductive adhesive, 8 is a photocurable resin tape, 9
is a through hole. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 3, Figure 1 ■ ′

Claims (1)

【特許請求の範囲】[Claims] １　電子部品のパッド形成面と基板との間に、該パッド
に対応する部分に透孔を形成してなる絶縁層を介在させ
、且つ該絶縁層の透孔に導電性接着剤を介在させること
により、前記基板に電子部品を接続するようにしたこと
を特徴とする電子部品の接続方法。1. Interposing an insulating layer with a through hole formed in a portion corresponding to the pad between the pad forming surface of the electronic component and the substrate, and interposing a conductive adhesive in the through hole of the insulating layer. A method for connecting electronic components, characterized in that an electronic component is connected to the substrate.
JP58109845A 1983-06-17 1983-06-17 Connecting method of electronic part Pending JPS601849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58109845A JPS601849A (en) 1983-06-17 1983-06-17 Connecting method of electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58109845A JPS601849A (en) 1983-06-17 1983-06-17 Connecting method of electronic part

Publications (1)

Publication Number Publication Date
JPS601849A true JPS601849A (en) 1985-01-08

Family

ID=14520651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58109845A Pending JPS601849A (en) 1983-06-17 1983-06-17 Connecting method of electronic part

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Country Link
JP (1) JPS601849A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0321239A2 (en) * 1987-12-17 1989-06-21 Matsushita Electric Industrial Co., Ltd. Fabricating method of semiconductor device
WO1991009419A1 (en) * 1989-12-18 1991-06-27 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
EP0475022A1 (en) * 1990-09-13 1992-03-18 International Business Machines Corporation Direct attachment of semiconductor chips to a substrate with a thermoplastic interposer
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
EP0810649A2 (en) * 1996-05-28 1997-12-03 Motorola, Inc. Method for coupling substrates and structure
EP0962978A1 (en) * 1998-06-04 1999-12-08 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing same
US6189208B1 (en) 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
US6219911B1 (en) 1998-03-23 2001-04-24 Polymer Flip Chip Corp. Flip chip mounting technique
US6410415B1 (en) 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
EP1022774A3 (en) * 1999-01-21 2003-08-06 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
EP1306897A3 (en) * 2001-10-29 2005-05-11 Fujitsu Limited Method of making electrode-to-electrode bond structure and electrode-to-electrode bond structure made thereby

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0321239A2 (en) * 1987-12-17 1989-06-21 Matsushita Electric Industrial Co., Ltd. Fabricating method of semiconductor device
WO1991009419A1 (en) * 1989-12-18 1991-06-27 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
JPH05503191A (en) * 1989-12-18 1993-05-27 エポキシ・テクノロジー・インコーポレーテツド Flip-chip technology using conductive polymers and insulators
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
EP1089331A3 (en) * 1989-12-18 2004-06-23 PFC Corporation Flip chip technology using electrically conductive polymers and dieletrics
US6138348A (en) * 1989-12-18 2000-10-31 Polymer Flip Chip Corporation Method of forming electrically conductive polymer interconnects on electrical substrates
US5879761A (en) * 1989-12-18 1999-03-09 Polymer Flip Chip Corporation Method for forming electrically conductive polymer interconnects on electrical substrates
US5918364A (en) * 1989-12-18 1999-07-06 Polymer Flip Chip Corporation Method of forming electrically conductive polymer interconnects on electrical substrates
EP0475022A1 (en) * 1990-09-13 1992-03-18 International Business Machines Corporation Direct attachment of semiconductor chips to a substrate with a thermoplastic interposer
US6022761A (en) * 1996-05-28 2000-02-08 Motorola, Inc. Method for coupling substrates and structure
EP0810649A3 (en) * 1996-05-28 1998-12-23 Motorola, Inc. Method for coupling substrates and structure
EP0810649A2 (en) * 1996-05-28 1997-12-03 Motorola, Inc. Method for coupling substrates and structure
US6219911B1 (en) 1998-03-23 2001-04-24 Polymer Flip Chip Corp. Flip chip mounting technique
EP0962978A1 (en) * 1998-06-04 1999-12-08 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing same
SG87034A1 (en) * 1998-06-04 2002-03-19 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing same
US6372548B2 (en) 1998-06-04 2002-04-16 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor package with a semiconductor device attached to a multilayered substrate
US6538315B2 (en) 1998-06-04 2003-03-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing same
KR100557049B1 (en) * 1998-06-04 2006-03-03 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device and method of manufacturing same
US6189208B1 (en) 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
EP1022774A3 (en) * 1999-01-21 2003-08-06 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
US6410415B1 (en) 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
EP1306897A3 (en) * 2001-10-29 2005-05-11 Fujitsu Limited Method of making electrode-to-electrode bond structure and electrode-to-electrode bond structure made thereby

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