JPS60183660A - Input and output processing unit - Google Patents

Abstract

PURPOSE:To attain efficient cueing with a small quantity of hardware by providing a cueing means at each path and applying direct cueing to each path reaching an I/O for the input/output request to the I/O. CONSTITUTION:Channels CH2A-2D have respectively a cueingmeans and when a CPU1 starts an I/O5, only a device number given specifically to the I/O5 is designated and the path reaching the I/O5 is not designated. That is, this path is decided by an input/output processing unit 2, path information is given respectively to a sub-channel SBCH6 corresponding one by one to the I/O stored by the unit 2 and the CH2A-2D are given to line control information PCW. Thus, the efficient cueing and path selection are attained with a small quantity of hardware by applying direct cueing to each path reaching the I/O for the input/ output processing request to the I/O.

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to an input/output processing device that connects a central processing unit and an input/output device. [Background of the Invention] Conventionally, in input/output processing of a computer system, when an input/output device is activated, queuing of the input/output requests and selection of a route to the input/output device are generally performed on the central processing unit side, that is, by software. method. In this case, when an input/output device is activated, a method is used in which a group of routes is queued in a fictitious channel called a logical channel, and one of the available routes belonging to that logical channel is selected. ing. On the other hand, in recent computer systems, the queuing and route selection functions described above tend to be performed by hardware. In this case, such functionality is generally provided within the input/output processing device. However, if you follow the above software method, you will need tables that represent the correspondence between input/output devices and logical channels, and between logical channels and route groups. Since the dequeue process is performed in two stages, including a logical channel and a logical channel input/output device, there are problems with both the amount of metal objects and the speed of dequeue processing. Effect of request 1.
- To provide an input/output processing device that realizes good queue ink and route selection functions. [Summary of the Invention] The present invention provides 111 points between the central processing unit and the input/output device.
Input/output processing units connected via dangerous routes
In this method, a queuing means is provided for each route, and an input/output request to a certain input/output device is directly registered in the above-mentioned queuing means of the route 1- to the input/output device. By doing so, the chief fluva for logical channels is

This makes it possible to increase the speed of dequeue processing. [Embodiments of the invention]

FIG. 1 shows a system A! which is the object of the present invention. An example of +'J formation is shown. In the figure, ■ is the central processing unit i"j ((2II)
Ll), 2-digit input/output processing unit (IOP), 2A~2
1) are connection paths or channels (CH), 3 and 4
is human output control bag W (, (IOC), 3A, 313.4A
. lIB is the channel interface switch (CI-[SW) attached to 10c3.4, 5 is the input/output device (TOD)-6 is the subchannel (SRCll) corresponding to IOD 5, 7Δ~7o+'1 ．． c.
112A--2'v connect IOC3,/l &1. 8 is a service processor (SVI') that executes system configuration control, maintenance, and diagnostic functions; IO represents the entire memory including S B CH 6; Also, although omitted in the figure, c I-12A~
Each 2D has one queuing stage. CP tJ I, for example, when starting l OD 5, I
O]] Specify only the device number uniquely assigned to 5 (also corresponds to the subchannel number) -T Specify the route to 5, and determine the 1:Y: route. is 10112. This route selection & T OP
In order to perform the process in 2, the s r3c ti corresponding to each 101] and 1 pair held by l0P2 has route information, and each CI (corresponding to route control information +1.j
(riCW). FIG. 2 shows the information format of 5I3C116 corresponding to IOD 5, and the same applies to other S B CI+. In FIG. 2, FATI+ indicates route information. In the configuration example shown in FIG. 1, to PATl-10:3, there are
) physical address) is assigned to cell i~. The route information is set at the time of system construction, and is stored in the floppy disk of the 5VP8, and its contents are loaded into the 313 CH when the power is turned on. As shown in FIG.
T A T US byte - Q that performs cuno control
CT1-byte, LT A representing the actual device address of l0D5, and NQUAQ~3 representing the device address of the device queued next to the device in the queuing means for each path. . sTA”S
”, the contents of US pie 1- are shown in Figure 3 (a), QCT
The contents of I-Pi1~ are shown in FIG. 3(b). Note that the empty space in FIG. 2 includes control information for normal data transfer such as 00w addresses, control information for interrupts such as device status byte, and interrupt parameters, but these are not included in the present invention. Since it is not directly related to
Further explanation will be omitted. FIG. 4 shows the format of the route control information (PCW). The PCW contains 5 TATUS bytes representing the status of the route (CI), and information Q for controlling the queue.
CTL, FQUA, LQLJA
It becomes more. The VQ bit in QCTL indicates that one or more devices are queued on the route, and FQUA is the head device address of the queue, LQ
UA also indicates the final device address. The contents of 5TATUS by i~ in this PCW are shown in Figure 5(a).
The contents of the QCTI-byte are shown in FIG. 5(b). Furthermore, l0P2 has a conversion table as shown in FIG. 6, which associates device addresses with S B CH numbers. Actually, this conversion table is configured as a part of the memory 10 together with each 5BCH and PCW as shown in FIG. Hereinafter, the route selection and input/output request queuing processing of 10D5 in 10P2 will be explained with reference to FIGS. 8 to 11. FIG. 8 shows the operation flow when IOD 5 is activated from the CPUI. Prior to the activation of Io1)2, the CPUI shall set activation pending pin 1~ in the 5TATUS byte of 5BCH6. l0P2 is I
o Upon receiving the activation for D5, Sl'3CH6
(see step 101) to obtain route information therein. First, select PAT HO from among them (Step 102), and test the VQ bit (VQO) corresponding to the current path in the QCTL byte (Step 103).
). If the corresponding VQ bit is already 1, this indicates that there are still queued items on the route in the activation prior to the current activation, and in this case, the process moves to selecting another route (step 119). If the VQO pin 1- is 7-1-1, then refer to the PCW of the route (step 10/I) and check its status (step 105). Then, if it is not running or starting, try starting from PAT HO (step 10).
(E). If that route is in operation or is being activated by the input/output device in the pond, the activation of l0D5 through that route is given up, and the user's output request is queued in the queuing means for that route (step 118). , the process moves on to selection of another route (step 119). If you select PATHI in step 119, SB C:
Test the VQI in H6's Q CT L Pi 1-. (Step 120), if VQ1=], the process will move on to selecting another route again (Step 125), and henceforth, j
'' is repeated (step 12G). If VQI is not set, P A T l-1
1 p c vt' t, see step 121),
Check its status (step 122). and,
PAl'' [(If l is in operation or another input/output device is activated, it is also queued to r'ATHl, and then the process moves on to selecting another route (step 12-1, 125). If ATHL is not in operation or starting up, an attempt is made to start it from the relevant route (step 123).When attempting to start up IO15 from the relevant route (for example, PATH HO), first CW of the relevant route is attempted. and SrtsuC
Set the pins 1 to 1 during startup of l (step 107.
108). As a result of this startup, if the startup is successful (step to9), r) cw and 5I3C! + running bin 1-
Reset the operating bits in both registers (step +15), reset the operating bits in both registers (step +1), reset Pino 1-( At step 117), the process moves to data transfer operation. At this time, even if there is a queued item already queued on another route, the dequeue process is not performed at this point. What is dequeued is that when that route becomes safe and is taken out of the queue, the I/O request for that 313 Cu has already been successfully activated on another route, or the operation has already finished. ■,
It is 5゛. BO) If the result is °yi device in use (
Step 11.0). After receiving the device termination report, restart the startup process.
'C, PCVt7 and S T3 Receive the pin 1 during startup of CI-1 (Step l l 3), 5BCH
The end of the device t,'r is sent to the pin 1 (step)-14) and waits for the device end report from 10F)5. If the startup result is other than the above, startup has failed and the PC
Reset the booting bits of W and SB (2 IIL; Steps 11 to 1.) and report to CP T-3+ that the boot has failed in the form of an input/output interrupt (Step l) 2L queuing The processing is as shown in Fig. 10. S B C':, VQ corresponding to the relevant route of I-[G
j Pi 1 ~ (current I, 0 go, VQO) to Sera 1 ~,
(Step, 30 ] ), V of p CW of the route
QP1~ is tested (step: 302). If Qpill- of 1) CW in the current cough The end of that f
In order to cue to ike e, i"i at the final queue position at 13u, sunawachi, l-Q TJ A ni'3
7J'J SajL Tail device (1) Remember NQUΔ corresponding to this route in SI3CII, that is, the device address of the next position of the queue, and set it to Jn<byte, which is newly queued this time: yi setting 1. of pcw is stored in step 30'3). QUΔ is also changed to the device 11C address (step 304).
. If PCVJ's VQ pin 1~ is 0, AL. This shows that no one has queued 1 on this J route, so set the vQ bit (stenbu++35
), the device address to be queued this time is F Q 'UΔdoL
Q Seven I- to both sides of L5 (step 30r,
;),. Next, the I/O requests queued in each IY path are taken out of the queue and processed.
1. When the operation of that route is completed and it becomes usable, the operation of PCW is
3 After recess 1 ~ (step 201), V in PCW
("Test lpi1- (step 2()2).V
Q or O, IL indicates that no one is queued on the route, and then 1. processing is not performed. If VQ is 1, it is divided into Q and A in PCW.
Step 20
3) Check its status (step 204). And, it is still pending startup and is not being started via another route,
AND: There is no waiting for the device to end, and it is (step 20
8), after taking out the queue or IJ from this device 7 and performing dequeue processing (step 209), use this route to
Attempt to start 0D5 (steps 210-212). If this device has already started successfully in the 1iL path of the pond and the operation 1: is open 4i'i, J is running or has already finished, then S B C] - Since the activation of 1 is pending, this device is removed from the queue (step 205), and if there is another device in the queue, A41
(step 206), check the status of the device and perform step III. If there is no registered device, the PCW is reset to the VQ pin 1 and the process ends (step 207). If the device taken out from the queue is starting up on another route or is waiting for the device to finish, after dequeuing the device (step 213),
Queue to the end of the queue three times, (Step 2)
/]), newly registered with I7Q U A, 4t S B
Let's move on to CH processing. The dequeue process is as shown in No. 1121. First S
■Reset QPino 1~ corresponding to the relevant route of B CH (step 401); SP Cw's FQU
Interchange A and LQUA (step 102)
), , and if F Q tJ A and I-Q U A are the same value and JI. Since that device was the only device in the queue at u bQ, sa Jt, 1-) Reset the vQ pin 1- on the CW to indicate that the queue is empty. Become. 1. ``QUA and I-QUA do not match: I('' indicates that there are two or more devices in the queue,
Q IJ. lUsukoeli? S B C
N Q tJ corresponding to the relevant route of I
The first shift is made to be a small FQUA (step 1103). [Effects of the Invention] According to the present invention, an input/output processing request for one input/output device is queued directly to the '8 path leading to that input/output device, which eliminates the conventional concept of logical 9A/channel. It eliminates the need for hardware ↓ and t for support 1-, and when dequeuing, it is possible to directly extract the input/output device address for each :If, path queue or 1:), improving the dequeue processing speed. be able to.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an example of a system configuration according to the present invention, and FIG. 2 is a block diagram showing tables of information included in sub-channels. ), (b) is the second
Some of the information shown in the figure +i'i' 1iHfIf diagram of some bytes of rj c w, FIG. 6 is a diagram showing a χ4 correspondence table of device addresses and subchannels, and FIG. 7 is a diagram showing l'i! of memory.
J example t! : Show 1?1. 1st'N21 (a), (b
), (c) is a comprehensive processing flow diagram of an operation example according to the present invention, FIG. 1121 is a flow diagram of dequeue processing 1. I... Central processing: device, 2... Input/output processing device, 21
to, ~2 []... connection route (channel), 3. /I...
Input/output control device, 5. Input/output device, 8... Service processor. Fig. 1 Fig. 3 CO) (b) Fig. 5 Off Fig. 8 Fig. 9

Claims (1)

[Claims] (1) In an input/output processing device that connects an input/output device and a central processing unit via multiple paths, a means for queuing input/output requests is provided for each path, and input/output issued from the central processing unit is provided for each path. registering the request with one or more queuing means associated with the relevant input/output device;
An input/output processing device characterized in that a corresponding input/output device is activated using a path that has become available.