JPS60180150A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60180150A
JPS60180150A JP59034463A JP3446384A JPS60180150A JP S60180150 A JPS60180150 A JP S60180150A JP 59034463 A JP59034463 A JP 59034463A JP 3446384 A JP3446384 A JP 3446384A JP S60180150 A JPS60180150 A JP S60180150A
Authority
JP
Japan
Prior art keywords
metal
radiation
semiconductor substrate
plastic material
sealing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59034463A
Other languages
Japanese (ja)
Inventor
Tsutomu Yamaguchi
力 山口
Tadashi Matsumoto
忠 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59034463A priority Critical patent/JPS60180150A/en
Publication of JPS60180150A publication Critical patent/JPS60180150A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce an intrusion to a semiconductor substrate of radiation, and to inhibit the deterioration of characteristics and the generation of trouble by covering the periphery of the semiconductor substrate with a sealing material consisting of a plastic material, covering at least one part of the outside of the sealing material with a metal and grounding the metal. CONSTITUTION:The periphery of a semiconductor substrate 21 is covered with a sealing material composed of a plastic material 22, and one part or the whole of the outside of the sealing material is covered with metals 23, and the metals are grounded 25, thus constituting a semiconductor device. Aluminum or the like is used as the metal 23 and epoxy resin or the like as the plastic material 22. When aluminum in 0.5mm. thickness is used as the metal, the deterioration of characteristics is reduced extremely largely to not more than one tenth of the conventional devices only with the increase of 20% weight through aluminum flight distance is not more than one half the maximum range of the irradiation of radiation.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、放射線環境において、半導体の特性劣化を低
減させた半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device in which deterioration of semiconductor characteristics is reduced in a radiation environment.

（従来技術） 従来のこの種の装置は、セラミックまたはプラスチック
材料をパッケージ材料に使用していた。Prior Art Conventional devices of this type have used ceramic or plastic materials for the packaging material.

第１図にセラミックパッケージを用いた例を示す。Figure 1 shows an example using a ceramic package.

半導体基板１が実装されているセラミツクツくツケージ
２は、セラミックパッケージと熱膨張係数のはげ等しい
金属３により気密封止されている。A ceramic shoe cage 2 on which a semiconductor substrate 1 is mounted is hermetically sealed with a metal 3 having the same coefficient of thermal expansion as the ceramic package.

このような装置を放射線環境で使用すると、電子や陽子
等の放射線がパッケージを透過して、半導体基板にいた
り、その特性劣化やあるいは故障を発生させる。また、
照射放射線の最大飛程より薄い金属３に、放射線を照射
すると、その放射線が金属に入射する前に持っていたエ
ネルギよシも低エネルギの放射線が多数再放射され、特
性劣化が加速される。また、最大飛程よシ厚い金属では
放射線のシールド効果が期待できる反面、制動放射によ
る放射線で特性劣化や、半導体装置が大幅に重量増加す
る欠点を有している。When such a device is used in a radiation environment, radiation such as electrons and protons passes through the package and reaches the semiconductor substrate, causing its characteristics to deteriorate or break down. Also,
When a metal 3 that is thinner than the maximum range of the irradiated radiation is irradiated with radiation, a lot of radiation having lower energy than the radiation had before it was incident on the metal is re-radiated, accelerating the deterioration of characteristics. Furthermore, while metals that are thicker than the maximum range can be expected to have a radiation shielding effect, they have the disadvantage that radiation due to bremsstrahlung radiation deteriorates the characteristics and significantly increases the weight of the semiconductor device.

一方、第２図に示すプラスチック材料１２を封止材料と
する半導体材料１１では、照射放射線よシ低エネルギの
放射線の再放出や制動放射による放射線はほとんど発生
しないが、放射線に対するシールド効果が期待できない
ため、同様に特性劣化はまぬがれない欠点を有している
。On the other hand, with the semiconductor material 11 shown in FIG. 2, which uses the plastic material 12 as the sealing material, almost no radiation is generated due to re-emission of low-energy radiation or bremsstrahlung radiation, but no radiation shielding effect can be expected. Therefore, it also has the disadvantage of unavoidable characteristic deterioration.

本発明はこれらの欠点を除去するために提案されたもの
で、放射線の半導体基板への侵入を減少させ、特性劣化
や故障の発生を抑えた半導体装置を提供することを目的
とする。The present invention was proposed in order to eliminate these drawbacks, and an object of the present invention is to provide a semiconductor device in which the penetration of radiation into a semiconductor substrate is reduced, and the deterioration of characteristics and occurrence of failure are suppressed.

（発明の構成） 上記の目的を達成するため、本発明は半導体基板の周囲
をプラスチック材料からなる封止材料で櫟い、かつその
外側の少くとも一部を金属で覆い、該金属をアースする
ことを特徴とする半導体装置を発明の要旨とするもので
ある。(Structure of the Invention) In order to achieve the above object, the present invention surrounds a semiconductor substrate with a sealing material made of a plastic material, covers at least a part of the outside with a metal, and grounds the metal. The gist of the invention is a semiconductor device characterized by the following.

次に本発明の実施例を添附図面について説明する。なお
実施例は一つの例示であって、本発明の精神を逸脱しな
い範囲で、種々の変更あるいは改良を行いうろことは云
うまでも々い。Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

第３図は、本発明の一実施例であって、図中２１は半導
体基板、２２はプラスチック材料、２３は金属で、アー
ス線２５により半導体装置のアースに接続されている。FIG. 3 shows an embodiment of the present invention, in which 21 is a semiconductor substrate, 22 is a plastic material, and 23 is a metal, which are connected to the ground of the semiconductor device by a ground wire 25.

２４はリード線、２５はアース線を示す。なお金属２３
としては例えばアルミニウム、プラスチック材料２２と
して例えばエポキシ樹脂を用いている。24 is a lead wire, and 25 is a ground wire. Furthermore, metal 23
For example, aluminum is used as the material 22, and epoxy resin is used as the plastic material 22, for example.

スタティックメモリに第３図の構造を適用し、放射線を
照射した結果を第１表に示す。この実施第　１　表 例では、金属として厚さ０．５鮎のアルミニウムを使用
した例であシ、照射放射線の最大飛程の半分以下である
にもかかわらず、従来装置の高々２０チの重量増加であ
シ、かつ特性劣化が従来装置の」−以下と極めて大きく
減少している。さらに、Ｏ シールド効果を高めるために、金属の厚さを増すことも
さしつかえない。Table 1 shows the results of applying radiation to a static memory using the structure shown in FIG. In this implementation example in Table 1, aluminum with a thickness of 0.5 mm is used as the metal, and although the maximum range of the irradiated radiation is less than half, the weight of the conventional device is at most 20 inches. However, the deterioration of characteristics has been significantly reduced to less than that of the conventional device. Furthermore, it is also possible to increase the thickness of the metal in order to enhance the O 2 shielding effect.

また第４図は本発明の他の実施例を示すもので、図にお
いて３１は半導体基板、３２はプラスチック、３３は金
属、３４は空間、３５はアース線、３６はリード線を示
す。図に示すようにプラスチック材料と、半導体基板と
の間に空間３４をもうけると、放射線によシブラスチッ
ク材料が帯電しても、直接半導体基板と接していないた
め、特性劣化がさらに発生しにくくなる。なお金属とし
てはプラスチック材料の外側の一部または全部を覆って
もよい。FIG. 4 shows another embodiment of the present invention, in which 31 is a semiconductor substrate, 32 is plastic, 33 is metal, 34 is space, 35 is a ground wire, and 36 is a lead wire. As shown in the figure, if a space 34 is provided between the plastic material and the semiconductor substrate, even if the plastic material is charged by radiation, it is not in direct contact with the semiconductor substrate, so deterioration of characteristics will be less likely to occur. . Note that the metal may cover part or all of the outside of the plastic material.

（発明の効果） 以上、説明したように本発明によれば、半導体基板の表
面上に空間を有するか、もしくは々い場合でも、その周
囲をプラスチック材料からなる封止材料で覆い、かつそ
の外側の一部または全体を金属で゛覆い、これをアース
した構造の半導体装置であるため、放射線による特性劣
化を低減させる利点がある。(Effects of the Invention) As described above, according to the present invention, if there is a space on the surface of the semiconductor substrate, or even if it is, the surrounding area is covered with a sealing material made of a plastic material, and the outside of the space is covered with a sealing material made of a plastic material. Since the semiconductor device has a structure in which the semiconductor device is partially or entirely covered with metal and is grounded, it has the advantage of reducing characteristic deterioration due to radiation.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来の半導体装置の断面図、第３図及
び第４図は本発明装置の一実施例の断面図を示す。 １．１１．２１．３１・・・半導体基板、２・・・セラ
ミック材料、１２　．２２．３２・・・プラスチック材
料、３，２３．３３・・・金属、４．３４・・・空間、
２５゜（５） ３５・・・アース線、２４　．３６・・・リード線特許
出願人 （６） 第１図 第３図 第４図FIGS. 1 and 2 are sectional views of a conventional semiconductor device, and FIGS. 3 and 4 are sectional views of an embodiment of the device of the present invention. 1.11.21.31...Semiconductor substrate, 2...Ceramic material, 12. 22.32...Plastic material, 3,23.33...Metal, 4.34...Space,
25° (5) 35...Ground wire, 24. 36... Lead wire patent applicant (6) Figure 1 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] （１）半導体基板の周囲をプラスチック材料からなる封
止材料で覆い、かつその外側の少くとも一部を金属で覆
い、該金属をアースすることを特徴とする半導体装置。(1) A semiconductor device characterized in that a periphery of a semiconductor substrate is covered with a sealing material made of a plastic material, at least a part of the outside of the semiconductor substrate is covered with a metal, and the metal is grounded. （２）半導体基板表面とプラスチック材料との間に空間
を有することを特徴とする特許請求の範囲第１項記載の
半導体装置。(2) The semiconductor device according to claim 1, characterized in that there is a space between the semiconductor substrate surface and the plastic material.
JP59034463A 1984-02-27 1984-02-27 Semiconductor device Pending JPS60180150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59034463A JPS60180150A (en) 1984-02-27 1984-02-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59034463A JPS60180150A (en) 1984-02-27 1984-02-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60180150A true JPS60180150A (en) 1985-09-13

Family

ID=12414940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59034463A Pending JPS60180150A (en) 1984-02-27 1984-02-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60180150A (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5369056A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US5367766A (en) * 1990-08-01 1994-11-29 Staktek Corporation Ultra high density integrated circuit packages method
US5377077A (en) * 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5394014A (en) * 1990-11-28 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device improved in light shielding property and light shielding package
US5420751A (en) * 1990-08-01 1995-05-30 Staktek Corporation Ultra high density modular integrated circuit package
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5448450A (en) * 1991-08-15 1995-09-05 Staktek Corporation Lead-on-chip integrated circuit apparatus
US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
WO1996022669A2 (en) * 1995-01-13 1996-07-25 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US5572065A (en) * 1992-06-26 1996-11-05 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
DE4143494C2 (en) * 1990-11-28 1998-05-14 Mitsubishi Electric Corp Semiconductor device with reduced housing thickness and wt.
US5801437A (en) * 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5945732A (en) * 1997-03-12 1999-08-31 Staktek Corporation Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
US6144108A (en) * 1996-02-22 2000-11-07 Nitto Denko Corporation Semiconductor device and method of fabricating the same
US6205654B1 (en) 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US6262362B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Radiation shielding of three dimensional multi-chip modules
US6261508B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Method for making a shielding composition
US6326687B1 (en) * 1998-09-01 2001-12-04 Micron Technology, Inc. IC package with dual heat spreaders
US6368899B1 (en) 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
US6455864B1 (en) 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US6613978B2 (en) 1993-06-18 2003-09-02 Maxwell Technologies, Inc. Radiation shielding of three dimensional multi-chip modules
US6720493B1 (en) 1994-04-01 2004-04-13 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US7382043B2 (en) 2002-09-25 2008-06-03 Maxwell Technologies, Inc. Method and apparatus for shielding an integrated circuit from radiation
US7696610B2 (en) 2003-07-16 2010-04-13 Maxwell Technologies, Inc. Apparatus for shielding integrated circuit devices

Cited By (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550711A (en) * 1990-08-01 1996-08-27 Staktek Corporation Ultra high density integrated circuit packages
US6049123A (en) * 1990-08-01 2000-04-11 Staktek Corporation Ultra high density integrated circuit packages
US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5377077A (en) * 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5566051A (en) * 1990-08-01 1996-10-15 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5420751A (en) * 1990-08-01 1995-05-30 Staktek Corporation Ultra high density modular integrated circuit package
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
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