JPS60175161A - Memory access system - Google Patents

Abstract

PURPOSE:To form easily a program and to improve a processing speed by applying the different number of bits to an address part for an instruction word and forming a memory access means in addition to an access means using a conversion table. CONSTITUTION:The 1st memory access means uses the conversion table 3. The 2nd memory access means is formed independently from the 1st means and uses an instruction word address part consisting of 18 bits increased by 2 bits from an address part handled by the 1st means. Since 5 bits are assigned to a logical page No., it is unnecessary to convert the logical page No. into a physical page No. by referring the conversion table 3. The logical page No. can be made to correspond to the physical page No. of 7 bits originally, so that the reference of the conversion table 3 is unnecessary and only a memory protecting table 4 may be referred when the physical address is to be found out.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory access method, and particularly to a memory access method in an electronic computer including a central processing unit and a memory device.

(Prior art) The instruction word used in the electronic meter consists of an instruction code part,
It consists of an address section that specifies the address of a memory device or register in which data to be operated is stored. In addition, multiple bits can be stored in one memory device.
An address is assigned to each word of memory.

Therefore, when specifying absolute addressing, the address field of an instruction word is assigned the number of bits that can specify the address of the maximum number of words in the memory device, and as the memory capacity increases, the number of bits in the address field increases, and the entire instruction word becomes longer. The memory device used to store this information also has a significant impact on large devices. For this reason, efforts have been made to reduce the number of bits in the address field so that it can be specified directly and a large capacity memory device can be used even if the number of addresses is small.

Figure 1 is an explanatory diagram of the conventional memory access method implemented when using a memory device with a capacity of about half this size. In this example, the number of bits in the address field included in the instruction word is 16 bits. This address part is called a logical address, and when accessing the memory device (MUM) 2, this address part is guided to the logical address register 1. However, this number of bits allows direct access to only 64 words of memory.

On the other hand, a memory device has a capacity of 256 words and must be able to access any part of this. For this reason, a memory of 256 words is divided into 128 pages of 2 words each, and each page has a physical page number (P
PN) is specified by 7. The 16-bit logical address is divided into a 5-bit logical page number (LPN) and an 11-bit displacement (DISP). Furthermore, it has a conversion table 3 capable of converting each of the 32 entries represented by the 5-bit logical page number into a 7-bit physical page number. This conversion table 3 is made up of high-speed memory, etc., and when creating a program, the physical page number of the instruction word or operand word to be used next is checked in advance, and the conversion table 3 is read by the program before that program. It is used for rewriting or rewriting by the program management operating system. Note that this conversion table 3 has a 1-bit memory protection bit corresponding to a 7-bit physical page number.
When rewriting the page, refer to the memory protection table 4 set based on the purpose of use for each physical page number at system startup, and write whether or not rewriting is possible. Writing to prohibited pages is prevented when reading and accessing the memory.

It should be noted that the 11 bits representing the displacement in the logical address represent the word number of the words in the physical page 2.

Therefore, in this computer, in order to access the memory device from the logical address specified by the instruction word, use the conversion table 3 to extract the physical page number 5 from the logical page number l, and create the physical address along with the displacement value. I will do it. Moreover, if the conversion table 3 that has been rewritten once does not have a physical page number, it is necessary to rewrite the conversion table 3 and add the physical page number as described above. It also has the disadvantage of telling you when it falls.

(Object of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a means for accessing memory other than through a conversion table.
An object of the present invention is to provide a memory access method that facilitates program creation and improves processing speed.

(Structure of the Invention) The memory access method of the present invention refers to a conversion table from a logical address specified in an instruction word in an electronic computer that processes data stored in a memory device according to an instruction stored in the memory device. a first access means for creating a physical address of the memory device and accessing the memory;

The second access means accesses the memory by using the address specified in the instruction word as the physical address of the memory device, and the memory device protection means corresponds to each R of the first and second access means. It is characterized by

(Embodiments of the Invention) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is an explanatory diagram of an embodiment of the present invention, in which the first means of memory access is the same as that explained in FIG. 1, and is based on a method using a conversion table 3. The second means of memory access is provided separately from the first means, and in this example, the address part of the instruction word is handled by the first means.
We deal with bits increased to 18 bits. For this reason, conventionally, the instruction word was made up of 24 bits and consisted of one word, but when directly specifying a physical address, a word that requires the length of two words is used. It happens. However, in this case, as explained in Figure 1, there is no need to allocate 5 bits as a logical page number and convert it to a 7-bit physical page number by referring to conversion table 3. Since it can correspond to 7 bits, there is no need to refer to the conversion table 3, and it is only necessary to refer to the memory protection table 4 when calculating the physical address.

In this case, all instruction words are made into 2 words and the conversion table 3 is not used at all. Instead, the method used in conjunction with the first method is only a conversion table with a limited program, and a large number of commands can be used without rewriting the table. This is because if the memory at the physical address of the part can be accessed, there is no reduction in processing speed due to the rewriting operation, and the troublesome task of creating a program is reduced, making it possible to reduce the memory capacity required to store the program. Incidentally, in the processing when this type of computer is used in an electronic exchange, if the instruction words stored in the memory device 2 are less than 32 words and the data words are more than 200 words, most of the processing is carried out in the memory. A first means is available, using a single translation table, which is performed on a particular 64 word 2, including a work area of 64, and has a relatively infrequent access to a wide range of data words.

FIG. 3 is a block diagram showing an example of the second means of memory access described above. The 18-bit address register 5 is composed of 7 bits for the physical page number and 11 bits for the displacement, and the contents can be read as they are. It is given to the memory device 2 as address information.

t fcs The 7-bit physical page number is also given to the memory protection method 4 (stored in a high-speed memory, for example) set corresponding to the page at the time of system startup to obtain a 1-bit output indicating whether or not rewriting is possible. This output indicates that rewriting is allowed if the logical value is ``O'', and that rewriting is prohibited if the logical value is ``1'', and the first logical product of this output signal and the write signal is input. If the logic value of both signals is 11'', the gate circuit 6 interrupts the sequence control circuit (SQC) 8 to perform erroneous processing.On the other hand, the negation signal and write signal of the output from the memory protection table The logical value @'0'' that is input to the AND gate circuit 7 of 2 and the output of the protect table allows rewriting.
If so, a write instruction is given to the memory device. In addition, data for writing is given to the memory device 2 at the time of writing, and is rewritten by application of a memory access signal, and at the time of reading, a read output is similarly obtained by this one memory access signal.

(Effects of the Invention) As described above in detail, the present invention provides a different number of bits to the address part of an instruction word and provides a means of accessing memory other than the conversion table, thereby facilitating program creation and processing. This has the effect of increasing speed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a conventional memory access method, and FIG. 2 is an explanatory diagram of an embodiment of the memory access method according to the present invention.
FIG. 3 is a block diagram showing an embodiment of the second means of the access method in FIG. 2. 1...Logical address register, 2...
Memory device [(MEM), 3...Conversion table, 4...Memory protection table, 5...
・Physical address register, 6゜7......AND gate circuit, 8......Sequence control circuit (8QC
) out.

Claims (1)

[Claims] In an electronic computer that processes data stored in the memory device according to an instruction stored in the memory device, a physical address of the memory device is created by referring to a conversion table from the logical address specified in the instruction word and stored in the memory. A first access means for accessing, a second access means for accessing memory using the address specified in the instruction word as a physical address of the memory device, and a memory corresponding to each of the first and second access means. A memory access method comprising a device protection means.