JPS60174536A - Echo canceler - Google Patents

Abstract

PURPOSE:To converge the improvement amount of echo return loss in a short time by adding a loop gain control circuit to a normal echo canceler. CONSTITUTION:The loop gain control circuit 20 is connected between the output side of a DELTAH generating circuit 10 and another output side of the circuit 10. This circuit 20 is constituted by cascading an absolute value circuit, linear filter for averaging, and a clip circuit. An error of an input signal increases because the difference between the pulse transmission function of an echo path 5 and that of the H register in the echo canceler is large, and the correction amount of the circuit 10 also increses. On the other hand, the difference in transmission function decreases abruptly with time and the error signal becomes less smoothly, so the improvement amount of echo return loss also converges.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention relates to echoes caused by impedance mismatching of two-wire/four-wire conversion circuits in long-distance telephone lines, or wrap-around echoes between speakers and microphones that occur in remote telephone conferences, etc. It is related to a echo canceller that cancels.

(Conventional technology) A conventional device of this type will be explained using figures.

Figure 1 shows an example of the configuration of a conventional echo canceller.
In the diagram, 1 is the received signal input terminal, 2 is the received signal output terminal, 3 is the transmitted signal input terminal, 4 is the transmitted signal output terminal, 5
is an echo path; 6 is a subtractor; 7 is a convolution integrator; 8 is an An H register and an H register update circuit are blocks that update the contents of the H register by adding a new correction amount for each sample; 10 is a ΔH generation circuit that calculates the correction amount; 11 is an X
A square sum circuit calculates the sum of squares of the contents of the register, 12 is an input terminal for setting a loop gain α, and 13 is a transmission line.

The ΔH generation circuit 10 multiplies the output of the subtracter 6, that is, the error output signal and the loop gain α, and also outputs the sum of squares circuit 1.
In step a2, the result of division by the output signal of 1 is multiplied by the output of the KX register 8 to calculate the correction amount. This configuration is well known as an echo canceler using the standard learning identification method, and its operation is not detailed in IEICE Network [Applications of Digital Signal Processing] pages 216 to 221, so the explanation here is omitted. Omitted. Also, there is a configuration similar to this that excludes the sum of squares circuit 11, but
Basically, it operates in the same way as the echo canceller according to the standard learning identification method and is included in this, so below we will explain the case based on the standard learning identification method. In addition, the first
In the figure, it is assumed that A/D and D/A converters are inserted as appropriate depending on the type of signal on the echo path side and the transmission path side, and that the operation of the echo canceller -&L4 is digitally processed.

Now, in the standard learning identification method, the formula for sequentially modifying the estimated impulse response vector Hj, which represents the contents of the H register as an N-dimensional vector, is given by the following formula.

Here, xj is time t = jT (T - sample interval) K
The input signal vector ej in is the subtractor's force or error output signal.

In this conventional echo canceller configuration, the loop gain α
Since is given as a fixed constant, this will be referred to as the curved loop gain method. In addition, in order for the echo canceller to guarantee stable adaptive operation, 0〈α
<It needs to be 2.

Furthermore, considering the amount of echo cancellation and the convergence time, the condition for the loop gain α is 0<α≦1 (■).

According to the configuration based on this standard learning identification method, the amount of echo cancellation and the convergence time are in a trade-off relationship with respect to a constant loop gain α. That is, in order to increase the amount of echo cancellation, α must be chosen smaller, and in order to shorten the convergence time, α must be set to a larger value.

FIG. 2 is a diagram for explaining the convergence characteristics of a conventional echo canceller, and shows the above relationship with ERLE (echo return loss improvement amount) plotted on the vertical axis and time t plotted on the horizontal axis.

Therefore, the conventional device of this type has the disadvantage that it is not possible to improve the echo cancellation amount and the convergence time at the same time for a constant α.

(Object of the Invention) In order to eliminate the above-mentioned drawbacks, the present invention shortens the convergence speed and secures the required amount of echo cancellation by making the modified loop gain α variable. Explain in detail.

(Structure and operation of the invention) FIG. 3 is a block C1, Y diagram of an embodiment showing the structure of the present invention, and 1 to 131 in the figure are the same as those in FIG. 1. 20 is a loop gain control circuit which inputs the error signal ej, and is a loop gain control circuit which inputs the error signal ej of the present and past samples eLej-1+...+ej r+...(r
The echo canceller has an averaging function for vc (i positive integer) and a function of outputting a loop gain that ensures stable adaptive operation of the echo canceller.

FIG. 4 shows a first embodiment showing details of the block of the loop gain control circuit 29 shown in FIG. 3, and 21 is a signal input terminal to which an error signal ej is input. 22 is a square circuit, and 23 is a linear filter, such as a moving average filter or an integrator that can be configured cursively. 24 is a signal output terminal.

The configuration of the echo canceller of the present invention has a loop gain of α
From αj,! :This is the same as the conventional case where α is fixed, except that the error signal ej changes over time depending on the history of the error signal ej.

Since the echo canceller of the present invention is configured as described above, if the convergence operation is started for the input signal xJ at time j==0, immediately after the start of convergence, the pulse transfer function of the echo path 5 and the echo canceller Since the difference in the pulse transfer functions of the H registers 9 (specifically, the absolute value of the difference in impulse response vectors) is large, the error signal ej is also large. Therefore, at this time, the correction amount which is the output of the correction amount ΔH generation circuit 10 also increases because the output of the square sum circuit 11 increases in accordance with the amplitude of ej. On the other hand, since the correction amount is increased, the difference in pulse transfer function decreases rapidly over time compared to the fixed loop gain method, and the error signal ej
also gets smaller faster. Therefore, the amount of correction becomes smaller accordingly, and the echo return loss improvement amount (ERLE) converges to ERLE when α is small.

FIG. 5 is a second embodiment showing details of the blocks of the loop gain control circuit 20 in FIG. 3, and 21 to 23 are the same as those in FIG. 4. Reference numeral 25 denotes a first clipping circuit that clips to a value within the range of αj in which the linear filter output echo canceller should operate stably, that is, 0≦αj≦αmax≦1, and 26 C a signal output terminal. Also, the first glue 1 knob circuit 25 in FIG.
(c) can be replaced by a second clipping circuit having a lower limit value and an upper limit value. In this case, αj satisfies 0≦αmin≦αj≦αmax≦1. In this way, it is possible to prevent the adaptive operation from stopping or the transient characteristics from deteriorating due to αJ becoming too small or too small, and it is also possible to increase the degree of freedom in designing the filter in the loop gain control circuit. .

FIG. 6 shows a third embodiment showing details of the blocks of the loop gain control circuit 20 in FIG.
It is similar to the figure. 27 is a circuit (quantizer to the 11th power of 2) that outputs a positive number and a value to the power of 2 less than 2 (2n; n1l-1: a non-negative integer) using the clipping circuit shown in FIG.
28 is a signal output terminal. Here, the 2 over 1] power quantizer 27 has a function of outputting a signal obtained by performing a quantization operation such as rounding with the next lower bit of the first appearing 1 for an input of 1 or less expressed in binary. This is a circuit with Therefore, the output of the power of 2 quantizer 27 becomes a value of the power of 2. The use of a kneader has the advantage that the ΔH generation circuit does not actually require a multiplier to multiply the loop gain, and only requires a scaling operation.

It is also possible to replace the squaring circuit 22 in FIGS. 4 to 6 with an absolute value circuit that outputs the absolute value of the input signal. In this case, since there is no square circuit, there is an advantage that the circuit configuration is simple.

Furthermore, when realizing an echo canceller, the circuit configuration differs depending on the signal format inside the circuit, such as fixed point, floating point, calculation format, etc., but the present invention improves the convergence characteristics of the conventional fixed loop gain method regardless of these. Is possible.

FIG. 7 is a diagram illustrating a comparative example of the convergence characteristics of the echo canceller of the present invention and the convergence characteristics of a conventional echo canceller confirmed by computer simulation. The configuration of the loop gain control circuit 20 consists of a cascade connection of an absolute value circuit, a linear filter that performs uniform averaging, and a second clip circuit. In this example, the number of taps N of the adaptive filter that performs convolution integration, the loop gain generation formula, and the upper and lower limits of the clipping circuit are N = 1000 αj = K (l ej14-lej-II) αma!
=1. αml. =025. As will be seen, compared to the conventional fixed loop gain method A, the echo canceller of the present invention has exactly the same characteristics as α=1 of the fixed loop gain method at the time of initial convergence, as shown in B, and In steady state, it exhibits echo cancellation characteristics of α=0.25 for the fixed loop gain method.

(Effects) As explained above, according to the configuration of the present invention, by simply adding a few circuits to the conventional echo canceller circuit, convergence operation can be performed to significantly improve the ERLE within a short time, and the convergence operation can be performed in a steady state. can obtain sufficient ERLE, so it has the advantage of fast convergence speed in the case of α-1 in the conventional fixed loop gain method, and the advantage of fast convergence speed when α is small.
It has the advantage of combining the advantages of both methods in that RLE can be increased.

In addition, with an echo canceller, when two parties talk at the same time (double talk), the echo path estimation operation is disturbed by noise from the near-end talker, and double talk detection control is required to prevent this. According to the configuration of the invention, since the time for convergence operation is shortened, ER due to occurrence of double talk can be reduced.
There are advantages in that the probability of LE deterioration occurring is reduced, and the degree of BRLE deterioration due to double talk can be suppressed by designing the order of the filter of the loop gain control circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a conventional echo canceller, FIG. 2 is a diagram showing convergence characteristics of a conventional echo canceller, FIG. 3 is a block diagram of an embodiment showing the configuration of the present invention, and FIG. 5 and 6 are first, second, and third circuits showing details of the loop gain control circuit of FIG. 3, respectively.
FIG. 7 is a diagram for comparing and explaining the convergence characteristics of the present invention and the conventional echo canceller. 1 ...... Reception signal input terminal, 2 ...
...Receive signal output terminal, 3...Transmit signal input terminal, 4...Transmit signal output terminal, 5...Echo path, 6・・・・・・
・・・Subtractor, 7・・・・・・Convolution integrator, 8・・・・・・X register, 9 ・・・・・・・・・
...H register and H register update circuit, 10.
...... ΔH generation circuit, 11...
... Square sum circuit, 12 ...... Loop gain setting terminal, 13 ...... Transmission line, 20 ...
......Loop gain control circuit, 21...
...Signal input terminal, 22...Square circuit, 23...Linear filter, 24.26
．． 28... Signal output terminal, 25. ...
...Clip circuit, 27...2 squared quantization gain. Patent applicant: Nippon Telegraph and Telephone Public Corporation. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Sabahama t (θC) Procedural amendment (voluntary) Revenue stamp amount'' 1IpfL1.9□gJi26□ Commissioner of the Japan Patent Office Zhi Manabu Ka 1, Indication of matter f'1 Patent Application No. 1982-2'9612 2,
Name of the invention: Echo Canceller 3, Correcting person's relationship with tenant 1 Applicant's address: 1-1-6 Uchisaiwai-cho, Chiyo H1-ku, Tokyo (422) Nippon Telegraph and Telephone Public Corporation official name: Tsune Shinfuji 4 , Agent Address: 143-3-5 Nishi-Shinbashi 3"J", Minato-ku, Tokyo 105,
The number of inventions will increase due to the amendment. (4) Figure 7 of the drawing is corrected as shown in the attached sheet. Document stating the above claims Claims (1) An X register that stores N samples (N: a positive integer) of a received input signal, and an H register that stores an estimated parameter of an impulse response of an echo path. , a multiplier and a summation circuit that performs a convolution operation between the contents of the X register and the contents of the H register, and a subtraction circuit that subtracts the convolution output signal, which is a pseudo echo signal, from a transmission input signal that includes an echo signal. an adder connected to add a correction amount of the estimated parameter to the contents of the H register of the red sample, and update and store the result as the contents of the H register of the next sample; and the output signal of the subtracter which is an error signal. A nonlinear filter (loop gain control circuit) that takes as input, outputs the weighted average value or integral value for the error signal series of the current and past samples (averaging function), and has a non-negative output signal. and. The error signal is a first input signal, the output signal of the X register is a second input signal, the output signal of the loop gain control circuit is a third input signal, and these first, second, and third inputs An echo canceller comprising a correction amount generation circuit that sequentially generates and outputs a product of signals as a correction amount of the estimated parameter. (2) Claim (1) characterized in that the nonlinear filter (loop gain control circuit) is replaced with a cascaded configuration of an error signal square circuit and a linear filter having an averaging function. echo canceller. (3) Cascade connection configuration of a nonlinear filter (loop gain control circuit) with a squaring circuit, a linear filter with an averaging function, and a first clip circuit whose output upper limit value is 1 or less The echo canceller according to claim (1), characterized in that the echo canceller is replaced with . (4) The nonlinear filter (loop gain control circuit) is a squaring circuit, a linear filter with an averaging function, and a second output whose lower and upper limit values are 0 or more and 1 or less. The echo canceller according to claim 1, characterized in that the echo canceller is replaced with a cascade connection configuration with a clip circuit. (5) The echo canceller according to claim (2), (3), or (4), characterized in that the square circuit is replaced with an absolute value circuit. (6) A circuit (2+11 quantizer) that outputs the first or second clip circuit as a positive number and a value of 2 to the 11th power (2-"; n is a non-negative integer) that is less than or equal to 1. Claims (3) and (4) characterized in that
or (5). (7) A sum of squares circuit that calculates the sum of squares of N samples of the contents of the X register, and a reciprocal circuit that calculates the reciprocal of the output signal of the sum of squares circuit, and an output signal of the reciprocal circuit. is connected to a fourth input signal terminal of the correction amount generation circuit, and the correction amount generation circuit outputs the error signal, the output signal of the X register, the output signal of the loop gain control circuit, and the fourth input signal. It has a function of outputting the product of the signals of four parties, and uses the output signal of the correction amount generation circuit as the correction amount of the estimated parameter.
), (2), (3), (4), (5)
or (6). Figure 7 4 F5 Jt/(sec)

Claims (1)

[Claims] (1) An X register that stores N samples (N: a positive integer) of a received input signal; an H register that stores an estimated parameter of an impulse response of an echo path; and the contents of the X register and the a multiplier and a summation circuit that performs a convolution operation with the contents of the H register; a subtracter that subtracts the convolution output signal, which is a pseudo echo signal, from a transmission input signal that includes an echo signal; An adder connected to add the correction amount of the estimated parameter to the contents of the register and update and store it as the contents of the H register of the next sample; The weighting for the error signal series of samples is performed by using a nonlinear filter (loop gain control circuit) that outputs an average value or an integral value (averaging function) and has a non-negative output signal; 1 input signal, the output signal of the X register as the second input signal, and the output signal of the loop gain control circuit as the third input signal, and the product of these first, second, and third input signals is the An echo canceller comprising a correction amount generation circuit that sequentially generates and outputs correction amounts for estimated parameters. (2) Claim (1) characterized in that the nonlinear filter (loop gain control circuit) is replaced with a cascaded configuration of an error signal square circuit and a linear filter having an averaging function. echo canceller. (3) Two nonlinear filters (loop gain control circuits)
A patent claim characterized in that the multiplication circuit is replaced with a cascade-connected configuration of a linear filter having an averaging function and a first clip circuit whose output upper limit value is 1 or less. The echo canceller described in item (1) above. (4) Two nonlinear filters (loop gain control circuits)
The IPI characteristic is that the multiplier circuit is replaced with a cascade-connected configuration of a linear filter having an averaging function and a second clip circuit whose lower and upper limits of the output of the linear filter are values of 0 or more and 1 or less. Claim No. (1)
Echo canceller described in section. (5) The echo canceller according to claim (2), (3), or (4), characterized in that the square circuit is replaced with an absolute value circuit. (6) First Or use the second clip circuit as a positive number and 1
Claims (3) and 3) are characterized in that the circuit is replaced with a circuit (a power of 2 quantizer) that outputs the following power of 2 value (2-nin is a non-negative integer): The echo canceller according to item (4) or item (5). (7) A sum-of-squares circuit that calculates the sum of squares for N samples of the contents of the X register, and a reciprocal of the output signal of the sum-of-squares circuit. The output signal of the reciprocal circuit is connected to the fourth input signal terminal of the correction amount generation circuit, and the correction amount generation circuit calculates the error signal, the output signal of the X register, and the It has a function of outputting a product of four signals: an output signal of the loop gain control circuit and a fourth input signal, and is characterized in that the output signal of the correction amount generation circuit is used as the correction amount of the estimated parameter. Claim No. 1
), (2), (3), (4), (5)
The echo canceller described in item 1 or item 6).