JPS60168240A - Interrupt processing circuit - Google Patents

Abstract

PURPOSE:To reduce the number of control lines and to simplify the constitution by using a data bus to report information, which indicates an interrupt factor whose interrupt should be accepted, to all interrupt factors. CONSTITUTION:Interrupt requests I1-I4 generated from input/output ports 1-1- 1-4 are inputted to a register 2 and are transmitted to a priority level giving encoder 4. The encoder 4 transmits an interrupt signal INT to a CPU5 and encodes information having a higher priority level and outputs it as a part of vector information (the first vector information) onto a data bus 6. Input/output ports 1-1-1-4 discriminate whether their own interrupt requests are accepted or not on a basis of the first vector information, and the input/output port whose interrupt request is accepted outputs the second vector information onto the data bus. The CPU5 takes in the first and the second vector information from the data bus 6 and enters into the interrupt processing.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention provides a method for controlling multiple interrupt factors (for example, input/output/-), etc., inside and outside of a two-body device (including a processor, memory, etc.). The present invention relates to an interrupt processing circuit used in a device having the present invention.

When there are multiple interrupt sources (interrupt sources), generally a priority is assigned to each side interrupt source.

When multiple interrupt factors request interrupts at the same time, the one with the highest priority is selected and processed. However, as a practical matter, it is rather rare for a plurality of interrupt factors to generate interrupt requests at exactly the same time, and it is often the case that an interrupt request is generated from another interrupt factor while a certain interrupt processing routine is being executed.

In this case, if the interrupt request is from an interrupt source with a low priority, it will be ignored and processing will continue, but if it is an interrupt request from a high priority interrupt source, processing will continue. A method of interrupting and moving to a new interrupt source processing routine.

So-called priority interrupt
It is desirable to have the function of pt).

Normally, such functions are not performed in hardware (because the circuit size is large and complicated).

It can be included in the main routine by software or processed by O8 (operation system: management program).

[Prior art]

Conventionally, as methods for realizing this type of priority interrupt function, there are known methods that use a daisy chain circuit and methods that use a priority interrupt controller.

In a daisy chain circuit, multiple input/output ports that generate nine interrupt requests are connected in parallel to one interrupt request line, and each input/output port has an input terminal and an output terminal for controlling interrupt priority. and are connected in series so that the control output output from the output terminal of the input/output port of the previous stage becomes the control input input to the input terminal of the input/output port of the next stage, and at a certain input/output port, When the control input input to the relevant input terminal is at the prohibition level, and when the relevant input/output port is transmitting an interrupt signal, the control output output from the relevant output terminal is set to the prohibition level and the input/output from the next stage onwards? - prohibits the client from sending an interrupt signal to the processor even if an interrupt request occurs.

In this way, in a daisy chain circuit, signals for controlling priorities are connected in series through multiple input/output ports, and the control signal from the previous stage's input/output port is taken into its own input/output port.

After processing, it is sent to the input/output port of the second stage.

When the number of connected stages is large, that is, when the number of input/output ports requesting interrupts is large, it takes time for the control signal to be transmitted to the last stage.

Therefore, after the processor accepts the interrupt signal,
After sending a recognition response signal for the interrupt signal to each input/output port, it takes time to send vector information from the input/output port that issued the interrupt signal back to the processor.
The processor will not be able to provide vector information in time.

This has the disadvantage that the number of input/output ports that can be connected is limited.

On the other hand, the priority interrupt controller has the disadvantage of having a complicated two-circuit configuration.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt processing circuit that can expand the number of interrupt factors that can request interrupts to a processor with a simple configuration.

[Structure of the invention]

According to the present invention, in a device having a plurality of interrupt factors inside and outside a main device including a processor, means for sending an interrupt signal to the processor when an interrupt request generated from the interrupt factor is received; In synchronization with a recognition response signal from the processor in response to the interrupt signal, data indicating that an interrupt has been accepted for one of the interrupt factors that generated the interrupt request is sent to the processor. an interrupt processing circuit that uses some lines of the data bus to send part of the vector information (first vector information) sent via the bus to each of the interrupt causes. is obtained.

Then, only the interrupt factor for which the 92 interrupt is accepted due to the first vector information sent via some lines of the data bus transmits the second vector information in synchronization with the recognition response signal. The remaining lines of the data bus are used to send the data to the processor, and the processor:
After fetching these vector information (consisting of first vector information and second vector information) from the data bus and stopping sending of the recognition response signal, interrupt processing for the interrupt cause for which the interrupt has been accepted is executed. do.

[Embodiments of the Invention] Examples of the present invention will be described below with reference to two drawings.

Referring to FIG. 1, one embodiment of an interrupt processing circuit according to the present invention is shown in a block diagram.

In this embodiment, one interrupt factor is an input/output port, and four input/output ports 1-1.1-
2.1-3 and 1-4 are provided. Interrupt requests 1. generated from each of these input/output ports 1-1 to 1-4. ~■
4 is input to the register 2, which takes the timing according to the timing signal φ from the oscillator 3 and then sends the 2 interrupt requests 1 to I4 to the priority encoder 4.

In the priority encoder 4, registers 2 to 9 interrupt request I
Immediately upon inputting I to Step 4, an interrupt signal INT is sent to the processor 5, which encodes information for accepting the input/output port with the highest priority from among the input interrupt requests. Then, the priority encoder 4 encodes this encoded information.

In synchronization with the recognition response signal INTA to the interrupt signal INT from the processor 5, it is output onto the data bus as part of the vector information (first vector information).

Each of the input/output ports 1-1 to 1-4 determines whether or not its own interrupt request is accepted based on the first vector information, and accepts the input/output port that is attached. outputs the second vector information onto the data bus 6 in synchronization with the recognition response signal INTA. At this time.

The lines on which the first vector information outputted from the priority encoder 2 and the second vector information outputted from the input/output port are carried are bit-assigned so that they do not collide on the data bus 6. It is assumed that

The processor 5 receives vector information (first vector information and second vector information) output from the data bus 6 in synchronization with the recognition response signal INTA.

Stops sending the recognition response signal INTA and enters 1 interrupt processing. On the other hand, the priority encoder 4 and each input/output port 1-
1 to 1-4 stop transmitting their respective vector information at the same time as the recognition response signal INTA stops. Furthermore, the input/output port that has received two interrupts also stops sending out one interrupt request.

Next, the operation of the present invention will be explained in more detail with reference to the time chart shown in FIG.

In the initial state, it is assumed that the processor 5 is executing the main program. At time t].

Input/output data) 1-2.1-3 to interrupt request I2. I
3, this interrupt request 12r13 is timed by the timing signal φ from the oscillator 3 in the register 2 and then input to the priority encoder 4.

At this time, the priority encoder 4 sends an interrupt signal INT to the processor 5, and also sends the interrupt signal VI2 of the higher priority input/output r-) 1-2 to accept the interrupt.
encode.

When the processor 5 receives the second interrupt signal INT, it sends a recognition response signal INT to notify that the interrupt is accepted.
A is sent to each input/output port 1-1 to 1-4 and the priority encoder 4. The priority encoder 4 synchronizes with this recognition response signal INTA.

The encoded information VI2 is outputted onto the data bus 6 as part of the vector information V, that is, as first vector information.

Each of the input/output ports 1-1 to 1-4 determines whether or not the transmitted interrupt request is accepted based on the first vector information V12. Therefore, in this case, the input/output port 1-2 determines that the transmitted interrupt request I2 has been accepted, and outputs the second vector information v22 onto the data bus 6 in synchronization with the recognition response signal INTA. .

The processor 5 takes in the vector information (first vector information V12 and second vector information 22) output in synchronization with the recognition response signal INTA from the data bus 6, and stops the recognition response signal INTA. Interrupt request I2 (input/output capo)
) Starts the interrupt processing routine for 1-2).

The priority encoder 4 and the input/output ports 1-2.

At the same time as the recognition response signal INTA stops, the first
Vector information ■12. Stop the second vector information V22. And 1 interrupt was accepted by the input/output capo) 1-2
also stops 1 interrupt request process 2. and.

The priority encoder 4 encodes information V13 for accepting interrupts from the input/output ports 1-3.

At time t2, when the interrupt processing routine for interrupt request #2 is completed, the first processor 5 sends the recognition response signal INTA to each input/output port 1-1 to 1-4 and priority in order to execute the interrupt for interrupt request #1. The data is sent to the ranked encoder 4 and the same procedure as described above is performed.

Vector information output in synchronization with the recognition response signal INTA (first vector information V131 second vector information v23)
from the data bus 6 and sends the recognition response signal INTA.
1 and starts the interrupt processing routine for interrupt requester 3.

At time t3, before the processor 5 completes the interrupt processing routine for the interrupt requester 3, the input/output yff-)1
If an interrupt request 1 is generated from -1, a 2-interrupt signal INT is sent to the processor 5, and information Vll for accepting an interrupt at the input/output port 1-1 is encoded.

When the processor 5 receives this interrupt signal INT, it interrupts the interrupt processing routine for the interrupt request I3 that is currently being executed, and sends the recognition response signal INTA to each input/output port 1-1 to 1-4 and the priority encoder 4. Send to. Then, the processor 5 processes the vector information (first vector information v1°, second vector information V21) output in synchronization with the recognition response signal INTA according to the same procedure as described above.
) from the data bus 6 and sends the recognition response signal IN.
TA is stopped and an interrupt processing routine for interrupt requester 1 is started.

After that, at time t4, the processor 5 requests 2 interrupts ■1
When the interrupt handling routine for has completed.

The interrupt processing routine for the interrupted interrupt request I3 is restarted, and when the interrupt processing routine for the interrupt request I3 is completed at time t5, processing of the main program is resumed.

Incidentally, in the above embodiment, the case where there is only an input/output port as one interrupt factor is described.

Needless to say, the invention can also be applied to other interrupt factors 2, such as processors and memory control circuits.

〔Effect of the invention〕

As is clear from the above explanation, since the data bus is used to notify all interrupt sources of which interrupt source is to be accepted, more interrupt sources can be used than in the case of the -y′ easy chain circuit. I can do it. Also, because a portion of the data bus is allocated to transmit information about which interrupt source should be accepted, the number of control lines can be reduced.

Configuration becomes easier. Furthermore, since a single interrupt processing circuit can be connected in cascade, there is also the effect that more input/output ports can be connected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of an interrupt processing circuit according to the present invention, and FIG. 2 is a time chart showing an example of the operation of the circuit shown in FIG. 1-1 to 1-4・I/O port, 2...Register. 3... Oscillator, 4... Prioritized encoder, 5... Processor, 6... Data bus. Figure 1

Claims (1)

[Scope of Claims] 1. In a device having a plurality of interrupt factors inside and outside a main unit including a processor. means for receiving an interrupt request generated from the interrupt factor and transmitting an interrupt signal to the processor; Information indicating that an interrupt has been accepted for one of the interrupt factors that generated the interrupt request is sent to the processor in synchronization with a recognition response signal from the processor in response to the interrupt signal. An interrupt processing circuit comprising means for sending part of vector information sent via a data bus to each of the interrupt sources using some lines of the data bus.